Signal transmission system, signal processing method and device, storage medium, electronic equipment and program product

Abstract

The embodiment of the invention provides a signal transmission system, a signal processing method and device, a storage medium, electronic equipment and a program product, and relates to the field of computers.The signal transmission system comprises a control board card and a data board card, and the control board card comprises a control device and a first programmable logic device; the data board card comprises a second programmable logic device and a calculation device; the control device communicates with the first programmable logic device through a control command, the first programmable logic device communicates with the second programmable logic device through a preset communication protocol, and the second programmable logic device is used for analyzing one path of received signals to obtain at least two paths of analyzed signals; and the at least two paths of analyzed signals are forwarded to the calculation device for data processing. Through adoption of the scheme, the problem of low signal transmission efficiency in related technologies is solved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computers, and more specifically, to a signal transmission system, a signal processing method and device, a storage medium, an electronic device, and a program product. Background Art

[0002] In order to achieve efficient server design, new shared technologies are constantly being introduced, including the DC-SCM architecture. In the DC-SCM architecture, some public designs on the server motherboard (data board) are stripped out as an independent board (control board) that can be applied to all server products. This achieves the effect of module reuse, cost reduction and efficiency improvement.

[0003] In the related art, there are a large number of pathways in the control board, while the communication protocol used for signal interaction between the control board and the data board often only supports a small number of pathways, which results in the communication protocol being unable to effectively support complete signal transmission, thereby causing a technical problem of low signal transmission efficiency.

[0004] Therefore, there is a technical problem of low signal transmission efficiency in the related art. Summary of the invention

[0005] The embodiments of the present application provide a signal transmission system, a signal processing method and device, a storage medium, an electronic device, and a program product to at least solve the technical problem of low efficiency of signal transmission in the related art.

[0006] According to an embodiment of the present application, a signal transmission system is provided, the system comprising a control board and a data board, wherein the control board comprises a control device and a first programmable logic device, and the data board comprises a second programmable logic device and a computing device; the control device communicates with the first programmable logic device via a control command, wherein the control command is used to instruct the first programmable logic device to encapsulate at least two signals generated in the control device to obtain a packaged signal, wherein the at least two signals correspond to at least two paths of the control device, the control device comprises M paths, and M is a positive integer greater than 1; the first programmable logic device communicates with the second programmable logic device via a preset The invention relates to a method for communicating with a computer readable medium according to a communication protocol, wherein the first programmable logic device is used to map a signal to a target path on a preset communication protocol, the target path is used to send the signal to the second programmable logic device, the target path is a path determined from N paths supported by the preset communication protocol and matched with at least two paths according to a path matching rule, the path matching rule stores a mapping relationship between each path in the N paths and multiple paths in the M paths, where N is a positive integer less than M; the second programmable logic device is used to parse the received signal to obtain at least two signals after parsing, and forward the at least two signals after parsing to the computing device for data processing.

[0007] According to an embodiment of the present application, a signal processing method is provided, comprising: obtaining at least two signals to be transmitted, wherein the at least two signals come from different paths of a control device, the control device includes M paths, and M is a positive integer greater than 1; determining, according to a path matching rule, a target path that matches at least two paths of the at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, and N is a positive integer less than M; encapsulating the at least two signals to obtain a encapsulated signal, and mapping the signal to a target path, wherein the target path is used to send the signal to a data board.

[0008] According to one embodiment of the present application, a signal processing method is also provided, including: obtaining a received signal, wherein one signal is a signal of different paths of a control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated; parsing the signal to obtain at least two signals after parsing, and storing the at least two signals in a memory, wherein at least two signals carry memory number information; reading signals in the at least two signals in sequence according to the memory number information, and forwarding the read signals to a computing device corresponding to the signals read in a data board.

[0009] According to another embodiment of the present application, a signal processing device is provided, including: an acquisition unit, used to acquire at least two signals to be transmitted, wherein the at least two signals come from different paths of a control device, the control device includes M paths, and M is a positive integer greater than 1; a determination unit, used to determine, according to a path matching rule, a target path that matches at least two paths of the at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, and N is a positive integer less than M; a mapping unit, used to encapsulate the at least two signals to obtain a encapsulated signal, and map the signal to a target path, wherein the target path is used to send the signal to a data board.

[0010] According to another embodiment of the present application, a signal processing device is also provided, including: an acquisition unit, used to acquire a received signal, wherein one signal is a signal of different paths of a control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated; a parsing unit, used to parse the signal to obtain at least two signals after parsing, and store the at least two signals in a memory, wherein at least two signals carry memory number information; a forwarding unit, used to read signals in the at least two signals in sequence according to the memory number information, and forward the read signals to a computing device corresponding to the signals read in a data board.

[0011] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0012] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0013] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method in each embodiment of the present application are implemented.

[0014] Through the embodiments provided by this application, on the control board side, the control device can send control commands to the first programmable logic device to instruct it to encapsulate at least two signals generated within the control device into one signal. This process can dynamically match the signals of M channels (M>1) in the control device to the limited N channels (N<M) in the preset communication protocol, and realize the combination of signals through software, thereby breaking through the limitation of the number of channels of the hardware protocol. The first programmable logic device maps the encapsulated one signal to the target channel in the preset communication protocol based on the preset channel matching rule, and the channel matching rule stores the mapping relationship between the N channels in the preset communication protocol and the M channels in the control device. Through this mapping, even if the preset communication protocol itself only supports a small number of channels, it can effectively transmit the signals of multiple channels in the control board, greatly improving the flexibility and efficiency of signal transmission. On the data board side, the second programmable logic device is responsible for parsing the received one signal into at least two signals, and then forwarding these signals to the computing device for data processing. This process realizes the reverse de-encapsulation of the signal, ensuring the integrity and availability of the multiple signals in the original control board. Through the above method, the problem of limited signal transmission between the control board and the data board in the DC-SCM architecture is effectively solved. It can not only integrate and distribute a large number of signals without changing the existing hardware architecture and communication protocol definition, but also ensure the high speed, high efficiency and low latency of signal transmission, thus achieving the technical effect of improving signal transmission efficiency and solving the technical problem of low signal transmission efficiency in the related art. Description of the Drawings

[0015] Figure 1 is a hardware structure block diagram of a signal processing method according to an embodiment of the present application;

[0016] Figure 2 is a schematic diagram of a signal transmission system according to the present application;

[0017] Figure 3 is a schematic diagram of a signal transmission system according to the present application;

[0018] Figure 4 is a schematic diagram of a signal transmission system according to the present application;

[0019] Figure 5 is a schematic diagram of a signal transmission system according to the present application;

[0020] Figure 6 is a schematic diagram of a signal transmission system according to the present application;

[0021] Figure 7 is a schematic diagram of a signal transmission system according to the present application;

[0022] Figure 8 is a flow chart of a signal processing method according to the present application;

[0023] Fig. 9 is a flow chart of a signal processing method according to the present application;

[0024] Fig.10 is a structural block diagram of a signal processing device according to an embodiment of the present application;

[0025] Fig.11 It is a structural block diagram of a signal processing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] In order to help you more clearly understand the method embodiments provided in the embodiments of the present application, the abbreviations and key terms appearing in the embodiments of the present application are explained below and will not be repeated later.

[0029] DC-SCI: Data Center Secure Control Interface, data center security control interface.

[0030] CPLD: Complex Programmable Logic Device, complex programmable logic device.

[0031] BMC: Baseboard Management Controller, used to manage the server motherboard.

[0032] LVDS: Low Voltage Differential Signaling, a low-amplitude differential signal technology that can transmit serial data at speeds up to several thousand Mbps.

[0033] LTPI: LVDS Tunneling Protocol and Interface, is a communication protocol and interface defined in the DC-SCM2.0 specification. It uses 8 CPLD / FPGA differential IO pins to connect the CPLD / FPGA of the SCM and HPM boards.

[0034] RAM: Random access memory, here refers to the storage area built into the CPLD, which is used to temporarily store data in batches.

[0035] GPIO: General-purpose input / output, general-purpose input and output pin.

[0036] OCP: Open Compute Project, open source computing project, is An activity of the IT industry to share more efficient server and data center designs with the general IT industry.

[0037] DC-SCM: Data Center Secure Control Module, data center security control module.

[0038] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 is a hardware structure block diagram of a signal processing method according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0039] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the mapping relationship in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0040] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0041] As an alternative, Figure 2As shown, a signal transmission system includes a control board 202 and a data board 204, wherein the control board 202 includes a control device 206 and a first programmable logic device 208, and the data board 204 includes a second programmable logic device 210 and a computing device 212; the control device communicates with the first programmable logic device through a control command, wherein the control command is used to instruct the first programmable logic device to encapsulate at least two signals generated in the control device to obtain a packaged signal, wherein the at least two signals correspond to at least two paths of the control device, and the control device includes M paths, where M is a positive integer greater than 1; the first programmable logic device communicates with the second programmable logic device through a control command, wherein the control command is used to instruct the first programmable logic device to encapsulate at least two signals generated in the control device to obtain a packaged signal, wherein the at least two signals correspond to at least two paths of the control device, and the control device includes M paths, where M is a positive integer greater than 1; The devices communicate through a preset communication protocol, wherein a first programmable logic device is used to map a signal to a target path on the preset communication protocol, the target path is used to send a signal to a second programmable logic device, the target path is a path determined from N paths supported by the preset communication protocol and matched with at least two paths according to a path matching rule, the path matching rule stores a mapping relationship between each path in the N paths and multiple paths in the M paths, N is a positive integer less than M; the second programmable logic device is used to parse a received signal to obtain at least two signals after parsing, and forward the at least two signals after parsing to the computing device for data processing.

[0042] Optionally, in this embodiment, the signal transmission system can be applied to, but not limited to, a hardware link expansion transmission scenario based on the LTPI standard protocol. In this scenario, with the development of the Internet of Things, big data, and AI technology, the role of servers is becoming more and more important, and the server industry has become increasingly mature. In order to achieve efficient design of servers, new sharing technologies are constantly being introduced, including the DC-SCM architecture.

[0043] In the DC-SCM architecture, some public designs on the server motherboard (data board) are separated and used as an independent board (control board) to be applied to all server products, thereby achieving the effect of module reuse, cost reduction and efficiency improvement.

[0044] In the related art, there are a large number of pathways in the control board, while the communication protocol used for signal interaction between the control board and the data board often only supports a small number of pathways, which results in the communication protocol being unable to effectively support complete signal transmission, thereby causing a technical problem of low signal transmission efficiency.

[0045] To further illustrate, Figure 3As shown in the figure, the DC-SCM 2.0 architecture in the related art, between the SCM CPLD (programmable logic device in the control board) and the HPM CPLD (programmable logic device in the data board), through 4 pairs of LVDS differential lines, a total of 8 signals, completes the transmission of GPIO, I2C, UART and other signals between the SCM board (control board) and the HPM (data board), thereby completing the signal interconnection between the BMC (control device) on the SCM board and other devices on the HPM board. Figure 4 As shown, this is the standard frame format defined in the LTPI protocol. Figure 4 It can be seen that the LTPI protocol supports the transmission of 16 low-latency GPIO signals, 6 I2C signals, 2 UART signals, and multiple normal-latency GPIO signals.

[0046] Based on the above Figure 3 and Figure 4 It can be found that currently, only 16 low-latency GPIOs, 2 UARTs, and 6 I2Cs can be transmitted between the SCM board and the HPM board. In server design, the demand for low-latency GPIOs is very small, and 16 GPIOs are sufficient to meet the demand. Other normal-latency GPIO signals can be expanded to thousands, which is not a bottleneck at all. However, the BMC chip itself has 16 I2C and 5 UART hardware interfaces. As server system design becomes more and more complex, only using 6 I2C and 2 UART hardware interfaces is far from meeting system design requirements, which leads to the problem that the standard protocol does not match the application scenario.

[0047] For the above problems, through the signal transmission system provided by the embodiments of the present application, on the control board card side, the control device can send a control command to the first programmable logic device to instruct it to encapsulate at least two signals generated within the control device to form one signal. This process can dynamically match the signals of M channels (M>1) in the control device to the limited N channels (N<M) in the preset communication protocol, and realize the combination of signals through software, thus breaking through the limitation of the number of channels of the hardware protocol. The first programmable logic device maps the encapsulated one signal to the target channel in the preset communication protocol based on the preset channel matching rule, and the channel matching rule stores the mapping relationship between the N channels in the preset communication protocol and the M channels in the control device. Through this mapping, even if the preset communication protocol itself only supports a small number of channels, it can effectively transmit the signals of multiple channels in the control board card, greatly improving the flexibility and efficiency of signal transmission. On the data board card side, the second programmable logic device is responsible for parsing the received one signal into at least two signals, and then forwarding these signals to the computing device for data processing. This process realizes the reverse de-encapsulation of the signal, ensuring the integrity and availability of the multiple signals in the original control board card. Through the above method, the problem of limited signal transmission between the control board card and the data board card in the DC-SCM architecture is effectively solved. It can not only integrate and distribute a large number of signals without changing the existing hardware architecture and communication protocol definition, but also ensure the high speed, high efficiency and low latency of signal transmission, thus achieving the technical effect of improving signal transmission efficiency and solving the problem of mismatch between the above standard protocol and the application scenario.

[0048] Optionally, in this embodiment, the control board card (Control Board Card, abbreviated as SCM) bears the management functions of the server, including monitoring, configuration and control, etc., and includes key components such as a control device (also known as a baseboard management controller, BMC) and a first programmable logic device (SCM CPLD) for data encapsulation and transmission.

[0049] Optionally, in this embodiment, the data board card (Data Board Card, abbreviated as HPM) is used to process data calculation and storage functions, including core components such as a CPU and a memory, and includes a second programmable logic device (HPM CPLD) for data transmission and parsing.

[0050] Optionally, in this embodiment, the control device is the BMC on the control board card, which is used for remote monitoring and management of the server. In this embodiment, there can be but are not limited to multiple channels on the control device, and there can be but are not limited to multiple channels for transmitting I2C signals and multiple channels for transmitting UART signals.

[0051] Optionally, in this embodiment, the first programmable logic device is a CPLD on a control board for signal encapsulation and conversion; the second programmable logic device is a CPLD on a data board for signal reception, analysis and forwarding.

[0052] Optionally, in this embodiment, the computing device is a central processing unit (CPU) or other data processing components on a data board, which is responsible for receiving and processing data signals transmitted from the control board.

[0053] Optionally, in this embodiment, the preset communication protocol may be, but is not limited to, the LTPI protocol, which is used for internal communication within the server and is used to define how to transmit data between the control board and the data board via LVDS differential signal technology.

[0054] Optionally, in this embodiment, on the control board side, the control device sends a control command to the first programmable logic device to instruct it to encapsulate the multiple signals (M channels, M is a positive integer greater than 1) generated in the control device. For example, assuming that the control device (BMC) has 16 I2C channels and 5 UART channels, but in the current LTPI protocol, each board can only support 6 I2C and 2 UART transmissions. In this case, the control command will instruct the first programmable logic device to combine the signals of the channels to form signals that can be mapped to a smaller number of channels (N channels) on the LTPI protocol.

[0055] Optionally, in this embodiment, the first programmable logic device encapsulates at least two signals generated in the control device to obtain an encapsulated signal, maps the signal to a target path on a preset communication protocol, and the target path is used to send the signal to the second programmable logic device. The target path is a path that is determined from N paths supported by the preset communication protocol and matches at least two paths according to a path matching rule, and the path matching rule stores a mapping relationship between each path in the N paths and multiple paths in the M paths.

[0056] It should be noted that a path matching rule is established in advance, wherein the path matching rule indicates a mapping relationship between N paths and M paths, the first i paths among the N paths correspond to P+1 paths among the M paths, the last Ni paths correspond to P paths among the M paths, P is the quotient of N divided by M, and i is a positive integer less than or equal to N.

[0057] To further illustrate, assume that the control device (BMC) has 16 channels (assumed to be a1, a2...a16) for a certain type of data transmission, but in the current LTPI protocol, there are only 6 channels (assumed to be b1, b2...b6) that support this type of data transmission. The following channel matching rules can be established, but are not limited to: channels b1, b2, b3 and b4 correspond to three channels among the 16 channels, that is, channel b1 corresponds to channels a1, a2 and a3, channel b2 corresponds to channels a4, a5 and a6, channel b3 corresponds to channels a7, a8 and a9, channel b4 corresponds to channels a10, a11 and a12, channels b5 and b6 correspond to two channels among the 16 channels, channel b5 corresponds to channels a13 and a14, and channel b6 corresponds to channels a15 and a16.

[0058] It is understandable that based on the above-mentioned channel matching rules, it is possible to averagely map a greater number of channels on the control device based on channels supported by a smaller number of protocols, thereby making subsequent multi-channel signal encapsulation more balanced and improving signal transmission efficiency.

[0059] Optionally, in this embodiment, on the data board side, the second programmable logic device is responsible for receiving and parsing a signal transmitted via a preset communication protocol, restoring it into at least two signals, and then forwarding it to a computing device (such as a CPU) for further data processing. For example, assuming that the received signal represents data of I2C channels 1, 2, and 3 transmitted from the control board BMC via the LTPI protocol I2C channel 1, the second CPLD will parse the data, restore it into three independent I2C signals, and send them to the I2C slave device on the data board for processing.

[0060] Through the embodiments provided in this application, on the control board side, the control device can send control commands to the first programmable logic device, instructing it to encapsulate at least two signals generated within the control device to form one signal. This process can dynamically match the signals of M channels (M>1) in the control device to the limited N channels (N<M) in the preset communication protocol, and realize the combination of signals through software, thus breaking through the limitation of the number of channels of the hardware protocol. The first programmable logic device maps the encapsulated one signal to the target channel in the preset communication protocol based on the preset channel matching rule, and the channel matching rule stores the mapping relationship between the N channels in the preset communication protocol and the M channels in the control device. Through this mapping, even if the preset communication protocol itself only supports a small number of channels, the effective transmission of multiple-channel signals in the control board can be realized, greatly improving the flexibility and efficiency of signal transmission. On the data board side, the second programmable logic device is responsible for parsing the received one signal into at least two signals, and then forwarding these signals to the computing device for data processing. This process realizes the reverse de-encapsulation of the signal, ensuring the integrity and availability of the multiple-channel signals in the original control board. Through the above method, the problem of limited signal transmission between the control board and the data board in the DC-SCM architecture is effectively solved. It can not only integrate and distribute a large number of signals without changing the existing hardware architecture and communication protocol definition, but also ensure the high speed, high efficiency and low latency of signal transmission, thus achieving the technical effect of improving signal transmission efficiency.

[0061] As an alternative solution, the first programmable logic device includes M first parsing modules, where the M first parsing modules are used to parse the signals of the M channels to obtain the data information corresponding to the signals of the M channels, and the M first parsing modules include at least two first parsing modules for parsing at least two signals.

[0062] Optionally, in this embodiment, within the first programmable logic device of the control board, there are M first parsing modules, which are used to parse the signals of M channels in the control device (BMC) respectively to obtain relevant data information.

[0063] Optionally, in this embodiment, each first parsing module corresponds to one channel of the BMC and is responsible for parsing the signal received from this channel and extracting its data information. For example, if the BMC has 16 I2C channels and 5 UART channels, then 16 modules for parsing I2C signals and 5 modules for parsing UART signals are set in the first programming logic device.

[0064] Through the embodiments provided by the present application, by setting and executing the functions of the M first parsing modules in the first programming logic device, it is possible to overcome the limitation of the number of channels in the communication protocol and realize the effective transmission of all channel signals of the BMC. For example, the originally limited I2C and UART signals can now be transmitted through a smaller number of hardware links, which improves the efficiency of signal transmission and the overall performance of the system. In addition, this solution maintains compatibility with existing communication protocols.

[0065] As an optional solution, the first programmable logic device includes M first storage modules, wherein the M first storage modules are used to store data information corresponding to signals of M paths, and the M first storage modules include at least two first storage modules for storing data information corresponding to at least two signals.

[0066] Optionally, in this embodiment, the M first storage modules in the first programmable logic device correspond to the M channels of the BMC respectively, and are used to store the signal data information extracted by the parsing module. For example, if the BMC has 16 I2C channels and 5 UART channels, the first CPLD will be provided with 16 first storage modules for storing I2C signal data information and 5 first storage modules for storing UART signal data information.

[0067] Optionally, in this embodiment, each first storage module is responsible for storing the data information extracted by its corresponding parsing module. For at least two signals beyond the direct support range of the LTPI protocol, the corresponding at least two first storage modules will store the data information of these signals for subsequent combination and packaging. For example, for I2C channels 4, 5, and 6 that need to be transmitted through combination, their data information will be stored in these three first storage modules respectively, and will then be selected to be combined into one signal to meet the transmission requirements of the LTPI protocol.

[0068] Through the embodiments provided by the present application, signal data information can be effectively stored and managed without changing the hardware topology, especially for signal data that needs to be transmitted through combination. This mechanism ensures the complete storage of all data information and provides important data resources for subsequent data combination and packaging, thereby achieving the improvement of signal transmission efficiency and optimization of system performance without violating the preset communication protocol.

[0069] As an optional solution, the first programmable logic device includes a packaging module, wherein the packaging module is used to capture data information corresponding to signals of M paths from the M first storage modules in sequence according to storage number information of the M first storage modules, and combine the data information corresponding to the signals of the M paths according to a target format to obtain combined first packaged data.

[0070] Optionally, in this embodiment, in the first programmable logic device of the control board, the encapsulation module is used to sequentially capture the stored data information according to the storage number information of the first storage module, and perform data combination to form the first encapsulated data that meets the transmission requirements of the preset communication protocol. The storage number information is used to indicate the unique identifier of the data information corresponding to each signal in the first storage module, which is used for the encapsulation module to accurately capture and combine the data information. The target format is used to indicate the data combination format that meets the transmission requirements of the preset communication protocol. The encapsulation module will combine the data information according to this format to achieve efficient transmission of the signal.

[0071] As an optional solution, the encapsulation module includes a first encapsulation submodule, wherein the first encapsulation submodule is used to capture first data information corresponding to at least two I2C signals from M first storage modules, and combine the first data information according to a first target format to obtain combined first encapsulation sub-data, wherein the first data information includes first storage number information of at least two I2C signals in the first storage module, storage address information and I2C data information of the control device, and the first target format is used to indicate that the first storage number information, storage address information and I2C data information of each I2C signal are combined in sequence; the encapsulation module includes a second encapsulation submodule, wherein the second encapsulation submodule is used to capture second data information corresponding to at least two UART signals from the M first storage modules, and combine the second data information according to a second target format to obtain combined second encapsulation sub-data, wherein the second data information includes second storage number information and UART data information of at least two UART signals in the first storage module, and the second target format is used to indicate that the second storage number information and UART data information of each UART signal are combined in sequence.

[0072] Optionally, in this embodiment, in the first programmable logic device on the control board side, the first packaging submodule is responsible for capturing the first data information corresponding to at least two I2C signals from the M first storage modules. This data information includes the storage number of the signal, the storage address in the control device (BMC), and the specific data content of the signal. For example, for the I2C channels 4, 5, and 6 that need to be transmitted, the first packaging submodule will capture the data information stored in the first storage modules 4, 5, and 6, including the storage number, storage address, and signal data.

[0073] Next, the first encapsulation submodule will combine the captured first data information according to the first target format. The first target format stipulates that the data should be combined in the order of storage number, storage address and signal data to form the first encapsulation sub-data. For example, the first encapsulation submodule will generate data including: storage number (corresponding to channel 4), storage address (address of channel 4 in BMC), signal data (data of channel 4), then storage number (corresponding to channel 5), storage address (address of channel 5 in BMC), signal data (data of channel 5), and finally storage number (corresponding to channel 6), storage address (address of channel 6 in BMC), signal data (data of channel 6), and all data are combined into a data packet that meets the transmission requirements.

[0074] Optionally, in this embodiment, the second packaging submodule processes the data information of the UART signal. It captures the second data information corresponding to at least two UART signals from the M first storage modules, including storage numbers and signal data. For example, for the data of UART channels 1 and 2, the second packaging submodule will capture the storage numbers and signal data from the first storage modules 1 and 2.

[0075] Then, the second encapsulation submodule combines the second data information according to the second target format to generate second encapsulation sub-data. The second target format indicates that the storage number and the signal data should be combined in sequence to form the second encapsulation sub-data. For example, the second encapsulation sub-data includes: a storage number (corresponding to UART channel 1), signal data (data of UART channel 1), followed by a storage number (corresponding to UART channel 2) and corresponding signal data (data of UART channel 1), and all the data are combined into a data packet that meets the transmission requirements.

[0076] Through the embodiments provided in this application, through detailed operations at the software level, efficient integration and packaging of I2C and UART signal data are achieved, ensuring that all signal data can be transmitted in a compatible and efficient manner even in an environment where the number of communication protocol channels is limited.

[0077] As an optional solution, the first programmable logic device includes a main control module, wherein the main control module is used to add protocol address information supported by a preset communication protocol before the first encapsulated sub-data to obtain third encapsulated sub-data; the first programmable logic device includes a mapping module, wherein the mapping module is used to map the second encapsulated data to N paths supported by the preset communication protocol, wherein the second encapsulated data includes second encapsulated sub-data and third encapsulated sub-data, and the second encapsulated data corresponding to at least two signals are mapped to a target path among the N paths.

[0078] Optionally, in this embodiment, in the first programmable logic device on the control board side, the main control module adds protocol address information (LTPI-2IC address) supported by a preset communication protocol (such as LTPI protocol) before the first package sub-data (containing data information of at least two I2C signals) to form third package sub-data.

[0079] It is understandable that since the protocol address information is the starting point identifier of data transmission, it ensures that the data can be correctly identified and processed. For example, for the combined I2C signal data, the main control module will add the I2C address information of the LTPI protocol before the data to form the third package sub-data for transmission.

[0080] Optionally, in this embodiment, the mapping module is responsible for mapping the second encapsulated data to N paths supported by the preset communication protocol, where the second encapsulated data contains all encapsulated data, including the second encapsulated sub-data and the third encapsulated sub-data, ensuring that the data can be transmitted through the correct hardware path. Even if the amount of data exceeds the amount directly supported by the protocol, the efficiency and accuracy of the transmission can be guaranteed through combination and mapping.

[0081] Through the embodiments provided in the present application, through the collaborative work of the main control module and the mapping module, the server can ensure that all signal data can not only be transmitted in the correct format, but also can be correctly mapped to the hardware path supported by the preset communication protocol, thereby achieving efficient, accurate and compatible signal transmission.

[0082] As an optional solution, the second programmable logic device includes N second analysis modules, wherein the N second analysis modules are used to analyze signals sent by multiple N paths to obtain data information corresponding to the signals sent by the N paths, the data information corresponding to the signals sent by the N paths corresponds to the data information of the signals generated by the M paths, and the N second analysis modules include a second analysis module for analyzing one signal.

[0083] Optionally, in this embodiment, N second parsing modules are designed in the second programmable logic device on the data board side, and each second parsing module is responsible for parsing a signal through a preset communication protocol (such as LTPI protocol) to restore the signal data information generated by the original M paths. This design ensures that the receiving end can accurately understand and process the data sent by the control board side through combination and encapsulation, thereby achieving efficient decoding and restoration of the signal.

[0084] It is understandable that the data information parsed by the N second parsing modules will be used to restore the signal data information generated by the original M channels. This process is carried out according to the data encapsulation rules on the control board side and the format defined by the protocol, ensuring accurate data recovery. For example, if the control board side combines the data of I2C channels 4, 5 and 6 and sends them through I2C channel 1 of the LTPI protocol, the second parsing module on the data board side will parse this signal and restore the original data information of I2C channels 4, 5 and 6, thereby achieving complete recovery of the signal data.

[0085] Through the embodiments provided in the present application, through the design of N second parsing modules, the data board side can accurately parse and restore the signal data information sent by the control board side. Even if the number of these signals exceeds the number of channels directly supported by the preset communication protocol, the integrity and accuracy of the data can be ensured, thereby achieving efficient and compatible signal transmission.

[0086] As an optional solution, the second editable logic device includes M second storage modules, wherein the M second storage modules are used to store data information of signals generated by M paths, and the M second storage modules include at least two second storage modules for storing data information corresponding to at least two signals.

[0087] Optionally, in this embodiment, in the second editable logic device on the data board side, M second storage modules are designed to match the number of signals generated by the M paths on the control board side. The function of these storage modules is to store the signal data information parsed by the N second parsing modules to ensure that the data can be accurately recorded at the receiving end for subsequent processing.

[0088] Optionally, in this embodiment, each second storage module is responsible for storing the signal data information generated by a corresponding control board side channel after being parsed by the second parsing module. For example, for the data information of I2C channels 4, 5 and 6 transmitted from the control board side through combination and encapsulation, the data board side will be provided with a corresponding storage module for storing the parsed data information of I2C channels 4, 5 and 6.

[0089] Through the embodiments provided in the present application, by setting M second storage modules on the data board side, the server designer can ensure that all signal data information can be accurately recorded at the receiving end, without being affected by the signal combination and packaging on the control board side, thereby maintaining the integrity of the signal transmission.

[0090] As an optional solution, the second editable logic device includes an identification module, wherein the identification module is used to identify the storage number information included in the data information corresponding to the signals sent by the N paths;

[0091] The second editable logic device includes a sending module, wherein the sending module is used to store the signals sent by the N paths into the corresponding second storage module according to the storage number information.

[0092] Optionally, in this embodiment, on the data board side, the identification module first parses the received signal data information and identifies the storage number information contained therein. The storage number information is a key identifier used by the data board side to distinguish the data of different control board side channels. Through this information, the identification module can classify the data information of different channels and prepare to store them in the corresponding second storage module.

[0093] For example, when receiving data sent through LTPI protocol I2C channel 1, the identification module will identify the storage number information in the data packet, which corresponds to the original I2C channels 4, 5 and 6 on the control board side. By identifying the storage number information, the identification module can distinguish the signal channel to which the data information originally belongs, and prepare for subsequent distribution and storage.

[0094] Optionally, in this embodiment, the sending module is responsible for storing the parsed signal data information into a corresponding storage module in the M second storage modules according to the storage number information obtained by the identification module. This process ensures that the data can be accurately classified and stored in the storage module corresponding to the original signal path on the control board side, which is convenient for subsequent processing or transmission to the corresponding hardware device.

[0095] For example, if the identification module recognizes that the storage number information in the data packet corresponds to I2C channels 4, 5 and 6 on the control board side, the sending module will ensure that these data information are stored in the second storage modules 4, 5 and 6 on the data board side, respectively, restoring the data layout of the original signal path, facilitating subsequent signal distribution and processing.

[0096] Through the embodiments provided in the present application, through the collaborative work of the identification module and the sending module, the server designer can ensure that all received signal data information can be accurately classified and stored in M ​​second storage modules, corresponding to the original signal path on the control board side, thereby maintaining the integrity and accuracy of signal transmission.

[0097] As an optional solution, the second editable logic device includes a forwarding module, wherein the forwarding module is used to read data information from the M second storage modules in sequence according to the storage number information, and forward the read data information to the corresponding computing device for data processing.

[0098] Optionally, in this embodiment, in the second editable logic device on the data board side, the forwarding module reads data information from the second storage module in sequence according to the storage number information. The storage number information corresponds to the original signal path on the control board side, so that the forwarding module can accurately identify and read the data information of the corresponding path. Subsequently, the forwarding module forwards the read data information to the computing device (such as a chip) for further data processing.

[0099] The computing device (such as a chip) is responsible for receiving the data information forwarded by the forwarding module and performing further data processing. It can be, but is not limited to, communicating with external hardware devices, such as interacting with I2C slave devices or UART slave devices, completing data parsing, processing or storage, thereby realizing the effective application of signal data in the system.

[0100] Through the embodiments provided in the present application, based on the reading and forwarding mechanism of the forwarding module, the server designer can ensure that all signal data information can be accurately forwarded to the computing device for data processing after being received, parsed, classified and stored, thereby realizing the complete transmission and application of signal data.

[0101] As an optional solution, the above signal transmission system is applied to the I2C and UART hardware link expansion transmission scenarios based on the LTPI standard protocol to solve the problem that the number of I2C and UART channels included in the current LTPI standard protocol cannot meet the design requirements of the server system. While keeping the current hardware topology and LTPI standard frame definition unchanged, the number of I2C and UART hardware links in the LTPI protocol application scenario can be expanded by only modifying the CPLD code.

[0102] To further illustrate, Figure 5 The DC-SCM 2.0 architecture after optimization in this embodiment is shown in FIG. This embodiment includes the following two parts:

[0103] Part 1: SCM CPLD code modification. Figure 3 As shown in the figure, the original LTPI protocol uses transparent transmission to transmit I2C and UART, so the number of I2C and UART hardware links that can interact between the SCM board and the HPM board is limited by the number of I2C and UART channels included in the LTPI protocol. Figure 5 In the process, by modifying the SCM CPLD code and adding the I2C parsing module and the UART parsing module, the data of the multi-channel I2C and UART hardware links of the BMC can be parsed and combined into one channel of I2C and UART, and then occupy one channel of I2C and UART channels in the LTPI protocol for transmission.

[0104] Part 2: HPM CPLD code modification. Figure 5 In the process, by modifying the HPM CPLD, adding I2C parsing module and UART parsing module, the one-way I2C and UART channels in the LTPI protocol are parsed, and the multi-way I2C data and UART data are restored according to the established rules, and finally mapped into multi-way I2C and UART hardware links, which are connected to the slave devices on the HPM board.

[0105] Specifically, combined Figure 6 , the above first part is explained in detail.

[0106] BMC has 16 I2C and 5 UART hardware links, and the LTPI protocol has only 6 I2C channels and 2 UART channels. In the application scenario where all hardware links are interconnected, it is necessary to redistribute the correspondence between each I2C and UART channel in the LTPI protocol and the actual I2C and UART hardware links. Here, the I2C1, 2, 3, and 4 channels of the LTPI protocol correspond to the 3 I2C hardware links of the BMC respectively, and the I2C5 and 6 of the LTPI protocol correspond to the 2 I2C link hardware links of the BMC respectively. UART is divided in a similar way.

[0107] like Figure 6 As shown, the design principles of the I2C channel 1 of the LTPI protocol and its corresponding I2C hardware links 1 / 2 / 3 of the BMC are analyzed in detail.

[0108] like Figure 6 In step ①, write CPLD code to implement three I2C parsing modules to parse the data of the three I2C hardware links of the BMC.

[0109] like Figure 6 In step ②, the parsed I2C address and I2C data are stored in the corresponding RAM according to the I2C hardware link number. The data format in each RAM is shown in Table 1.

[0110] Table 1

[0111]

[0112] like Figure 6 In step ③, the data in the RAM is polled in sequence, and new I2C data to be sent is composed in the form of RAM number (BMC's I2C hardware link number) + BMCI2C address + I2C data.

[0113] like Figure 6In step ④, write CPLD code to implement 1-way I2C Master (equivalent to I2C framing), and send new I2C data in sequence. The sending format is: LTPI I2C address + RAM number + BMCI2C address + I2C data.

[0114] like Figure 6 In step ⑤, map the I2C Master signal implemented by the CPLD code to the I2C channel 1 in the LTPI protocol.

[0115] Specifically, combined Figure 7 , the above second part is explained in detail.

[0116] like Figure 7 In step ①, write CPLD code to implement an I2C parsing module to parse the I2C data of I2C channel 1 in the LTPI protocol.

[0117] like Figure 7 In step ②, the frame format "LTPI I2C address + RAM number + BMCI2C address + I2C data" is parsed, and the BMCI2C address + I2C data are stored in the corresponding RAM according to the RAM number. The data format in each RAM is shown in Table 1.

[0118] like Figure 7 In step ③, read the data in the RAM in sequence according to the RAM number (the I2C hardware link number of the BMC), implement three I2C Masters, map them to the hardware I2C link under the CPLD, and complete the communication with the I2C slave device. The data format is: I2C address + I2C data.

[0119] In summary, by modifying the SCM CPLD and HPMCPLD codes, the I2C hardware links of the three BMCs are completed. Through one LTPI I2C channel, communication with three I2C slave devices is achieved. Other I2C links and UART links are designed using the same principle.

[0120] Through the embodiments provided in this application, the number of I2C and UART hardware links can be expanded in the LTPI protocol application scenario by only modifying the CPLD code, while the current hardware topology and LTPI standard frame definition remain unchanged, thereby solving the problem that the number of I2C and UART channels included in the current LTPI standard protocol cannot meet the design requirements of the server system. The LTPI protocol is truly used in products to achieve the purpose of reducing costs and increasing efficiency.

[0121] As an alternative, Figure 8 As shown, a signal processing method comprises:

[0122] S802, obtaining at least two signals to be transmitted, wherein the at least two signals come from different paths of a control device, the control device includes M paths, and M is a positive integer greater than 1;

[0123] S804, determining, according to a path matching rule, a target path that matches at least two paths of at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, where N is a positive integer less than M;

[0124] S806, encapsulate at least two signals to obtain an encapsulated signal, and map the signal to a target channel, wherein the target channel is used to send the signal to a data board.

[0125] Optionally, in this embodiment, the at least two signals to be transmitted may be, but are not limited to, different paths from a control device (such as a BMC), and may be, but are not limited to, need to be transmitted through the LTPI protocol. Path matching rule: A set of mapping relationships stored in the system, which defines a mapping relationship between each path in the N paths supported by a preset communication protocol (such as the LTPI protocol) and at least two paths in the M paths of the control device.

[0126] Optionally, in this embodiment, the target path: a path for transmitting the encapsulated signal determined from N paths supported by a preset communication protocol according to a path matching rule.

[0127] Optionally, in this embodiment, the data board is a computing device for receiving the packaged signal and performing data processing, such as a BMC or other computing device on an HPM board.

[0128] Optionally, in this embodiment, at the initial stage of signal transmission, at least two signals to be transmitted are obtained from the BMC chip, and these signals come from M paths of the BMC chip, where M is a positive integer greater than 1, indicating that the BMC chip has multiple signal paths, but not all signals of all paths can be directly transmitted through the preset communication protocol.

[0129] For example, the BMC chip may have 16 I2C channels and 5 UART channels, but the LTPI protocol only supports 6 I2C channels and 2 UART channels. Therefore, it is necessary to select at least two signals from these M channels for transmission.

[0130] Optionally, in this embodiment, according to a preset path matching rule, a target path that matches at least two signals to be transmitted is determined from N paths supported by a preset communication protocol. The path matching rule stores the mapping relationship between each of the N paths and at least two of the M paths. N is a positive integer less than M, that is, through the mapping rule, it is determined which paths of the LTPI protocol will be used to transmit the signals of which BMC chips.

[0131] Optionally, in this embodiment, the at least two obtained signals are encapsulated to form one signal, and then this signal is mapped to the determined target path for transmission. This process ensures that even if the number of signals exceeds the number of paths directly supported by the preset communication protocol, efficient signal transmission can be achieved through software-level optimization.

[0132] Through the embodiments provided in this application, the signals of M paths (M>1) in the control device can be dynamically matched to the limited N paths (N<M) on the preset communication protocol, and signal combination is realized through software, thereby breaking through the limitation of the number of paths of the hardware protocol. The encapsulated single signal is mapped to the target path on the preset communication protocol based on the preset path matching rule. The path matching rule stores the mapping relationship between the N paths on the preset communication protocol and the M paths in the control device. Through this mapping, even if the preset communication protocol itself only supports a small number of paths, effective transmission of multiple path signals in the control board can be achieved, greatly improving the flexibility and efficiency of signal transmission.

[0133] As an alternative solution, encapsulating at least two signals to obtain an encapsulated single signal includes:

[0134] Performing a parsing operation on at least two signals to obtain the data information of the at least two signals;

[0135] Storing the data information of the at least two signals in a memory and generating memory number information of the at least two signals;

[0136] Based on the memory number information and data information of each of the at least two signals, performing an ordered combination to obtain one signal.

[0137] Optionally, in this embodiment, first perform a parsing operation on the at least two obtained signals, decompose each signal, and extract the data information therein, such as the I2C address, data content, or UART data stream. This process can respectively identify the specific content of each signal and prepare for subsequent encapsulation and transmission.

[0138] Optionally, in this embodiment, the extracted data information will be stored in a memory within the system. At the same time, memory number information is generated for the data information of each signal, and these number information are used to accurately distinguish and locate the data information of different signals in subsequent combinations. The memory number information is a key identifier in the packaging process, ensuring the orderliness and traceability of the signal data.

[0139] Optionally, in this embodiment, according to the memory number information and the data information, an orderly combination is performed to create a packaged signal. This process usually follows certain rules, such as the priority of the signal source path, time sequence or other logical rules, to ensure that the packaged signal can accurately reflect the data information and order of the original signal, and is convenient for transmission through a preset communication protocol.

[0140] Through the method provided in the embodiment of the present application, at least two signals obtained from the BMC chip can be effectively encapsulated into one signal, overcoming the limitation of the number of hardware protocol channels, achieving efficient processing and accurate transmission of signal data, and providing solid technical support for improving the communication capabilities of the server system. This mechanism not only improves the efficiency and accuracy of signal transmission, but also enhances the flexibility of signal processing, which helps to optimize the signal transmission link without changing the hardware architecture.

[0141] As an optional solution, a path matching rule is established in advance, wherein the path matching rule indicates a mapping relationship between N paths and M paths, the first i paths among the N paths correspond to P+1 paths among the M paths, the last Ni paths correspond to P paths among the M paths, P is the quotient of N divided by M, and i is a positive integer less than or equal to N.

[0142] To further illustrate, assume that the control device (BMC) has 16 channels (assumed to be a1, a2...a16) for a certain type of data transmission, but in the current LTPI protocol, there are only 6 channels (assumed to be b1, b2...b6) that support this type of data transmission. The following channel matching rules can be established, but are not limited to: channels b1, b2, b3 and b4 correspond to three channels among the 16 channels, that is, channel b1 corresponds to channels a1, a2 and a3, channel b2 corresponds to channels a4, a5 and a6, channel b3 corresponds to channels a7, a8 and a9, channel b4 corresponds to channels a10, a11 and a12, channels b5 and b6 correspond to two channels among the 16 channels, channel b5 corresponds to channels a13 and a14, and channel b6 corresponds to channels a15 and a16.

[0143] Through the embodiments provided in the present application, based on the above-mentioned path matching rules, it is possible to averagely map a greater number of paths on the control device based on a smaller number of paths supported by the protocol, thereby making subsequent multi-channel signal encapsulation more balanced and improving signal transmission efficiency.

[0144] As an alternative, Fig. 9 As shown, a signal processing method comprises:

[0145] S902, obtaining a received signal, wherein the signal is a signal of a different path of the control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated;

[0146] S904, parsing one signal to obtain at least two signals after parsing, and storing the at least two signals in a memory, wherein the at least two signals carry memory number information;

[0147] 906 , reading signals in at least two channels in sequence according to the memory serial number information, and forwarding the read signals to a computing device corresponding to the read signals in the data board.

[0148] Optionally, in this embodiment, one signal is a signal that is encapsulated by the control device and forwarded through a path supported by a preset communication protocol, and includes signal data information from different paths of the control device.

[0149] Optionally, in this embodiment, the memory number information is a unique identifier assigned to each channel of original signal data information during the signal encapsulation process, and is used to accurately identify and classify the data information of the original signal when the receiving end parses the signal.

[0150] Optionally, in this embodiment, the computing device is a computing device in a data board that is responsible for processing the parsed signal data, such as a BMC or other specific hardware on a server motherboard.

[0151] Optionally, in this embodiment, a signal forwarded by a path supported by a preset communication protocol is first obtained. This signal is formed by encapsulating multiple different path signals of the control device and contains signal data information from multiple paths.

[0152] Optionally, in this embodiment, the acquired signal is parsed to restore data information of at least two original signals. This process usually requires distinguishing and identifying the source path and data content of the original signal according to the memory number information carried by the signal.

[0153] The parsed signal data information will be stored in the memory and carry the memory number information for subsequent reading and forwarding operations.

[0154] Optionally, in this embodiment, at least two channels of signal data information stored in the memory are read in sequence according to the memory number information, and the read signal data are forwarded to a corresponding computing device in the data board for processing.

[0155] Through the embodiments provided in the present application, the receiving system on the data board side can ensure that the data information of all encapsulated signals can be accurately parsed and orderly forwarded to the computing device in the data board for processing, overcoming the limitation of the number of hardware protocol paths, and realizing efficient processing and accurate application of signal data, which not only improves the efficiency and accuracy of signal data processing, but also enhances the flexibility of signal processing.

[0156] As an optional solution, one signal is parsed to obtain at least two signals after parsing, including:

[0157] Performing format analysis on one signal to obtain a frame format of the signal, wherein the frame format is composed of memory number information and data information of each signal in at least two signals;

[0158] According to the frame format, one signal is divided to obtain at least two signals.

[0159] Optionally, in this embodiment, the frame format of one signal is parsed to determine the structure and organization of the signal data, thereby providing a basis for subsequent signal division.

[0160] Optionally, in this embodiment, the frame format is used to indicate the format followed during signal transmission, and includes signal data information and memory number information, which is used to describe the structure and source of the signal data.

[0161] Optionally, in this embodiment, a signal forwarded by a path supported by a preset communication protocol is first format parsed to determine its frame format. The frame format is based on the memory number information and data information allocated to each original signal when the signal is previously encapsulated. This information has been encoded in the frame format when the signal is encapsulated, and is used to describe the structure and source of the signal data.

[0162] Optionally, in this embodiment, according to the frame format obtained by parsing, one signal is divided to restore at least two original signals. This process is based on the memory number information in the frame format, and the data information of one signal is restored to multiple original signals, each signal corresponding to a specific computing device, so as to perform subsequent data processing.

[0163] Through the embodiments provided by the present application, the system can ensure that one received encapsulated signal can be accurately restored to at least two original signals, and then accurately perform subsequent data processing and application. This mechanism not only improves the efficiency and accuracy of signal data processing, but also enhances the flexibility of signal processing.

[0164] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0165] In the present embodiment, a signal processing device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0166] Fig.10 is a structural block diagram of a signal processing device according to an embodiment of the present application, such as Fig.10 As shown, the device comprises:

[0167] An acquisition unit 1002 is used to acquire at least two signals to be transmitted, wherein the at least two signals come from different paths of the control device, the control device includes M paths, and M is a positive integer greater than 1;

[0168] A determining unit 1004 is used to determine, according to a path matching rule, a target path that matches at least two paths of at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, where N is a positive integer less than M;

[0169] The mapping unit 1006 is used to encapsulate at least two signals to obtain an encapsulated signal, and map the signal to a target channel, wherein the target channel is used to send the signal to a data board.

[0170] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0171] As an optional solution, the mapping unit 1006 includes:

[0172] An analysis module, used to perform an analysis operation on at least two signals to obtain data information of at least two signals;

[0173] A generating module, used for storing data information of at least two signals in a memory, and generating memory number information of at least two signals;

[0174] The combination processing module is used to perform orderly combination based on the memory number information and data information of each signal in at least two signals to obtain one signal.

[0175] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0176] As an optional solution, the above device also includes:

[0177] An establishing unit is used to establish a path matching rule, wherein the path matching rule indicates a mapping relationship between N paths and M paths, the first i paths in the N paths correspond to P+1 paths in the M paths, the last Ni paths correspond to P paths in the M paths, P is the quotient of N divided by M, and i is a positive integer less than or equal to N.

[0178] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0179] Fig.11 is a structural block diagram of a signal processing device according to an embodiment of the present application, such as Fig.11 As shown, the device comprises:

[0180] The acquisition unit 1102 is used to acquire a received signal, wherein the signal is a signal of a different path of the control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated;

[0181] The parsing unit 1104 is used to parse one signal to obtain at least two signals after parsing, and store the at least two signals in a memory, wherein the at least two signals carry memory number information;

[0182] The forwarding unit 1106 is used to read the signals in at least two channels in sequence according to the memory serial number information, and forward the read signals to the computing device corresponding to the read signals in the data board.

[0183] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0184] As an optional solution, the parsing unit 1104 includes:

[0185] A parsing module, used for format parsing one signal to obtain a frame format of the signal, wherein the frame format is composed of memory number information and data information of each signal in at least two signals;

[0186] The division module is used to divide one signal according to the frame format to obtain at least two signals.

[0187] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0188] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0189] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0190] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0191] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0192] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0193] An embodiment of the present application further provides a computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores the computer program product, and when the computer program is executed by a processor, the steps of the method in each embodiment of the present application are implemented.

[0194] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0195] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0196] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A signal transmission system, characterized in that: The system comprises a control board and a data board, wherein the control board comprises a control device and a first programmable logic device, and the data board comprises a second programmable logic device and a computing device; The control device communicates with the first programmable logic device through a control command, wherein the control command is used to instruct the first programmable logic device to encapsulate at least two signals generated in the control device to obtain a packaged signal, wherein the at least two signals correspond to at least two paths of the control device, and the control device includes M paths, where M is a positive integer greater than 1; The first programmable logic device communicates with the second programmable logic device through a preset communication protocol, wherein the first programmable logic device is used to map the signal to a target path on the preset communication protocol, the target path is used to send the signal to the second programmable logic device, the target path is a path determined from N paths supported by the preset communication protocol according to a path matching rule and matching the at least two paths, the path matching rule stores a mapping relationship between each path in the N paths and multiple paths in the M paths, and N is a positive integer less than M; The second programmable logic device is used to parse the received signal to obtain at least two signals after parsing, and forward the at least two signals after parsing to the computing device for data processing.

2. The system according to claim 1, characterized in that The first programmable logic device includes M first analysis modules, wherein the M first analysis modules are used to analyze the signals of the M paths to obtain data information corresponding to the signals of the M paths, and the M first analysis modules include at least two first analysis modules for analyzing the at least two signals.

3. The system according to claim 2, characterized in that The first programmable logic device includes M first storage modules, wherein the M first storage modules are used to store data information corresponding to the signals of the M paths, and the M first storage modules include at least two first storage modules for storing data information corresponding to the at least two signals.

4. The system according to claim 3, characterized in that The first programmable logic device includes a packaging module, wherein the packaging module is used to capture data information corresponding to the signals of the M paths from the M first storage modules in sequence according to the storage number information of the M first storage modules, and combine the data information corresponding to the signals of the M paths according to the target format to obtain the combined first packaging data.

5. The system according to claim 4, characterized in that The encapsulation module includes a first encapsulation submodule, wherein the first encapsulation submodule is used to capture first data information corresponding to at least two I2C signals from the M first storage modules, and perform data combination on the first data information according to a first target format to obtain combined first encapsulation sub-data, wherein the first data information includes first storage number information of the at least two I2C signals in the first storage module, storage address information in the control device, and I2C data information, and the first target format is used to indicate that the first storage number information, the storage address information, and the I2C data information of each I2C signal are combined in sequence; The encapsulation module includes a second encapsulation sub-module, wherein the second encapsulation sub-module is used to capture second data information corresponding to at least two UART signals from the M first storage modules, and combine the second data information according to a second target format to obtain a combined second encapsulation sub-data, wherein the second data information includes second storage number information and UART data information of the at least two UART signals in the first storage module, and the second target format is used to indicate that the second storage number information and the UART data information of each UART signal are combined in sequence.

6. The system according to claim 5, characterized in that The first programmable logic device includes a main control module, wherein the main control module is used to add protocol address information supported by the preset communication protocol before the first package sub-data to obtain third package sub-data; The first programmable logic device includes a mapping module, wherein the mapping module is used to map the second encapsulated data to the N paths supported by the preset communication protocol, wherein the second encapsulated data includes the second encapsulated sub-data and the third encapsulated sub-data, and the second encapsulated data corresponding to the at least two signals are mapped to the target path among the N paths.

7. The system according to claim 1, characterized in that The second programmable logic device includes N second analysis modules, wherein the N second analysis modules are used to analyze the signals sent by the N paths to obtain data information corresponding to the signals sent by the N paths, the data information corresponding to the signals sent by the N paths corresponds to the data information of the signals generated by the M paths, and the N second analysis modules include a second analysis module for analyzing the one signal.

8. The system according to claim 7, characterized in that The second editable logic device includes M second storage modules, wherein the M second storage modules are used to store data information of signals generated by the M paths, and the M second storage modules include at least two second storage modules for storing data information corresponding to the at least two signals.

9. The system according to claim 8, characterized in that The second editable logic device comprises an identification module, wherein the identification module is used to identify the storage number information included in the data information corresponding to the signals sent by the N paths; The second editable logic device includes a sending module, wherein the sending module is used to store the signals sent by the N paths into the corresponding second storage module according to the storage number information.

10. The system according to claim 9, characterized in that The second editable logic device includes a forwarding module, wherein the forwarding module is used to read data information from the M second storage modules in sequence according to the storage number information, and forward the read data information to the corresponding computing device for data processing.

11. A signal processing method, characterized in that: include: Acquire at least two signals to be transmitted, wherein the at least two signals come from different paths of a control device, the control device includes M paths, and M is a positive integer greater than 1; Determining, according to a path matching rule, a target path that matches at least two paths of the at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, where N is a positive integer less than M; The at least two signals are encapsulated to obtain an encapsulated signal, and the signal is mapped to the target path, wherein the target path is used to send the signal to a data board.

12. The method according to claim 11, characterized in that The encapsulating the at least two signals to obtain an encapsulated signal includes: Performing an analysis operation on the at least two signals to obtain data information of the at least two signals; storing data information of the at least two signals in a memory, and generating memory number information of the at least two signals; Based on the memory number information and the data information of each signal of the at least two signals, orderly combination is performed to obtain the signal.

13. The method according to claim 11, characterized in that Before determining, according to the path matching rule, a target path that matches at least two paths of the at least two signals from the N paths supported by the LTPI protocol, the method further includes: Establish the path matching rule, wherein the path matching rule indicates a mapping relationship between the N paths and the M paths, the first i paths among the N paths correspond to P+1 paths among the M paths, the last Ni paths correspond to P paths among the M paths, P is the quotient of N divided by M, and i is a positive integer less than or equal to N.

14. A signal processing method, characterized in that: include: Acquire a received signal, wherein the signal is a signal of a different path of the control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated; Parsing the one-way signal to obtain at least two parsed signals, and storing the at least two-way signals in a memory, wherein the at least two-way signals carry memory number information; According to the memory number information, the signals in the at least two channels of signals are read in sequence, and the read signals are forwarded to the computing device corresponding to the read signals in the data board.

15. The method according to claim 14, characterized in that The step of parsing the one signal to obtain at least two signals after parsing includes: Performing format analysis on the one-way signal to obtain a frame format of the one-way signal, wherein the frame format is composed of the memory number information and data information of each of the at least two-way signal; According to the frame format, the one signal is divided to obtain the at least two signals.

16. A signal processing device, characterized in that: include: An acquisition unit, configured to acquire at least two signals to be transmitted, wherein the at least two signals come from different paths of a control device, the control device includes M paths, and M is a positive integer greater than 1; a determining unit, configured to determine, according to a path matching rule, a target path that matches at least two paths of the at least two signals from N paths supported by a preset communication protocol, wherein the path matching rule stores N mapping relationships between each path in the N paths and at least two paths in the M paths, where N is a positive integer less than M; The mapping unit is used to encapsulate the at least two signals to obtain an encapsulated signal, and map the signal to the target path, wherein the target path is used to send the signal to the data board.

17. A signal processing device, characterized in that: include: An acquisition unit, used to acquire a received signal, wherein the signal is a signal of a different path of the control device, and is a signal forwarded by a path supported by a preset communication protocol after being encapsulated; A parsing unit, configured to parse the one signal to obtain at least two signals after parsing, and store the at least two signals in a memory, wherein the at least two signals carry memory number information; The forwarding unit is used to read the signals in the at least two channels of signals in sequence according to the memory number information, and forward the read signals to the computing device corresponding to the read signals in the data board card.

18. A computer program product, characterized in that The method comprises a computer program, which, when executed by a processor, implements the steps of the method according to any one of claims 11 to 13 or 14 to 15.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 11 to 13 or 14 to 15 when executed by a processor.

20. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 11 to 13 or 14 to 15 are implemented.

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