Verification method and device of chip encryption module, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a verification method and device of a chip encryption module, electronic equipment and a storage medium. The method comprises the steps of obtaining random input data; determining a first calculation result according to the random input data and the DUT to be detected, and determining a random detection result corresponding to the random input data according to the random input data and a preset detection model; according to the random detection result and the first calculation result, determining a first verification result corresponding to the DUT to be detected, generating random input data to ensure that the verification process has wide coverage under various inputs and multiple modes, and respectively inputting the random input data into the DUT to be detected and a preset detection model to ensure that the verification process has wide coverage under various input and multiple modes. The first calculation result and the random detection result are obtained and compared, then the verification result is obtained, and the reliability and comprehensiveness of function verification are improved by using a large amount of random excitation and randomly setting register configuration of the AES.

Description

Technical Field

[0001] The present application relates to the field of verification technology, and in particular to a verification method, device, electronic device and storage medium for a chip encryption module. Background Art

[0002] In recent years, with the continuous expansion of the scale of digital integrated circuit design, chip verification has played a very important role in the success of chip design. In the verification work, a good verification platform and method are very necessary. AES (Advanced Encryption Standard, used to verify the Advanced Encryption Standard) is a widely used symmetric encryption algorithm used to protect the confidentiality of sensitive data. In embedded systems and chip design, the correctness and performance of the AES module are crucial. In the prior art, the driver module generates a fixed excitation signal, which is input into the device under test (DUT), and the detection result corresponding to the excitation signal is calculated, and the detection result is compared with the standard data. Although this method can test some signals of the model under test, it cannot detect the module under test in the face of some burst signals. Therefore, how to improve the comprehensiveness of the detection of the module under test is a problem that needs to be solved urgently. Summary of the invention

[0003] Some embodiments of the present application aim to provide a verification method, device, electronic device and storage medium for a chip encryption module. Through the technical solutions of the embodiments of the present application, random input data is obtained; a first calculation result is determined according to the random input data and the DUT to be tested, wherein the DUT to be tested is encrypted and decrypted by an encryption algorithm and a decryption algorithm; a random detection result corresponding to the random input data is determined according to the random input data and a pre-set detection model; a first verification result corresponding to the DUT to be tested is determined according to the random detection result and the first calculation result. In the embodiments of the present application, random input data is generated to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then the random input data is respectively input to the DUT to be tested and the pre-set detection model to obtain a first calculation result and a random detection result, and the first calculation result and the random detection result are compared to obtain a first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0004] In a first aspect, some embodiments of the present application provide a chip encryption module verification method, including:

[0005] Get random input data;

[0006] Determine a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm;

[0007] Determine a random detection result corresponding to the random input data according to the random input data and a preset detection model;

[0008] A first verification result corresponding to the DUT to be tested is determined according to the random detection result and the first calculation result.

[0009] Some embodiments of the present application generate random input data to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then input the random input data to the DUT to be tested and the pre-set detection model respectively to obtain a first calculation result and a random detection result, and compare the first calculation result and the random detection result to obtain a first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0010] Optionally, the preset detection model and the DUT to be tested are implemented in at least one programming language, and the programming language includes at least C language or Verilog algorithm.

[0011] Some embodiments of the present application provide verification accuracy by setting a detection model, which is a model generated by C language for performing encryption and decryption functions, to verify the encryption and decryption functions of the DUT under test.

[0012] Optionally, determining a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result includes:

[0013] The first detection result and the random detection result are compared to obtain a first verification result, wherein the first verification result at least includes passing the verification or failing the verification.

[0014] Some embodiments of the present application compare the first calculation result with the random detection result to obtain the verification result corresponding to the DUT to be tested, and use a large number of random stimuli to randomly set the register configuration of AES to improve the reliability and comprehensiveness of functional verification.

[0015] Optionally, the method further comprises:

[0016] Input error injection data;

[0017] Inputting the error injection data into the DUT to be tested to obtain a second calculation result;

[0018] Inputting the error injection data into the preset detection model to obtain an error detection result corresponding to the error injection data;

[0019] A second verification result corresponding to the DUT to be tested is determined according to the second calculation result and the error detection result.

[0020] Some embodiments of the present application generate erroneous input data, for example, input data outside the design specification, to verify the stability and robustness of the AES module when facing abnormal situations.

[0021] Optionally, determining a random detection result corresponding to the random input data according to the random input data and a preset detection model includes:

[0022] The random input data is input into the preset detection model through a preset conversion interface to obtain a random detection result corresponding to the random input data.

[0023] In a second aspect, some embodiments of the present application provide a verification device for a chip encryption module, including:

[0024] An acquisition module, used to obtain random input data;

[0025] A first calculation module, used for determining a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm;

[0026] A second calculation module, used to determine a random detection result corresponding to the random input data according to the random input data and a preset detection model;

[0027] A comparison module is used to determine a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result.

[0028] Some embodiments of the present application generate random input data to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then input the random input data to the DUT to be tested and the pre-set detection model respectively to obtain a first calculation result and a random detection result, and compare the first calculation result and the random detection result to obtain a first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0029] Optionally, the preset detection model and the DUT to be tested are implemented in at least one programming language, and the programming language includes at least C language or Verilog algorithm.

[0030] Some embodiments of the present application provide verification accuracy by setting a detection model, which is a model generated by C language for performing encryption and decryption functions, to verify the encryption function of the DUT under test.

[0031] Optionally, the comparison module is used to:

[0032] The first detection result and the random detection result are compared to obtain a first verification result, wherein the first verification result at least includes passing the verification or failing the verification.

[0033] Some embodiments of the present application compare the first calculation result with the random detection result to obtain the verification result corresponding to the DUT to be tested, and use a large number of random stimuli to randomly set the register configuration of AES to improve the reliability and comprehensiveness of functional verification.

[0034] Optionally, the comparison module is used to:

[0035] Input error injection data;

[0036] Inputting the error injection data into the DUT to be tested to obtain a second calculation result;

[0037] Inputting the error injection data into the preset detection model to obtain an error detection result corresponding to the error injection data;

[0038] A second verification result corresponding to the DUT to be tested is determined according to the second calculation result and the error detection result.

[0039] Some embodiments of the present application generate erroneous input data, for example, input data outside the design specification, to verify the stability and robustness of the AES module when facing abnormal situations.

[0040] Optionally, the second computing module is used to:

[0041] The random input data is input into the preset detection model through a preset conversion interface to obtain a random detection result corresponding to the random input data.

[0042] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, a chip encryption module verification method as described in any embodiment of the first aspect can be implemented.

[0043] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the chip encryption module verification method as described in any embodiment of the first aspect.

[0044] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, can implement the chip encryption module verification method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A schematic diagram of a flow chart of a chip encryption module verification method provided in an embodiment of the present application;

[0047] Figure 2 A schematic diagram of a flow chart of another chip encryption module verification method provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of the structure of a verification device for a chip encryption module provided in an embodiment of the present application;

[0049] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0051] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0052] In recent years, with the continuous expansion of the scale of digital integrated circuit design, chip verification has played a very important role in the success of chip design. In the verification work, a good verification platform and method are very necessary. AES is a widely used symmetric encryption algorithm used to protect the confidentiality of sensitive data. In embedded system and chip design, the correctness and performance of the AES module are crucial. In the prior art, the driver (Driver) module generates a fixed excitation signal, which is input into the module to be tested (DUT), and the detection result corresponding to the excitation signal is calculated, and the detection result is compared with the standard data. Although this method can test some signals of the model to be tested, it cannot detect the module to be tested in the face of some burst signals. Therefore, how to improve the comprehensiveness of the detection of the module to be tested is a problem that needs to be solved urgently. In view of this, some embodiments of the present application provide a verification method for a chip encryption module, which includes obtaining random input data; determining a first calculation result based on the random input data and the DUT to be tested, wherein the DUT to be tested is performed using an encryption algorithm and a decryption algorithm. The random input data is encrypted and decrypted; a random detection result corresponding to the random input data is determined according to the random input data and a pre-set detection model; a first verification result corresponding to the DUT to be tested is determined according to the random detection result and the first calculation result. In the embodiment of the present application, random input data is generated to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then the random input data is respectively input to the DUT to be tested and the pre-set detection model to obtain a first calculation result and a random detection result, and the first calculation result and the random detection result are compared to obtain the first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0053] like Figure 1 As shown, an embodiment of the present application provides a chip encryption module verification method, the method comprising:

[0054] S101, obtaining random input data;

[0055] Specifically, the terminal device randomly generates a random test vector, ie, random input data, within a constraint range according to design requirements to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, wherein the design requirements may be design specifications.

[0056] S102, determining a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm;

[0057] Specifically, the DUT to be tested is an encryption module on the chip to be tested, and the terminal device inputs random input data into the DUT to be tested to obtain a first calculation result corresponding to the random input data.

[0058] S103, determining a random detection result corresponding to the random input data according to the random input data and a preset detection model;

[0059] Specifically, a detection model is also provided on the terminal device, and the detection model is used to implement the functions of the advanced encryption standard module. The pre-set detection model and the DUT to be tested are implemented using C language and Verilog algorithm respectively.

[0060] The terminal device inputs the random input data into a pre-set detection model to obtain a random detection result corresponding to the random input data.

[0061] S104: Determine a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result.

[0062] Specifically, the terminal device compares the random detection result and the first calculation result. If the two are the same, it means that the encryption and decryption functions of the DUT under test have passed the verification. If the two are different, it means that the DUT under test has failed the verification.

[0063] The embodiment of the present application provides a method for verifying an Advanced Encryption Standard (AES) module, which aims to build a verification platform to verify the correctness of the ciphertext / plaintext obtained from the input plaintext / ciphertext in various encryption / decryption modes, analyze the performance of multiple algorithm cores under full load in the case of large data volume, and provide data support for the design.

[0064] Some embodiments of the present application generate random input data to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then input the random input data to the DUT to be tested and the pre-set detection model respectively to obtain a first calculation result and a random detection result, and compare the first calculation result and the random detection result to obtain a first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0065] Another embodiment of the present application further supplements the verification method of the chip encryption module provided in the above embodiment.

[0066] Optionally, the preset detection model and the DUT to be tested are implemented in at least one programming language, and the programming language includes at least C language or Verilog algorithm.

[0067] Among them, the pre-set detection model and the DUT to be tested are implemented using C language and Verilog algorithm respectively, and the programming language of the encryption model written in the detection model is not specifically limited in the embodiment of the present application.

[0068] Exemplarily, Model 1, i.e., the DUT to be tested, is an encrypted model obtained by programming an algorithm in Verilog, and Model 2, i.e., the pre-set detection model, is an encrypted model obtained by programming an algorithm in C language.

[0069] Some embodiments of the present application provide verification accuracy by setting a detection model, which is an encryption model written in C language and is used to verify the encryption and decryption functions of the DUT under test.

[0070] Optionally, determining a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result includes:

[0071] If the first detection result and the random detection result are the same, a judgment result is determined, and the judgment result at least includes passing the verification or failing the verification.

[0072] If the first test result and the random test result are the same, determining a judgment result, the judgment result at least including passing the verification;

[0073] If the first test result and the random test result are different, determining a judgment result, the judgment result at least including failure to pass the verification;

[0074] For example, the embodiments of the present application can also be used for some less frequently used algorithm modes in the AES algorithm, which have been verified and covered with reference to the documents of the standard algorithm. Even if the AES function is modified, it can continue to be used by simply adjusting the test case settings, which greatly improves the reusability of the verification environment. In addition, the embodiments of the present application use a large number of random stimuli to randomly set the register configuration of AES to improve the reliability of function verification.

[0075] Some embodiments of the present application compare the first calculation result with the test result, and whether the output of the DUT is correct can be clearly observed through the printed information.

[0076] Optionally, the method further comprises:

[0077] Input error injection data;

[0078] Inputting the error injection data into the DUT to be tested to obtain a second calculation result;

[0079] Inputting the error injection data into the pre-set detection model respectively to obtain the error detection results corresponding to the error injection data;

[0080] A second verification result corresponding to the DUT to be tested is determined according to the second calculation result and the error detection result.

[0081] The embodiments of the present application may also perform an error injection test, that is, generate erroneous input data, such as input data outside the design specification, to verify the stability and robustness of the AES module when facing abnormal situations.

[0082] During the entire algorithm operation process, the error injection function will continuously give the module under test (DUT) incorrect configuration. When the algorithm encounters incorrect configuration and input, the module may be reset and the special error flag will be assigned a value of 1. It will also output incorrect encrypted or decrypted data. By printing information, you can see the error injection at different times and whether the module under test can respond normally.

[0083] Some embodiments of the present application generate erroneous input data, for example, input data outside the design specification, to verify the stability and robustness of the AES module when facing abnormal situations.

[0084] Optionally, determining a random detection result corresponding to the random input data according to the random input data and a preset detection model includes:

[0085] The random input data is input into the preset detection model through a preset conversion interface to obtain a random detection result corresponding to the random input data.

[0086] like Figure 2 As shown, the driver module is used to generate random input data and random error input, and bridge a comparator module used to save the module under test (DUT). The outputs of model 1 (first detection module) and model 2 (second detection module) are compared for data correctness through comparison functions. The AES algorithm is used as the module under test (DUT), using the AHB bus. Model 1 is an algorithm written in Verilog, and model 2 is an algorithm written in C language. Both models implement the functions of the advanced encryption standard module as a reference model to participate in the calculation.

[0087] A random test vector is automatically generated through a random vector function and given to the module under test (DUT) for randomized AES algorithm mode verification. The random test vector is input into model 1. After the random test vector is converted through the direct programming interface (DPI), the random test vector is input into model 2. The module under test (DUT) and models 1 and 2 simultaneously verify the algorithm.

[0088] When one or more algorithm data are input into the module under test (DUT), model 1 and model 2, they will generate their own outputs. The driver module will receive the outputs of the module under test (DUT) and model 1 and model 2, and send them to the comparator for comparison. The printed information can clearly show whether the output of the DUT is correct.

[0089] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0090] like Figure 2 As shown, during verification, the random test vector generation function and error injection function in the driver module are called, and given to model 1 and the module under test (DUT) through the AHB interface. The verification language used is system verilog, and the input to model 2 needs to be converted into C language through the direct programming interface (DPI) and given to model 2.

[0091] When all three stimuli are given, the outputs of the module under test (DUT), model 1 and model 2 will be saved in the comparator, and the data correctness comparison will be performed through the comparison function. When errors are injected into the module under test (DUT), model 1 and model 2, the error information will also be saved in the comparator. Through the simulation information printing, it can be observed whether the module's response to abnormal conditions is in line with expectations.

[0092] When different data volume encryption and decryption processes are input into the DUT, the performance analysis will record the calculation time and data volume of the current data, calculate the throughput of the algorithm through the function and record it in the performance analysis table for reference by designers.

[0093] Another embodiment of the present application provides a chip encryption module verification device, which is used to execute the chip encryption module verification method provided in the above embodiment.

[0094] like Figure 3 , which is a schematic diagram of the structure of the verification device of the chip encryption module provided in the embodiment of the present application. The verification device of the chip encryption module includes an acquisition module 301, a first calculation module 302, a second calculation module 303 and a comparison module 304, wherein:

[0095] The acquisition module 301 is used to acquire random input data;

[0096] The first calculation module 302 is used to determine a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm;

[0097] The second calculation module 303 is used to determine the random detection result corresponding to the random input data according to the random input data and the preset detection model;

[0098] The comparison module 304 is used to determine a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result.

[0099] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0100] Some embodiments of the present application generate random input data to ensure that the verification process has extensive coverage for multiple inputs and multiple modes, and then input the random input data to the DUT to be tested and the pre-set detection model respectively to obtain a first calculation result and a random detection result, and compare the first calculation result and the random detection result to obtain a first verification result corresponding to the DUT to be tested. By using a large number of random stimuli and randomly setting the register configuration of AES, the reliability and comprehensiveness of functional verification are improved.

[0101] Another embodiment of the present application further supplements the verification device of the chip encryption module provided in the above embodiment.

[0102] Optionally, the preset detection model and the DUT to be tested are implemented in at least one programming language, and the programming language includes at least C language or Verilog algorithm.

[0103] Some embodiments of the present application provide verification accuracy by setting a detection model, which is an encryption model written in C language and is used to verify the encryption and decryption functions of the DUT under test.

[0104] Optionally, the comparison module is used to:

[0105] The first detection result and the random detection result are compared to obtain a first verification result, wherein the first verification result at least includes passing the verification or failing the verification.

[0106] Some embodiments of the present application compare the first calculation result with the random detection result to obtain the verification result corresponding to the DUT to be tested, and use a large number of random stimuli to randomly set the register configuration of AES to improve the reliability and comprehensiveness of functional verification.

[0107] Optionally, the comparison module is used to:

[0108] Input error injection data;

[0109] Inputting the error injection data into the DUT to be tested to obtain a second calculation result;

[0110] Inputting the error injection data into the preset detection model respectively to obtain error detection results corresponding to the error injection data;

[0111] A second verification result corresponding to the DUT to be tested is determined according to the second calculation result and the error detection result.

[0112] Some embodiments of the present application generate erroneous input data, for example, input data outside the design specification, to verify the stability and robustness of the AES module when facing abnormal situations.

[0113] Optionally, the second computing module is used to:

[0114] The random input data is input into the preset detection model through a preset conversion interface to obtain a random detection result corresponding to the random input data.

[0115] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0116] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0117] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the chip encryption module verification method provided in the above embodiments can be implemented.

[0118] An embodiment of the present application also provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to any embodiment of the chip encryption module verification method provided in the above embodiments.

[0119] like Figure 4 As shown, some embodiments of the present application provide an electronic device 400, which includes: a memory 410, a processor 420, and a computer program stored in the memory 410 and executable on the processor 420, wherein the processor 420 can implement any embodiment of the verification method of the chip encryption module as described above when reading the program from the memory 410 through a bus 430 and executing the program.

[0120] Processor 420 can process digital signals and can include various computing structures, such as complex instruction set computer structure, reduced instruction set computer structure, or a structure that implements a combination of multiple instruction sets. In some examples, processor 420 can be a microprocessor.

[0121] The memory 410 may be used to store instructions executed by the processor 420 or data related to the execution of instructions. These instructions and / or data may include codes for implementing some or all functions of one or more modules described in the embodiments of the present application. The processor 420 of the disclosed embodiment may be used to execute instructions in the memory 410 to implement the method shown above. The memory 410 includes a dynamic random access memory, a static random access memory, a flash memory, an optical memory, or other memory known to those skilled in the art.

[0122] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0123] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0124] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A chip encryption module verification method, characterized in that: The method comprises: Get random input data; Determine a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm; Determine a random detection result corresponding to the random input data according to the random input data and a preset detection model; A first verification result corresponding to the DUT to be tested is determined according to the random detection result and the first calculation result.

2. The chip encryption module verification method according to claim 1, characterized in that: The preset detection model and the DUT to be tested are implemented using at least one programming language, and the programming language at least includes C language or Verilog algorithm.

3. The chip encryption module verification method according to claim 1, characterized in that: The step of determining a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result includes: The first detection result and the random detection result are compared to obtain a first verification result, wherein the first verification result at least includes passing the verification or failing the verification.

4. The chip encryption module verification method according to claim 1, characterized in that: The method further comprises: Input error injection data; Inputting the error injection data into the DUT to be tested to obtain a second calculation result; Inputting the error injection data into the preset detection model respectively to obtain error detection results corresponding to the error injection data; A second verification result corresponding to the DUT to be tested is determined according to the second calculation result and the error detection result.

5. The chip encryption module verification method according to claim 1, characterized in that: The step of determining a random detection result corresponding to the random input data according to the random input data and a preset detection model includes: The random input data is input into the preset detection model through a preset conversion interface to obtain a random detection result corresponding to the random input data.

6. A verification device for a chip encryption module, characterized in that: The device comprises: An acquisition module, used to obtain random input data; A first calculation module, used for determining a first calculation result according to the random input data and the DUT to be tested, wherein the DUT to be tested is obtained by encryption and decryption using an encryption algorithm and a decryption algorithm; A second calculation module, used to determine a random detection result corresponding to the random input data according to the random input data and a preset detection model; A comparison module is used to determine a first verification result corresponding to the DUT to be tested according to the random detection result and the first calculation result.

7. The chip encryption module verification device according to claim 6, characterized in that: The preset detection model and the DUT to be tested are implemented using at least one programming language, and the programming language at least includes C language or Verilog algorithm.

8. The chip encryption module verification method according to claim 6, characterized in that: The comparison module is used for: The first detection result and the random detection result are compared to obtain a first verification result, wherein the first verification result at least includes passing the verification or failing the verification.

9. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the chip encryption module verification method described in any one of claims 1 to 5 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the program, when executed by a processor, can implement the chip encryption module verification method described in any one of claims 1 to 5.

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