Circuit board fault diagnosis method and system based on artificial intelligence

Abstract

The present invention provides a circuit board fault diagnosis method and system based on artificial intelligence, which relates to the technical field of circuit board fault diagnosis, including constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, and generating an electromagnetic field distortion distribution map; dividing the fault sensitive area of ​​the circuit board based on the electromagnetic field distortion distribution map, outputting the performance degradation rate of each functional area of ​​the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate; reconstructing the function of the circuit board according to the fault risk assessment matrix, establishing a dynamic fault tolerance mechanism of the circuit board, generating a task load distribution strategy based on the dynamic fault tolerance mechanism, deploying the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repairing the circuit board by adjusting the logical structure of the field programmable gate array, verifying the repair effect and outputting a diagnosis report.

Description

Technical Field

[0001] This invention relates to circuit board fault diagnosis technology, and more particularly to a circuit board fault diagnosis method and system based on artificial intelligence. Background Technology

[0002] As electronic devices evolve towards higher-density integration and higher performance, circuit board fault diagnosis and maintenance face significant challenges. Traditional fault diagnosis methods primarily rely on human experience and fixed detection rules, making it difficult to handle complex fault scenarios. Existing technologies exhibit poor adaptability in rule-based methods, struggling to handle unknown fault types; statistical model-based methods suffer from high computational complexity and insufficient real-time performance; and expert system-based methods face difficulties in knowledge acquisition and high maintenance costs. While some research has begun to incorporate machine learning techniques for fault diagnosis, these methods suffer from strong sample dependence and poor generalization ability. Furthermore, existing diagnostic methods often separate fault detection from repair, lacking a systematic solution.

[0003] Therefore, there is an urgent need to establish an intelligent and adaptive circuit board fault diagnosis and repair mechanism to improve system reliability. Summary of the Invention

[0004] This invention provides a circuit board fault diagnosis method and system based on artificial intelligence, which can solve the problems in the prior art.

[0005] A first aspect of the present invention,

[0006] An artificial intelligence-based circuit board fault diagnosis method is provided, including:

[0007] A three-dimensional electromagnetic field simulation model of a circuit board is constructed. Multiple virtual sensing probes are set in the three-dimensional electromagnetic field simulation model. The virtual sensing probes correspond one-to-one with the positions of the physical sensors on the circuit board. The measured data of the physical sensors and the simulation data of the virtual sensing probes are collected. By comparing the deviation values ​​of the measured data and the simulation data, an abnormal behavior pattern library of the circuit board is established. A backpropagation neural network is constructed based on the abnormal behavior pattern library. The electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the backpropagation neural network, and an electromagnetic field distortion distribution map is generated.

[0008] The circuit board is divided into fault-sensitive areas based on the electromagnetic field distortion distribution map. An adaptive sampling array is deployed in the fault-sensitive areas. The adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed based on the multi-dimensional signals collected by the adaptive sampling array. The fault feature vector is input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board. A fault risk assessment matrix is ​​generated based on the performance degradation rate.

[0009] The circuit board is functionally reconstructed based on the fault risk assessment matrix, and the computing tasks in high-risk areas are migrated to low-risk areas. A dynamic fault tolerance mechanism for the circuit board is established, and a task load allocation strategy is generated based on the dynamic fault tolerance mechanism. The task load allocation strategy is deployed to the field-programmable gate array (FPGA) of the circuit board, and the circuit board is autonomously repaired by adjusting the logic structure of the FPGA. The operating data of the circuit board after repair is collected, and the operating data is compared with the fault feature vector before repair to verify the repair effect and output a diagnostic report.

[0010] In one alternative embodiment,

[0011] By comparing the deviations between measured and simulated data, an abnormal behavior pattern library for the circuit board is established. A backpropagation neural network is constructed based on this library. The electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated using this backpropagation neural network, generating an electromagnetic field distortion distribution map, including:

[0012] The time-domain statistical features are generated by an adaptive wavelet decomposition module, and the frequency-domain spectral features are generated by a fast Fourier transform module. An attention mechanism is used to dynamically assign weights to the time-domain statistical features and the frequency-domain spectral features to form a fused feature vector.

[0013] The feature covariance matrix is ​​updated using the recursive least squares algorithm. Based on the updated feature covariance matrix, the Mahalanobis distance between the measured feature vectors and the simulated feature vectors is calculated to obtain the anomaly sequence.

[0014] An anomaly sequence is subjected to a dual-criteria density clustering method based on local density and distance distribution to determine cluster centers and adaptively adjust clustering parameters using fractal dimension to form anomaly pattern sequence;

[0015] The intrinsic mode functions (EMFs) of the abnormal pattern sequences are obtained through empirical mode decomposition. The evolutionary features of the EMFs are extracted using a sliding time window. The temporal association rules of the evolutionary features are mined based on the improved Apriori algorithm, and an abnormal behavior pattern library is established.

[0016] A deep hybrid neural network is trained based on an abnormal behavior pattern library. Spatial domain features are extracted through convolutional layers with residual connections, temporal domain features are extracted using long short-term memory units and gated recurrent units, and topological domain features are extracted using graph convolutional layers. The extracted features are combined and input into a fully connected layer to output the predicted value of electromagnetic field distortion.

[0017] Spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variation function. The Kriging interpolation parameters are adjusted using a Bayesian optimization algorithm. Spatial interpolation is performed on the predicted electromagnetic field distortion values. A multi-resolution distortion distribution representation is constructed through wavelet transform, and an electromagnetic field distortion distribution map is generated.

[0018] In one alternative embodiment,

[0019] Spatial anisotropy constraints on circuit board wiring density and impedance distribution are introduced into the variation function. A Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters, and spatial interpolation is performed on the predicted electromagnetic field distortion values. A multi-resolution distortion distribution representation is constructed using wavelet transform, generating an electromagnetic field distortion distribution map, including:

[0020] A density weight matrix is ​​constructed based on the circuit board wiring density distribution, and an impedance weight matrix is ​​constructed based on the circuit board impedance distribution. The density weight matrix and the impedance weight matrix are then combined using a rotation matrix to form an anisotropic matrix.

[0021] An exponential variation function is constructed using the anisotropy matrix. The variation function includes the nugget effect value, the sill value, and the spatial vector product term of the anisotropy matrix.

[0022] An optimization objective function is established, which includes interpolation prediction error, spatial smoothing constraint, and anisotropic characteristic. Gaussian process regression is used to establish the mapping relationship between parameters and objective function. The nugget effect value, sill value, and Kriging interpolation search radius of the variogram are iteratively optimized by maximizing the expected improvement criterion.

[0023] The Kriging weight coefficients are calculated based on the optimized variogram, and the electromagnetic field distortion estimate of the interpolation point is obtained by solving the Kriging equations.

[0024] The electromagnetic field distortion estimate is decomposed into multiple scales using orthogonal wavelet basis functions to obtain the coarsest-scale approximation coefficients and detail coefficients at different scales. The approximation coefficients and detail coefficients are then reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and overlays contour lines to show the distortion gradient changes.

[0025] In one alternative embodiment,

[0026] A fault feature vector is constructed based on the multidimensional signals acquired by the adaptive sampling array. This fault feature vector is then input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board. A fault risk assessment matrix is ​​generated based on the performance degradation rate, including:

[0027] A state space is constructed based on the multidimensional signals collected by the adaptive sampling array. The state space includes the state of functional units, operating parameters, and historical diagnostic results. An action space is constructed based on the action space, which includes operating condition identification and risk assessment actions.

[0028] A functional association graph is constructed based on the state space. The vertex set in the functional association graph represents the functional units of the circuit board, and the edge set represents the signal coupling relationship between the functional units. Based on the functional association graph, the mutual influence between the functional units is modeled through a graph attention mechanism to obtain fault characteristics.

[0029] A top-level strategy network with an execution entity and a judge entity structure is used for work condition identification. The execution entity network processes the work condition state vector through a residual connection layer and a batch normalization layer to obtain the work condition category probability distribution. The judge entity network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function based on the work condition identification accuracy and risk assessment effect.

[0030] A variational autoencoder model is constructed, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence composed of the fault features and the probability distribution of the working condition category into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory.

[0031] A causal temporal convolutional network is introduced into the posterior distribution space of the latent variables. The causal temporal convolutional network obtains the performance degradation evolution law through dilated convolution and performs multiple forward propagations using a random deactivation method to obtain the performance degradation prediction result.

[0032] A graph converter model is constructed, and the circuit board is modeled as a heterogeneous graph network. The node features of the heterogeneous graph network include the failure probability, performance index and topology features of the functional unit. The performance degradation prediction results are input into the graph converter model, and the risk propagation mode is learned through a multi-head attention mechanism.

[0033] A causal graph is constructed based on the risk propagation model. The causal graph is then structured using variational reasoning. The fault propagation strength between the functional units is evaluated through intervention calculus, and a fault risk assessment matrix is ​​generated.

[0034] In one alternative embodiment,

[0035] A causal graph is constructed based on the aforementioned risk propagation model. A variational inference method is used to perform structural learning on the causal graph. Interventional calculus is used to assess the fault propagation strength between the functional units, generating a fault risk assessment matrix, including:

[0036] A neural causal graph is constructed, which includes multiple functional unit nodes and directed edges between nodes. Temporal features of each functional unit node are extracted. The generator of a variational adversarial neural network is used to map the temporal features into conditional latent variables. The discriminator of the variational adversarial neural network evaluates the difference between the conditional latent variables and the true distribution to obtain a temporal feature representation.

[0037] Based on the temporal feature representation, a graph morphology adaptive layer is constructed. The graph morphology adaptive layer generates dynamic convolution kernels according to the local structural features of functional unit nodes, and adaptively adjusts the topology of the neural causal graph to obtain an optimized neural causal graph.

[0038] The optimized neural causal graph is input into the causal graph neural network. The causal embedding layer of the causal graph neural network maps functional unit nodes to the causal representation space, and the causal inference layer extracts causal dependencies through gated graph convolution.

[0039] The causal dependencies are input into a stochastic causal field model, which uses an energy function to jointly model the state of functional unit nodes, calculates the causal strength between nodes, and uses a dual attention mechanism to process the causal strength to obtain attention-enhanced causal features.

[0040] A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, maintains local risk features using residual connections, outputs propagation features, and combines the propagation features with the causal strength in a weighted manner to generate a fault risk assessment matrix. The elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

[0041] In one alternative embodiment,

[0042] Based on the fault risk assessment matrix, the circuit board is functionally reconfigured, and computational tasks in high-risk areas are migrated to low-risk areas. A dynamic fault tolerance mechanism for the circuit board is established, and a task load allocation strategy is generated based on the dynamic fault tolerance mechanism, including:

[0043] The incoming risk value and outgoing risk value of each functional unit are calculated based on the fault risk assessment matrix. The incoming risk value represents the degree of risk impact of other functional units on the target functional unit, and the outgoing risk value represents the degree of risk propagation of the target functional unit to other functional units.

[0044] The weighted fusion of the incoming risk value and the outgoing risk value yields the comprehensive risk level of each functional unit. Based on the comprehensive risk level, a migration optimization model is established for the computational tasks on the circuit board.

[0045] A set of candidate migration schemes is generated based on the migration optimization model. The overall system risk value is calculated for each candidate scheme in the set of candidate migration schemes. The candidate scheme with the minimum overall system risk value is selected as the optimal task allocation scheme.

[0046] According to the optimal task allocation scheme, a three-module redundancy structure is constructed in each functional unit. The three-module redundancy structure achieves reliable data output through parallel data processing and majority voting selection mechanism.

[0047] Collect real-time load data of each functional unit, calculate the load distribution status based on the processing capacity of the functional unit, and calculate the deployment score for the task to be deployed based on the load distribution status.

[0048] The task priority is calculated by combining the task importance index with the comprehensive risk level, and a task queue based on priority is generated. The task priority in the task queue is dynamically adjusted according to the load distribution status.

[0049] An initial task allocation scheme is generated based on the task queue and the deployment score. The initial allocation scheme is then iteratively optimized by combining the risk assessment matrix and the processing capacity of each functional unit, and a final task load allocation strategy is output, which includes task deployment location, execution sequence and load adjustment parameters.

[0050] In one alternative embodiment,

[0051] The task load distribution strategy is deployed to the field-programmable gate array (FPGA) of the circuit board. The circuit board is then autonomously repaired by adjusting the logic structure of the FPGA. Operational data of the repaired circuit board is collected, and this data is compared with the fault feature vector before repair to verify the repair effect and output a diagnostic report, including:

[0052] A state machine execution model is established based on the received task load allocation strategy, and a state transition rule base containing state transition conditions and trigger thresholds is generated. The state machine execution model includes idle state, loading start state, loading state, verification state, and switching state.

[0053] Read the state transition conditions in the state transition rule base, calculate the mapping relationship between the storage address of the configuration bitstream and the reconfigurable area of ​​the FPGA, and generate the configuration bitstream loading control signal according to the mapping relationship;

[0054] A double-buffer structure is constructed based on the loading control signal, and a buffer mutex lock and a buffer status flag are set. The buffer status flag indicates the current read / write status of the buffer.

[0055] The status flag of the buffer is detected. When data is written to one buffer, the data output strobe signal of the other buffer is set according to the mutex lock.

[0056] The configuration bitstream is written into the writable buffer of the double-buffered structure. After the writing is completed, the status flag of the buffer is updated, triggering the state machine execution model to switch states.

[0057] Collect functional unit operating status data, timing parameter data, and resource usage data in the FPGA, generate operating status feature vectors, perform correlation analysis between the operating status feature vectors and preset fault feature vectors, calculate functional unit status recovery rate, timing parameter recovery rate, and resource utilization optimization rate, and generate repair effect evaluation indicators.

[0058] A multi-level scoring model is established based on the repair effect evaluation indicators. Each evaluation indicator is weighted according to the weight set by the task priority identifier to generate a comprehensive repair score and output a diagnostic report containing fault location information and repair status information.

[0059] A second aspect of the present invention,

[0060] An artificial intelligence-based circuit board fault diagnosis system is provided, comprising:

[0061] The first unit is used to construct a three-dimensional electromagnetic field simulation model of the circuit board. Multiple virtual sensing probes are set in the three-dimensional electromagnetic field simulation model. The virtual sensing probes correspond one-to-one with the positions of the physical sensors on the circuit board. The measured data of the physical sensors and the simulation data of the virtual sensing probes are collected. By comparing the deviation values ​​of the measured data and the simulation data, an abnormal behavior pattern library of the circuit board is established. A backpropagation neural network is constructed based on the abnormal behavior pattern library. The electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the backpropagation neural network, and an electromagnetic field distortion distribution map is generated.

[0062] The second unit is used to divide the fault-sensitive areas of the circuit board based on the electromagnetic field distortion distribution map, and deploy an adaptive sampling array in the fault-sensitive areas. The adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed based on the multi-dimensional signals collected by the adaptive sampling array. The fault feature vector is input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board, and a fault risk assessment matrix is ​​generated based on the performance degradation rate.

[0063] The third unit is used to reconstruct the circuit board's functions based on the fault risk assessment matrix, migrate computing tasks from high-risk areas to low-risk areas, establish a dynamic fault tolerance mechanism for the circuit board, generate a task load allocation strategy based on the dynamic fault tolerance mechanism, deploy the task load allocation strategy to the field-programmable gate array (FPGA) of the circuit board, perform autonomous repair on the circuit board by adjusting the logic structure of the FPGA, collect the operating data of the circuit board after repair, compare the operating data with the fault feature vector before repair, verify the repair effect, and output a diagnostic report.

[0064] A third aspect of the present invention,

[0065] An electronic device is provided, comprising:

[0066] processor;

[0067] Memory used to store processor-executable instructions;

[0068] The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0069] Fourth aspect of the embodiments of the present invention,

[0070] A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0071] In this embodiment, by establishing a three-dimensional electromagnetic field simulation model and combining it with actual sensing data, abnormal behavior patterns of the circuit board can be accurately identified; the electromagnetic field distortion distribution is analyzed using a backpropagation neural network to achieve precise location of fault-sensitive areas; an adaptive sampling array and reinforcement learning model are used to quantitatively assess fault risks, improving the accuracy of fault diagnosis; autonomous repair of the circuit board is achieved through dynamic task load allocation and FPGA reconstruction, reducing maintenance costs; and a complete closed-loop mechanism of fault diagnosis-risk assessment-autonomous repair is established, improving the reliability and service life of the circuit board system. Attached Figure Description

[0072] Figure 1 This is a flowchart illustrating the circuit board fault diagnosis method based on artificial intelligence according to an embodiment of the present invention.

[0073] Figure 2 This is a schematic diagram of the structure of an artificial intelligence-based circuit board fault diagnosis system according to an embodiment of the present invention. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0076] Figure 1 This is a flowchart illustrating the artificial intelligence-based circuit board fault diagnosis method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0077] S101. Construct a three-dimensional electromagnetic field simulation model of the circuit board. Set multiple virtual sensing probes in the three-dimensional electromagnetic field simulation model. The virtual sensing probes correspond one-to-one with the positions of the physical sensors on the circuit board. Collect the measured data of the physical sensors and the simulation data of the virtual sensing probes. By comparing the deviation values ​​of the measured data and the simulation data, establish an abnormal behavior pattern library of the circuit board. Construct a backpropagation neural network based on the abnormal behavior pattern library. Calculate the degree of electromagnetic field distortion in each functional area of ​​the circuit board based on the backpropagation neural network and generate an electromagnetic field distortion distribution map.

[0078] First, a three-dimensional electromagnetic field simulation model of the circuit board is constructed. Using computer-aided design software, an accurate three-dimensional geometric model is established based on the actual structure and material parameters of the circuit board. Then, using the finite element method, the entire model is divided into numerous micro-elements, and boundary conditions and excitation sources are set. Virtual sensing probes are placed at several key locations within the model; these probes correspond one-to-one with the sensor positions on the actual circuit board.

[0079] Next, the model was solved using electromagnetic field simulation software to obtain electromagnetic field parameters such as electric and magnetic field strengths at each virtual probe location. Simultaneously, the actual circuit board was tested, and measurement data from the physical sensors at the corresponding locations were collected. The simulation data was compared with the measured data, and the deviation was calculated. Based on the distribution characteristics of the deviation values, a library of abnormal behavior patterns for the circuit board was established, including various fault modes such as short circuits, open circuits, and component failures.

[0080] A backpropagation neural network was constructed based on an abnormal behavior pattern library. This network consists of an input layer, hidden layers, and an output layer. The input is the electromagnetic field parameter deviation values ​​at each probe location, and the output is the degree of electromagnetic field distortion in each functional area of ​​the circuit board. The network was trained and optimized using a large number of training samples to achieve good generalization ability. Using the trained neural network and new test data, the degree of electromagnetic field distortion in each area of ​​the circuit board can be quickly calculated, and an intuitive electromagnetic field distortion distribution map can be generated.

[0081] In one alternative embodiment,

[0082] By comparing the deviations between measured and simulated data, an abnormal behavior pattern library for the circuit board is established. A backpropagation neural network is constructed based on this library. The electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated using this backpropagation neural network, generating an electromagnetic field distortion distribution map, including:

[0083] The time-domain statistical features are generated by an adaptive wavelet decomposition module, and the frequency-domain spectral features are generated by a fast Fourier transform module. An attention mechanism is used to dynamically assign weights to the time-domain statistical features and the frequency-domain spectral features to form a fused feature vector.

[0084] The feature covariance matrix is ​​updated using the recursive least squares algorithm. Based on the updated feature covariance matrix, the Mahalanobis distance between the measured feature vectors and the simulated feature vectors is calculated to obtain the anomaly sequence.

[0085] An anomaly sequence is subjected to a dual-criteria density clustering method based on local density and distance distribution to determine cluster centers and adaptively adjust clustering parameters using fractal dimension to form anomaly pattern sequence;

[0086] The intrinsic mode functions (EMFs) of the abnormal pattern sequences are obtained through empirical mode decomposition. The evolutionary features of the EMFs are extracted using a sliding time window. The temporal association rules of the evolutionary features are mined based on the improved Apriori algorithm, and an abnormal behavior pattern library is established.

[0087] A deep hybrid neural network is trained based on an abnormal behavior pattern library. Spatial domain features are extracted through convolutional layers with residual connections, temporal domain features are extracted using long short-term memory units and gated recurrent units, and topological domain features are extracted using graph convolutional layers. The extracted features are combined and input into a fully connected layer to output the predicted value of electromagnetic field distortion.

[0088] Spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variation function. The Kriging interpolation parameters are adjusted using a Bayesian optimization algorithm. Spatial interpolation is performed on the predicted electromagnetic field distortion values. A multi-resolution distortion distribution representation is constructed through wavelet transform, and an electromagnetic field distortion distribution map is generated.

[0089] For example, firstly, an adaptive wavelet decomposition module is used to perform time-domain analysis on the measured and simulated data of the circuit board, extracting statistical features such as mean, variance, skewness, and kurtosis. Simultaneously, a fast Fourier transform module is used to perform frequency-domain analysis on the data, obtaining spectral features such as dominant frequency, bandwidth, and spectral energy. Then, an attention mechanism is used to dynamically assign weights to the time-domain statistical features and the frequency-domain spectral features, forming a fused feature vector that comprehensively characterizes the electromagnetic properties of the circuit board.

[0090] Next, a recursive least squares algorithm is used to update the feature covariance matrix in real time to adapt to the dynamic changes in the circuit board's operating state. Based on the updated feature covariance matrix, the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated to obtain an anomaly degree sequence reflecting the degree of anomaly of the circuit board. For example, the anomaly degree sequence of a circuit board under normal operating conditions is [0.2, 0.3, 0.1, 0.4, 0.2], and when an anomaly occurs, the sequence becomes [1.5, 2.1, 1.8, 2.5, 2.3].

[0091] Then, a dual-criteria density clustering method based on local density and distance distribution is used to perform cluster analysis on the anomaly sequence. This method first calculates the local density and distance distribution of each data point, and then determines the cluster centers by comprehensively considering these two indicators. During the clustering process, fractal dimension is used to adaptively adjust clustering parameters such as the truncation distance to adapt to anomaly patterns at different scales. Through cluster analysis, similar anomaly patterns are grouped into one class, forming an anomaly pattern sequence.

[0092] Empirical Mode Decomposition (EMD) is performed on the obtained anomalous pattern sequences to obtain a series of intrinsic mode functions (EMFs). The evolutionary features of the EMFs, such as amplitude change rate and frequency drift, are extracted using a sliding time window method. Temporal correlation rules of these evolutionary features are mined based on an improved Apriori algorithm to establish an anomalous behavior pattern library. For example, a strong correlation may be found between "amplitude mutation" and "frequency drift," indicating that these two phenomena often occur simultaneously.

[0093] Based on an established database of abnormal behavior patterns, a deep hybrid neural network is trained to predict electromagnetic field distortion. This network comprises several functional modules: spatial domain features are extracted through convolutional layers with residual connections to capture local features of the electromagnetic field distribution; temporal domain features are extracted using long short-term memory units and gated recurrent units to learn the variation of the electromagnetic field over time; and topological domain features are extracted using graph convolutional layers to consider the connectivity between different regions of the circuit board. The extracted features are combined and input into a fully connected layer, ultimately outputting a predicted value for electromagnetic field distortion.

[0094] Finally, spatial anisotropy constraints on circuit board wiring density and impedance distribution are introduced into the variation function to reflect the variation characteristics of electromagnetic field distortion in different directions. A Bayesian optimization algorithm is used to adaptively adjust the parameters of the Kriging interpolation, such as the range and sill value, to spatially interpolate the discrete electromagnetic field distortion predictions, obtaining a continuous distribution. Then, a multi-resolution distortion distribution representation is constructed through wavelet transform, preserving both the global trend and highlighting local details, ultimately generating an intuitive electromagnetic field distortion distribution map.

[0095] In this embodiment, an abnormal behavior pattern library is constructed to effectively identify and classify electromagnetic field distortions on circuit boards. The combination of adaptive wavelet decomposition and fast Fourier transform provides comprehensive features in both the time and frequency domains, resulting in more comprehensive feature extraction. Utilizing recursive least squares and Mahalanobis distance, the feature covariance matrix can be updated in real time, improving the accuracy of anomaly assessment. Dual-criterion density clustering and fractal dimension adjustment further refine the identification of abnormal patterns. Simultaneously, the application of deep hybrid neural networks, combined with multiple feature extraction methods, enhances the model's adaptability to complex data. The introduction of spatial anisotropy constraints and Bayesian optimization optimizes the accuracy of electromagnetic field distortion prediction. The resulting electromagnetic field distortion distribution map provides a visual and quantitative basis for circuit board design and fault diagnosis, helping to improve product reliability and performance.

[0096] In one alternative embodiment,

[0097] Spatial anisotropy constraints on circuit board wiring density and impedance distribution are introduced into the variation function. A Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters, and spatial interpolation is performed on the predicted electromagnetic field distortion values. A multi-resolution distortion distribution representation is constructed using wavelet transform, generating an electromagnetic field distortion distribution map, including:

[0098] A density weight matrix is ​​constructed based on the circuit board wiring density distribution, and an impedance weight matrix is ​​constructed based on the circuit board impedance distribution. The density weight matrix and the impedance weight matrix are then combined using a rotation matrix to form an anisotropic matrix.

[0099] An exponential variation function is constructed using the anisotropy matrix. The variation function includes the nugget effect value, the sill value, and the spatial vector product term of the anisotropy matrix.

[0100] An optimization objective function is established, which includes interpolation prediction error, spatial smoothing constraint, and anisotropic characteristic. Gaussian process regression is used to establish the mapping relationship between parameters and objective function. The nugget effect value, sill value, and Kriging interpolation search radius of the variogram are iteratively optimized by maximizing the expected improvement criterion.

[0101] The Kriging weight coefficients are calculated based on the optimized variogram, and the electromagnetic field distortion estimate of the interpolation point is obtained by solving the Kriging equations.

[0102] The electromagnetic field distortion estimate is decomposed into multiple scales using orthogonal wavelet basis functions to obtain the coarsest-scale approximation coefficients and detail coefficients at different scales. The approximation coefficients and detail coefficients are then reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and overlays contour lines to show the distortion gradient changes.

[0103] First, a density weight matrix is ​​constructed based on the wiring density distribution of the circuit board. Specifically, the circuit board can be divided into several grid cells, the wiring density within each grid cell is statistically analyzed, and then normalized to the range of 0-1 to form a two-dimensional matrix. Similarly, an impedance weight matrix is ​​constructed based on the impedance distribution of the circuit board, and the impedance value of each grid cell is normalized to form another two-dimensional matrix.

[0104] Next, the density weight matrix and impedance weight matrix are combined using a rotation matrix to form the anisotropy matrix. Principal component analysis can be used to determine the rotation angle so that the combined matrix reflects the main directional characteristics of the circuit board wiring and impedance distribution. For example, assuming the density weight matrix is ​​D, the impedance weight matrix is ​​Z, and the rotation matrix is ​​R, the anisotropy matrix A can be expressed as: A = R * (αD + βZ) * R^T, where α and β are weighting coefficients.

[0105] Then, an exponential variogram is constructed using the anisotropy matrix. The variogram includes the nugget effect value C0, the sill value C, and the spatial vector product term of the anisotropy matrix. It can be expressed as: γ(h) = C0 + C * [1 - exp(-h^T * A * h)], where h is the spatial distance vector. The nugget effect value C0 represents random variation at the microscale, and the sill value C represents the limiting value of spatial correlation.

[0106] Next, an optimization objective function is established, including interpolation prediction error terms, spatial smoothing constraint terms, and anisotropic characteristic terms. Gaussian process regression is used to establish the mapping relationship between the parameters and the objective function. The nugget effect value, sill value, and search radius of the kriging interpolation are iteratively optimized using the expectation maximization improvement criterion. For example, initial values ​​C0=0.1, C=1, and search radius r=10 can be set, and optimization can be performed within the ranges [0, 0.5], [0.5, 2], and [5, 20] until the objective function converges.

[0107] The Kriging weighting coefficients are calculated based on the optimized variogram, and the electromagnetic field distortion estimate of the interpolation point is obtained by solving the Kriging equations. For each interpolation point, known sampling points in its neighborhood are selected, the Kriging equations are constructed and solved to obtain the distortion estimate of that point.

[0108] Finally, orthogonal wavelet basis functions are used to perform multi-scale decomposition of the electromagnetic field distortion estimate. Haar wavelets or Daubechies wavelets can be selected to decompose the distorted field into coarsest-scale approximation coefficients and detail coefficients at different scales. For example, for a 64×64 distorted field, a three-level decomposition can be performed to obtain 8×8 approximation coefficients and three sets of 8×8, 16×16, and 32×32 detail coefficients. Reconstructing these coefficients generates the electromagnetic field distortion distribution map.

[0109] In visualization, pseudo-color coding is used to represent distortion intensity, with blue indicating low-distortion areas and red indicating high-distortion areas. Contour lines are also overlaid to display distortion gradient changes; 5-10 contour lines can be selected to reflect the main gradient characteristics. This multi-scale, multi-level representation method reflects both the overall distribution trend of the distortion field and the fine structure of local areas, facilitating designers to quickly identify key regions and perform targeted optimizations.

[0110] In this embodiment, by introducing spatial anisotropy constraints on circuit board wiring density and impedance distribution, the constructed anisotropy matrix enhances the adaptability of the interpolation model to complex circuit board structures. The design of an exponential variogram effectively captures the spatial variation characteristics of the electromagnetic field, while combining interpolation prediction error and spatial smoothing constraints optimizes interpolation accuracy. Parameter optimization using Gaussian process regression significantly improves the performance of Kriging interpolation, enhancing the accuracy of electromagnetic field distortion estimation at the interpolation points. Finally, multi-scale decomposition using orthogonal wavelet basis functions clearly presents distortion information at different scales. The generated electromagnetic field distortion distribution map, using pseudo-color coding and contour overlay, intuitively displays the distortion intensity and gradient changes, providing crucial decision support for circuit board design and troubleshooting.

[0111] S102. Based on the electromagnetic field distortion distribution map, the fault-sensitive areas of the circuit board are divided. An adaptive sampling array is deployed in the fault-sensitive areas. The adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed based on the multi-dimensional signals collected by the adaptive sampling array. The fault feature vector is input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board. A fault risk assessment matrix is ​​generated based on the performance degradation rate.

[0112] Based on the electromagnetic field distortion distribution map, fault-sensitive areas of the circuit board are defined. Areas with high distortion are marked as high-sensitivity areas, areas with moderate distortion as medium-sensitivity areas, and areas with low distortion as low-sensitivity areas. Adaptive sampling arrays, including temperature sensing units, voltage sensing units, and electromagnetic sensing units, are deployed in the high-sensitivity and medium-sensitivity areas. These sensing units can automatically adjust the sampling frequency and accuracy according to environmental changes to obtain more accurate multidimensional signals.

[0113] A fault feature vector is constructed using temperature, voltage, and electromagnetic signals collected by an adaptive sampling array. This vector contains multiple feature parameters, such as temperature change rate, voltage ripple coefficient, and electromagnetic interference intensity. The constructed fault feature vector is then input into a pre-trained reinforcement learning model. This model employs a deep Q-network algorithm to continuously optimize its decision-making strategy through interaction with the environment. The model's output is the performance degradation rate of each functional area of ​​the circuit board, representing the probability of failure in each area. A fault risk assessment matrix is ​​generated based on the performance degradation rate, clearly displaying the fault risk level of each area of ​​the circuit board.

[0114] In one alternative embodiment,

[0115] A fault feature vector is constructed based on the multidimensional signals acquired by the adaptive sampling array. This fault feature vector is then input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board. A fault risk assessment matrix is ​​generated based on the performance degradation rate, including:

[0116] A state space is constructed based on the multidimensional signals collected by the adaptive sampling array. The state space includes the state of functional units, operating parameters, and historical diagnostic results. An action space is constructed based on the action space, which includes operating condition identification and risk assessment actions.

[0117] A functional association graph is constructed based on the state space. The vertex set in the functional association graph represents the functional units of the circuit board, and the edge set represents the signal coupling relationship between the functional units. Based on the functional association graph, the mutual influence between the functional units is modeled through a graph attention mechanism to obtain fault characteristics.

[0118] A top-level strategy network with an execution entity and a judge entity structure is used for work condition identification. The execution entity network processes the work condition state vector through a residual connection layer and a batch normalization layer to obtain the work condition category probability distribution. The judge entity network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function based on the work condition identification accuracy and risk assessment effect.

[0119] A variational autoencoder model is constructed, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence composed of the fault features and the probability distribution of the working condition category into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory.

[0120] A causal temporal convolutional network is introduced into the posterior distribution space of the latent variables. The causal temporal convolutional network obtains the performance degradation evolution law through dilated convolution and performs multiple forward propagations using a random deactivation method to obtain the performance degradation prediction result.

[0121] A graph converter model is constructed, and the circuit board is modeled as a heterogeneous graph network. The node features of the heterogeneous graph network include the failure probability, performance index and topology features of the functional unit. The performance degradation prediction results are input into the graph converter model, and the risk propagation mode is learned through a multi-head attention mechanism.

[0122] A causal graph is constructed based on the risk propagation model. The causal graph is then structured using variational reasoning. The fault propagation strength between the functional units is evaluated through intervention calculus, and a fault risk assessment matrix is ​​generated.

[0123] For example, based on the multidimensional signals acquired by the adaptive sampling array, a state space is first constructed. This state space includes three dimensions: functional unit states, operating parameters, and historical diagnostic results. Functional unit states describe the operating status of each functional module on the circuit board, such as voltage, current, and temperature; operating parameters reflect external environmental conditions, such as ambient temperature, humidity, and vibration; and historical diagnostic results record past fault diagnosis situations. Simultaneously, an action space is constructed, including two types of actions: operating condition identification and risk assessment. The operating condition identification action is used to determine the current working environment, and the risk assessment action is used to assess the degree of performance degradation of each functional unit.

[0124] Based on the constructed state space, a functional association graph is further constructed. In this graph, the vertex set represents the various functional units of the circuit board, such as power modules, signal processing modules, and storage modules; the edge set represents the signal coupling relationships between functional units, such as data transmission and energy transfer. The functional association graph is modeled using a graph attention mechanism to calculate the correlation weights between different functional units, thereby obtaining fault characteristics reflecting the overall state of the circuit board.

[0125] Next, a top-level policy network with an executive-evaluator structure is used for work condition identification. The executive network consists of multiple residual connection layers and batch normalization layers, used to process the work condition state vector and output the probability distribution of the work condition category. For example, possible work condition categories include normal operation, high temperature environment, and strong vibration environment. The evaluator network evaluates the value function of the current state. An experience replay buffer is also constructed to store state transition samples. A reward function is designed based on the accuracy of work condition identification and the effectiveness of risk assessment to guide the reinforcement learning training process.

[0126] Then, a variational autoencoder model is constructed. The encoder employs a bidirectional long short-term memory network to map the input sequence, composed of fault features and operational condition category probability distributions, into the posterior distribution of latent variables. The decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory. This effectively extracts temporal features and predicts future performance degradation trends.

[0127] A causal temporal convolutional network is introduced into the posterior distribution space of latent variables. This network expands the receptive field through dilated convolutional layers, effectively capturing long-term dependencies and thus obtaining the evolutionary patterns of performance degradation. Multiple forward propagations are performed using random deactivation to obtain performance degradation predictions with uncertainty. This method can assess the reliability of the predictions and provide more information for subsequent decision-making.

[0128] Next, a graph transformer model is constructed, modeling the circuit board as a heterogeneous graph network. In this network, node features include the failure probability, performance indicators, and topological characteristics of the functional units. The performance degradation prediction results obtained in the previous step are input into the graph transformer model, and a multi-head attention mechanism is used to learn the risk propagation patterns among different functional units. This takes into account the mutual influence between different parts of the circuit board, resulting in a more accurate overall risk assessment.

[0129] Finally, a causal graph is constructed based on the learned risk propagation pattern. Variational inference is used to learn the structure of the causal graph and determine the causal relationships between functional units. Interventional calculus is used to assess the fault propagation strength between functional units, i.e., the extent to which a fault in one unit affects other units. Finally, a fault risk assessment matrix is ​​generated, where each element represents the fault propagation strength of the corresponding functional unit pair.

[0130] In this embodiment, the fault feature vector constructed from multidimensional signals collected by an adaptive sampling array provides rich input for the reinforcement learning model, thereby outputting the performance degradation rate of each functional area. The design of the state space and action space enables the system to dynamically identify operating conditions and assess risks. The constructed functional association graph effectively captures the coupling relationships between functional units, improving the ability to extract fault features. The combination of the execution and evaluation networks improves the accuracy of operating condition identification and risk assessment, while the constructed variational autoencoder model further refines the reconstruction of performance degradation trajectories. The causal temporal convolutional network reveals the evolutionary law of performance degradation, enhancing predictive ability. The application of the graph transformer model allows for full utilization of the features of each node in the heterogeneous graph network, and leverages a multi-head attention mechanism to deeply learn risk propagation patterns. Finally, the generated fault risk assessment matrix provides a scientific basis for circuit board fault early warning and maintenance decisions, significantly improving the system's reliability and intelligence level.

[0131] In one alternative embodiment,

[0132] A causal graph is constructed based on the aforementioned risk propagation model. A variational inference method is used to perform structural learning on the causal graph. Interventional calculus is used to assess the fault propagation strength between the functional units, generating a fault risk assessment matrix, including:

[0133] A neural causal graph is constructed, which includes multiple functional unit nodes and directed edges between nodes. Temporal features of each functional unit node are extracted. The generator of a variational adversarial neural network is used to map the temporal features into conditional latent variables. The discriminator of the variational adversarial neural network evaluates the difference between the conditional latent variables and the true distribution to obtain a temporal feature representation.

[0134] Based on the temporal feature representation, a graph morphology adaptive layer is constructed. The graph morphology adaptive layer generates dynamic convolution kernels according to the local structural features of functional unit nodes, and adaptively adjusts the topology of the neural causal graph to obtain an optimized neural causal graph.

[0135] The optimized neural causal graph is input into the causal graph neural network. The causal embedding layer of the causal graph neural network maps functional unit nodes to the causal representation space, and the causal inference layer extracts causal dependencies through gated graph convolution.

[0136] The causal dependencies are input into a stochastic causal field model, which uses an energy function to jointly model the state of functional unit nodes, calculates the causal strength between nodes, and uses a dual attention mechanism to process the causal strength to obtain attention-enhanced causal features.

[0137] A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, maintains local risk features using residual connections, outputs propagation features, and combines the propagation features with the causal strength in a weighted manner to generate a fault risk assessment matrix. The elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

[0138] First, a neural causal graph is constructed, containing multiple nodes representing functional units and directed edges between them. For each functional unit node, temporal features, such as failure frequency and failure duration, are extracted from its historical operational data. Then, a variational adversarial neural network is used, where the generator maps the extracted temporal features to conditional latent variables, and the discriminator evaluates the difference between these conditional latent variables and the true distribution, ultimately obtaining the temporal feature representation for each functional unit node. For example, for a certain engine functional unit, features such as the number of failures per month and the average repair time over the past year are extracted, and after processing by the variational adversarial neural network, a 64-dimensional vector is obtained as its temporal feature representation.

[0139] Next, a graph morphology adaptive layer is constructed based on temporal feature representation. This layer dynamically generates convolutional kernels based on the local structural features of each functional unit node (such as the number of neighboring nodes and edge weights) to adaptively adjust the topology of the neural causal graph. Specifically, a graph attention network can be used to calculate the attention coefficients between nodes, and the edge weights can be dynamically adjusted based on these attention coefficients to obtain the optimized neural causal graph. For example, if the attention coefficients between a functional unit node and its three neighboring nodes are 0.4, 0.3, and 0.3, the weights of the corresponding edges can be adjusted accordingly.

[0140] The optimized causal graph is input into a causal graph neural network for processing. The causal embedding layer of this network first maps functional unit nodes to a causal representation space, representing each node as a low-dimensional vector. Then, the causal inference layer extracts the causal dependencies between nodes through gated graph convolution operations. Multiple gated graph convolutions can be configured, with each layer aggregating information from neighboring nodes and updating the representation of the current node. The final output is a feature representing the causal dependencies between nodes.

[0141] The aforementioned causal dependency characteristics are input into a stochastic causal field model. This model uses an energy function to model the joint distribution of the states of functional unit nodes, calculating the causal strength between nodes. Specifically, a potential function can be defined to characterize the energy of a single node and node pairs, and then the joint probability distribution of node states is obtained through normalization, thereby calculating the causal strength between nodes. Next, a dual attention mechanism is used to process the causal strength, that is, attention is considered simultaneously in the spatial and channel dimensions, resulting in attention-enhanced causal features. For example, for two functional unit nodes, the initial causal strength calculated is 0.7, which may be adjusted to 0.8 after attention enhancement.

[0142] Finally, a risk propagation network is constructed based on attention-enhanced causal features. This network models the propagation of fault risk between functional units through graph diffusing convolutions and employs residual connections to preserve local risk features. In practice, multiple layers of graph diffusing convolutions can be stacked, with each layer propagating and updating risk information. After the network outputs the propagation features, they are weighted and combined with the previously obtained causal strengths to generate a fault risk assessment matrix. Each element in this matrix represents the degree of risk propagation between two corresponding functional unit nodes. For example, in the generated 10x10 risk assessment matrix, the value of element (2, 5) is 0.6, indicating that the degree of risk propagation from functional unit 2 to functional unit 5 is 0.6.

[0143] In this embodiment, the constructed neural causal graph extracts the temporal features of functional units and utilizes conditional latent variables generated by a variational adversarial neural network to provide strong temporal support for the fault propagation model. The graph morphology adaptive layer optimizes the topology of the neural causal graph through dynamic convolutional kernels, enhancing its sensitivity to local features. The causal embedding and inference layers of the causal graph neural network effectively extract causal dependencies, laying the foundation for subsequent causal strength calculations. The stochastic causal field model jointly models the states of functional units through energy functions, calculates the causal strength between nodes, and further enhances causal features through a dual attention mechanism. Finally, the risk propagation network models fault risk using graph diffusion convolution, and the risk assessment matrix generated by combining propagation features and causal strength can intuitively reflect the degree of risk propagation between functional units. The application of this series of technologies not only improves the accuracy of fault warnings but also provides comprehensive data support and decision-making basis for circuit board reliability management.

[0144] S103. Based on the fault risk assessment matrix, the circuit board is functionally reconstructed, the computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault tolerance mechanism for the circuit board is established, a task load allocation strategy is generated based on the dynamic fault tolerance mechanism, the task load allocation strategy is deployed to the field-programmable gate array (FPGA) of the circuit board, the circuit board is autonomously repaired by adjusting the logic structure of the FPGA, the operating data of the circuit board after repair is collected, the operating data is compared with the fault feature vector before repair, the repair effect is verified and a diagnostic report is output.

[0145] Based on a fault risk assessment matrix, the circuit board is functionally reconfigured. Computational tasks in high-risk areas are migrated to low-risk areas to reduce the overall system failure probability. A dynamic fault-tolerance mechanism is established to monitor the performance status of each area in real time, automatically activating backup resources when the performance of a certain area degrades. A task load allocation strategy is generated based on the dynamic fault-tolerance mechanism to rationally allocate computing resources and avoid single points of failure.

[0146] The generated task load distribution strategy is deployed to the field-programmable gate array (FPGA) of the circuit board. By reconfiguring the FPGA's logic structure, the circuit board achieves autonomous repair. Specifically, the configuration of the FPGA's internal lookup tables and interconnect resources is modified, and the hardware descriptions of each functional module are redefined, thereby bypassing or replacing faulty areas and restoring system functionality.

[0147] After completing the autonomous repair, operational data of the repaired circuit board is collected, including parameters such as throughput, power consumption, and temperature of each functional module. This operational data is compared and analyzed with the fault feature vector before repair to evaluate the repair effect. If key performance indicators show significant improvement, the repair is considered successful; otherwise, further optimization of the repair strategy is required. Finally, a detailed diagnostic report is generated based on the analysis results, including information such as fault type, location, severity, and repair measures, providing a reference for subsequent maintenance.

[0148] In one alternative embodiment,

[0149] Based on the fault risk assessment matrix, the circuit board is functionally reconfigured, and computational tasks in high-risk areas are migrated to low-risk areas. A dynamic fault tolerance mechanism for the circuit board is established, and a task load allocation strategy is generated based on the dynamic fault tolerance mechanism, including:

[0150] The incoming risk value and outgoing risk value of each functional unit are calculated based on the fault risk assessment matrix. The incoming risk value represents the degree of risk impact of other functional units on the target functional unit, and the outgoing risk value represents the degree of risk propagation of the target functional unit to other functional units.

[0151] The weighted fusion of the incoming risk value and the outgoing risk value yields the comprehensive risk level of each functional unit. Based on the comprehensive risk level, a migration optimization model is established for the computational tasks on the circuit board.

[0152] A set of candidate migration schemes is generated based on the migration optimization model. The overall system risk value is calculated for each candidate scheme in the set of candidate migration schemes. The candidate scheme with the minimum overall system risk value is selected as the optimal task allocation scheme.

[0153] According to the optimal task allocation scheme, a three-module redundancy structure is constructed in each functional unit. The three-module redundancy structure achieves reliable data output through parallel data processing and majority voting selection mechanism.

[0154] Collect real-time load data of each functional unit, calculate the load distribution status based on the processing capacity of the functional unit, and calculate the deployment score for the task to be deployed based on the load distribution status.

[0155] The task priority is calculated by combining the task importance index with the comprehensive risk level, and a task queue based on priority is generated. The task priority in the task queue is dynamically adjusted according to the load distribution status.

[0156] An initial task allocation scheme is generated based on the task queue and the deployment score. The initial allocation scheme is then iteratively optimized by combining the risk assessment matrix and the processing capacity of each functional unit, and a final task load allocation strategy is output, which includes task deployment location, execution sequence and load adjustment parameters.

[0157] First, the inbound and outbound risk values ​​of each functional unit are calculated based on the fault risk assessment matrix. The inbound risk value characterizes the degree of risk impact from other functional units on the target functional unit, while the outbound risk value characterizes the degree of risk propagation from the target functional unit to other functional units. Specifically, the inbound risk value can be obtained by summing the row elements related to the target functional unit in the fault risk assessment matrix, and the outbound risk value can be obtained by summing the column elements. For example, for a certain functional unit A, its inbound risk value is 2.3 and its outbound risk value is 1.8.

[0158] Then, the incoming and outgoing risk values ​​are weighted and fused to obtain the comprehensive risk level of each functional unit. Weights of 0.6 and 0.4 can be used to weight the incoming and outgoing risk values ​​respectively to obtain the comprehensive risk level. Taking functional unit A as an example, its comprehensive risk level is 2.3 × 0.6 + 1.8 × 0.4 = 2.1. Based on the calculated comprehensive risk levels of each functional unit, a migration optimization model is established for the computational tasks on the circuit board. This model aims to minimize the overall system risk, with the processing capacity of the functional units as a constraint.

[0159] Next, a set of candidate migration schemes is generated based on the migration optimization model. Multiple candidate schemes can be generated using intelligent optimization algorithms such as genetic algorithms, each scheme including the task allocation among functional units. The overall system risk value is calculated for each candidate scheme in the set, which can be obtained by summing the products of the comprehensive risk of each functional unit and the amount of task it undertakes. The candidate scheme with the minimum overall system risk value is selected as the optimal task allocation scheme.

[0160] Based on the optimal task allocation scheme, a three-module redundancy structure is constructed in each functional unit. This structure contains three functionally identical processing modules, achieving reliable data output through parallel data processing and a majority voting mechanism. Specifically, input data is simultaneously fed into the three processing modules for computation, and the outputs of the three modules are compared. The result of at least two modules being consistent is selected as the final output. This mechanism effectively prevents system errors caused by single points of failure.

[0161] Real-time load data from each functional unit is collected, and the load distribution is calculated based on the processing capacity of each unit. Load data can be obtained by monitoring indicators such as CPU utilization and memory usage of functional units in real time. The ratio of real-time load to processing capacity is defined as the load rate, thus yielding the load distribution of the entire system. For example, if a functional unit has a real-time CPU utilization of 60%, a memory usage of 70%, and a processing capacity limit of 80%, then the load rate of that unit is (60% + 70%) / (2 × 80%) = 81.25%.

[0162] Deployment scores are calculated for tasks to be deployed based on load distribution. The deployment score is measured by the degree of matching between the task's resource requirements and the remaining resources of the functional unit; a higher matching degree results in a higher score. For example, if a task to be deployed requires 20% CPU resources and 30% memory resources, and for the aforementioned functional unit, its remaining CPU resources are 20% and its remaining memory resources are 10%, then the deployment score for this task in this unit can be calculated as (20% / 20% + 10% / 30%) / 2 = 75%.

[0163] Task priorities are calculated by combining task importance metrics with overall risk levels, generating a priority-based task queue. Task importance can be categorized into different levels based on business needs, and the task priority is obtained by weighting the overall risk level. The task priorities in the task queue are dynamically adjusted according to the load distribution. When a functional unit is overloaded, its high-priority tasks are migrated to units with lower loads.

[0164] Finally, an initial task allocation scheme is generated based on the task queue and deployment score. This scheme is then iteratively optimized by combining the risk assessment matrix and the processing capacity of each functional unit. During optimization, parameters such as task deployment location and execution sequence are adjusted to minimize overall system risk while achieving load balancing. The final output is a final task load allocation strategy that includes task deployment location, execution sequence, and load adjustment parameters. This strategy can be dynamically adjusted based on real-time load conditions to ensure system reliability and performance.

[0165] In this embodiment, the inbound and outbound risk values ​​calculated through the fault risk assessment matrix provide a quantitative basis for the comprehensive risk level of each functional unit, promoting the effective migration of computing tasks. In the migration optimization model, the task allocation scheme with the lowest overall system risk value is selected to ensure that the system maintains overall performance stability while reducing the workload in high-risk areas. The construction of a three-module redundancy structure, through parallel processing and majority voting mechanisms, further enhances the reliability of data output. Real-time load data collection and analysis enable the load distribution status to dynamically reflect the actual system operation, providing a scientific basis for task priority ranking. The final generated task load allocation strategy not only achieves intelligent task scheduling and optimization but also allows for real-time adjustments based on risk assessment and the processing capacity of functional units, improving the system's adaptability and efficiency. This scheme provides strong support for circuit board fault management and resource optimization, promoting intelligent development.

[0166] In one alternative embodiment,

[0167] The task load distribution strategy is deployed to the field-programmable gate array (FPGA) of the circuit board. The circuit board is then autonomously repaired by adjusting the logic structure of the FPGA. Operational data of the repaired circuit board is collected, and this data is compared with the fault feature vector before repair to verify the repair effect and output a diagnostic report, including:

[0168] A state machine execution model is established based on the received task load allocation strategy, and a state transition rule base containing state transition conditions and trigger thresholds is generated. The state machine execution model includes idle state, loading start state, loading state, verification state, and switching state.

[0169] Read the state transition conditions in the state transition rule base, calculate the mapping relationship between the storage address of the configuration bitstream and the reconfigurable area of ​​the FPGA, and generate the configuration bitstream loading control signal according to the mapping relationship;

[0170] A double-buffer structure is constructed based on the loading control signal, and a buffer mutex lock and a buffer status flag are set. The buffer status flag indicates the current read / write status of the buffer.

[0171] The status flag of the buffer is detected. When data is written to one buffer, the data output strobe signal of the other buffer is set according to the mutex lock.

[0172] The configuration bitstream is written into the writable buffer of the double-buffered structure. After the writing is completed, the status flag of the buffer is updated, triggering the state machine execution model to switch states.

[0173] Collect functional unit operating status data, timing parameter data, and resource usage data in the FPGA, generate operating status feature vectors, perform correlation analysis between the operating status feature vectors and preset fault feature vectors, calculate functional unit status recovery rate, timing parameter recovery rate, and resource utilization optimization rate, and generate repair effect evaluation indicators.

[0174] A multi-level scoring model is established based on the repair effect evaluation indicators. Each evaluation indicator is weighted according to the weight set by the task priority identifier to generate a comprehensive repair score and output a diagnostic report containing fault location information and repair status information.

[0175] For example, firstly, a state machine execution model is established based on the received task load allocation strategy. This model includes five states: idle, load start, load, verification, and switch. Simultaneously, a state transition rule base is generated, containing the transition conditions and trigger thresholds between each state. For instance, the condition for switching from the idle state to the load start state could be receiving a new task request, and the trigger threshold could be set to a task priority greater than 8.

[0176] Next, the state transition conditions in the state transition rule base are read, and the mapping relationship between the storage address of the configuration bitstream and the reconfigurable regions of the FPGA is calculated. Assuming the FPGA has four reconfigurable regions R1-R4, and the configuration bitstream is stored at addresses 0x1000-0x4000, the following mapping can be established: R1 corresponds to 0x1000-0x1FFF, R2 corresponds to 0x2000-0x2FFF, and so on. The loading control signal for the configuration bitstream is then generated based on this mapping relationship.

[0177] Then, a double-buffered structure is constructed based on the load control signals. Two buffers, A and B, are set up with a size of 4KB, along with a mutex and a buffer status flag. flag=0 indicates that A can be written and B can be read, and flag=1 indicates that B can be written and A can be read.

[0178] Next, the buffer status flag is checked. When flag=0, data is written to buffer A, and the data output strobe signal of buffer B is set according to the mutex, making data in B available for output. The reverse is also true.

[0179] The configuration bitstream is written to the currently writable buffer, and the flag is updated after the write is complete. For example, if the current flag is 0, writing data to A will set the flag to 1. This will trigger the state machine to switch from the loading startup state to the loading state.

[0180] Subsequently, the operating status, timing parameters, and resource usage data of each functional unit in the FPGA are collected to generate an operating status feature vector. This vector is then correlated with a preset fault feature vector to calculate various recovery rates and optimization rates. For example, if a functional unit recovers from a fault to normal operation, its recovery rate is 100%; if timing parameters are optimized from 200ns to 150ns, the timing parameter recovery rate is 25%; and if resource utilization increases from 60% to 80%, the resource utilization optimization rate is 33.33%.

[0181] Finally, a multi-level scoring model is established based on the above evaluation indicators. Assuming the task priority is 9, the weights for state recovery rate, timing recovery rate, and resource optimization rate can be set to 0.5, 0.3, and 0.2, respectively. A weighted comprehensive repair score, for example, 90 points, is obtained through calculation. The output diagnostic report includes information such as the fault location (e.g., region R2) and the repair status (e.g., back to normal).

[0182] In this embodiment, by deploying the task load distribution strategy to a Field Programmable Gate Array (FPGA), the system can flexibly adjust its logic structure to cope with fault conditions. The establishment of a state machine execution model ensures the orderly and controllable nature of the repair process. Precise management of state transitions through a state transition rule base optimizes the response speed and efficiency of the repair process. The use of a double-buffered structure improves the parallelism of data writing and output, reducing latency during the repair process. After repair, the system's acquisition and analysis of operational status data quantifies the state recovery of functional units, the optimization of timing parameters, and resource utilization. Correlation analysis with preset fault feature vectors provides a comprehensive evaluation of the repair effect. A multi-layer scoring model weights the evaluation indicators, generating a comprehensive repair score that provides an intuitive quantitative result for the fault repair effect. The final diagnostic report not only includes fault location information but also reflects the repair status, helping engineers quickly identify problems and optimize subsequent maintenance strategies. This solution significantly improves the board's adaptability and maintenance efficiency, providing crucial assurance for the reliable operation of intelligent systems.

[0183] Figure 2 This is a schematic diagram of the structure of an artificial intelligence-based circuit board fault diagnosis system according to an embodiment of the present invention, as shown below. Figure 2 As shown, the system includes:

[0184] The first unit is used to construct a three-dimensional electromagnetic field simulation model of the circuit board. Multiple virtual sensing probes are set in the three-dimensional electromagnetic field simulation model. The virtual sensing probes correspond one-to-one with the positions of the physical sensors on the circuit board. The measured data of the physical sensors and the simulation data of the virtual sensing probes are collected. By comparing the deviation values ​​of the measured data and the simulation data, an abnormal behavior pattern library of the circuit board is established. A backpropagation neural network is constructed based on the abnormal behavior pattern library. The electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the backpropagation neural network, and an electromagnetic field distortion distribution map is generated.

[0185] The second unit is used to divide the fault-sensitive areas of the circuit board based on the electromagnetic field distortion distribution map, and deploy an adaptive sampling array in the fault-sensitive areas. The adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed based on the multi-dimensional signals collected by the adaptive sampling array. The fault feature vector is input into a pre-trained reinforcement learning model to output the performance degradation rate of each functional area of ​​the circuit board, and a fault risk assessment matrix is ​​generated based on the performance degradation rate.

[0186] The third unit is used to reconstruct the circuit board's functions based on the fault risk assessment matrix, migrate computing tasks from high-risk areas to low-risk areas, establish a dynamic fault tolerance mechanism for the circuit board, generate a task load allocation strategy based on the dynamic fault tolerance mechanism, deploy the task load allocation strategy to the field-programmable gate array (FPGA) of the circuit board, perform autonomous repair on the circuit board by adjusting the logic structure of the FPGA, collect the operating data of the circuit board after repair, compare the operating data with the fault feature vector before repair, verify the repair effect, and output a diagnostic report.

[0187] A third aspect of the present invention,

[0188] An electronic device is provided, comprising:

[0189] processor;

[0190] Memory used to store processor-executable instructions;

[0191] The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0192] Fourth aspect of the embodiments of the present invention,

[0193] A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0194] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0195] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A circuit board fault diagnosis method based on artificial intelligence, characterized in that: include: Constructing a three-dimensional electromagnetic field simulation model of a circuit board, setting a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, wherein the virtual sensor probes correspond one-to-one to the physical sensor positions of the circuit board, collecting measured data of the physical sensor and simulation data of the virtual sensor probes, establishing an abnormal behavior pattern library of the circuit board by comparing the deviation values ​​between the measured data and the simulation data, constructing a back propagation neural network according to the abnormal behavior pattern library, calculating the degree of electromagnetic field distortion of each functional area of ​​the circuit board based on the back propagation neural network, and generating an electromagnetic field distortion distribution map; Based on the electromagnetic field distortion distribution map, the fault-sensitive area of ​​the circuit board is divided, and an adaptive sampling array is deployed in the fault-sensitive area, wherein the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit, and an electromagnetic sensing unit. A fault feature vector is constructed according to the multi-dimensional signal collected by the adaptive sampling array, and the fault feature vector is input into a pre-trained reinforcement learning model, and the performance degradation rate of each functional area of ​​the circuit board is output, and a fault risk assessment matrix is ​​generated according to the performance degradation rate; The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, the task load distribution strategy is deployed to the field programmable gate array of the circuit board, the circuit board is autonomously repaired by adjusting the logical structure of the field programmable gate array, the operating data of the repaired circuit board is collected, the operating data is compared with the fault feature vector before repair, the repair effect is verified and a diagnostic report is output.

2. The method according to claim 1, characterized in that By comparing the deviation values ​​of the measured data and the simulated data, an abnormal behavior pattern library of the circuit board is established, a back propagation neural network is constructed according to the abnormal behavior pattern library, and the electromagnetic field distortion degree of each functional area of ​​the circuit board is calculated based on the back propagation neural network to generate an electromagnetic field distortion distribution map, including: The time domain statistical features are generated by the adaptive wavelet decomposition module, the frequency domain spectrum features are generated by the fast Fourier transform module, and the attention mechanism is used to dynamically assign weights to the time domain statistical features and the frequency domain spectrum features to form a fusion feature vector; The recursive least squares algorithm is used to update the feature covariance matrix, and the Mahalanobis distance between the measured feature vector and the simulated feature vector is calculated based on the updated feature covariance matrix to obtain the abnormality sequence; A dual-criteria density clustering method based on local density and distance distribution is used to determine the cluster center of the abnormal degree sequence, and the clustering parameters are adaptively adjusted using the fractal dimension to form an abnormal pattern sequence. The abnormal mode sequence is decomposed through empirical mode decomposition to obtain the intrinsic mode function, and the evolution characteristics of the intrinsic mode function are extracted using a sliding time window. The time series association rules of the evolution characteristics are mined based on the improved Apriori algorithm to establish an abnormal behavior pattern library. A deep hybrid neural network is trained based on the abnormal behavior pattern library. The spatial domain features are extracted through the residual connection convolution layer. The temporal domain features are extracted using the long short-term memory unit and the gated recurrent unit. The topological domain features are extracted using the graph convolution layer. The extracted features are combined and input into the fully connected layer to output the electromagnetic field distortion prediction value. The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram. The Bayesian optimization algorithm is used to adjust the Kriging interpolation parameters. The electromagnetic field distortion prediction values ​​are spatially interpolated. The multi-resolution distortion distribution representation is constructed through wavelet transform to generate the electromagnetic field distortion distribution map.

3. The method according to claim 2, characterized in that The spatial anisotropy constraints of circuit board wiring density and impedance distribution are introduced into the variogram, and the Kriging interpolation parameters are adjusted by Bayesian optimization algorithm. The electromagnetic field distortion prediction value is spatially interpolated, and a multi-resolution distortion distribution representation is constructed by wavelet transform. The electromagnetic field distortion distribution map is generated, including: Constructing a density weight matrix based on the wiring density distribution of the circuit board, and constructing an impedance weight matrix based on the impedance distribution of the circuit board, and combining the density weight matrix and the impedance weight matrix through a rotation matrix to form an anisotropic matrix; Using the anisotropy matrix to construct an exponential variogram, the variogram includes a nugget effect value, a sill value, and a spatial vector product term of the anisotropy matrix; An optimization objective function including an interpolation prediction error term, a spatial smoothness constraint term and an anisotropic characteristic term is established, a mapping relationship between parameters and the objective function is established by using Gaussian process regression, and the nugget effect value, the sill value and the search radius of the Kriging interpolation of the variogram are iteratively optimized by maximizing the expected improvement criterion; The Kriging weight coefficient is calculated based on the optimized variogram, and the estimated value of the electromagnetic field distortion of the interpolation point is obtained by solving the Kriging equations; The electromagnetic field distortion estimation value is decomposed at multiple scales using orthogonal wavelet basis functions to obtain approximate coefficients of the coarsest scale and detail coefficients of different scales. The approximate coefficients and the detail coefficients are reconstructed to generate an electromagnetic field distortion distribution map. The electromagnetic field distortion distribution map uses pseudo-color coding to represent the distortion intensity and superimposes contour lines to display the distortion gradient changes.

4. The method according to claim 1, characterized in that Constructing a fault feature vector according to the multidimensional signal collected by the adaptive sampling array, inputting the fault feature vector into a pre-trained reinforcement learning model, outputting the performance degradation rate of each functional area of ​​the circuit board, and generating a fault risk assessment matrix according to the performance degradation rate includes: Constructing a state space based on the multidimensional signals collected by the adaptive sampling array, wherein the state space includes functional unit states, operating parameters and historical diagnosis results, and constructing an action space, wherein the action space includes operating condition identification and risk assessment actions; Based on the state space, a functional association graph is constructed, wherein a vertex set in the functional association graph represents a functional unit of a circuit board, and an edge set represents a signal coupling relationship between the functional units; based on the functional association graph, mutual influences between the functional units are modeled through a graph attention mechanism to obtain fault characteristics; The top-level policy network of the executive body and the judge body structure is used for working condition identification. The executive body network processes the working condition state vector through the residual connection layer and the batch normalization layer to obtain the working condition category probability distribution. The judge body network evaluates the state value function, constructs an experience replay buffer to store state transition samples, and constructs a reward function according to the working condition identification accuracy and risk assessment effect. Constructing a variational autoencoder model, wherein the encoder uses a bidirectional long short-term memory network to map the input sequence consisting of the fault characteristics and the operating condition category probability distribution into a latent variable posterior distribution, and the decoder uses a transposed convolutional network to reconstruct the performance degradation trajectory; A causal temporal convolutional network is introduced into the latent variable posterior distribution space, wherein the causal temporal convolutional network obtains the performance degradation evolution law through hole convolution, and performs multiple forward propagations using random inactivation to obtain the performance degradation prediction result; Constructing a graph converter model, modeling the circuit board as a heterogeneous graph network, wherein the node features of the heterogeneous graph network include the failure probability, performance index and topological features of the functional unit, inputting the performance degradation prediction result into the graph converter model, and learning the risk propagation model through a multi-head attention mechanism; A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix.

5. The method according to claim 4, characterized in that A causal graph is constructed based on the risk propagation model, a variational reasoning method is used to perform structural learning on the causal graph, and the fault propagation intensity between the functional units is evaluated through intervention calculation to generate a fault risk assessment matrix including: Constructing a neural causal graph, the neural causal graph includes directed edges between multiple functional unit nodes, extracting time series features of each functional unit node, using a variational adversarial neural network generator to map the time series features into conditional latent variables, and using a variational adversarial neural network discriminator to evaluate the difference between the conditional latent variables and the true distribution to obtain a time series feature representation; Based on the temporal feature representation, a graph morphology adaptive layer is constructed, wherein the graph morphology adaptive layer generates a dynamic convolution kernel according to the local structural features of the functional unit nodes, and adaptively adjusts the topological structure of the neural causal graph to obtain an optimized neural causal graph; Inputting the optimized neural causal graph into a causal graph neural network, wherein the causal embedding layer of the causal graph neural network maps the functional unit nodes to the causal representation space, and the causal reasoning layer extracts the causal dependency through gated graph convolution; The causal dependency relationship is input into a random causal field model, the random causal field model uses an energy function to perform joint distribution modeling on the states of the functional unit nodes, calculates the causal strength between the nodes, and uses a dual attention mechanism to process the causal strength to obtain an attention-enhanced causal feature; A risk propagation network is constructed based on the attention-enhanced causal features. The risk propagation network models the propagation of fault risks through graph diffusion convolution, adopts residual connections to maintain local risk features, outputs propagation features, and weightedly combines the propagation features with the causal strength to generate a fault risk assessment matrix, wherein the elements of the fault risk assessment matrix represent the degree of risk propagation between functional unit nodes.

6. The method according to claim 1, characterized in that The circuit board is functionally reconstructed according to the fault risk assessment matrix, computing tasks in high-risk areas are migrated to low-risk areas, a dynamic fault-tolerant mechanism for the circuit board is established, and a task load distribution strategy is generated based on the dynamic fault-tolerant mechanism, including: Calculate the incoming risk value and the outgoing risk value of each functional unit according to the fault risk assessment matrix, wherein the incoming risk value represents the risk impact degree of other functional units on the target functional unit, and the outgoing risk value represents the risk propagation degree of the target functional unit to other functional units; The inbound risk value and the outbound risk value are weightedly merged to obtain a comprehensive risk of each functional unit, and a migration optimization model is established for the computing tasks in the circuit board according to the comprehensive risk; Generate a set of candidate migration solutions based on the migration optimization model, calculate the overall system risk value for each candidate solution in the set of candidate migration solutions, and select the candidate solution with the minimum overall system risk value as the optimal task allocation solution; According to the optimal task allocation scheme, a three-module redundant structure is constructed in each functional unit, and the three-module redundant structure realizes reliable output of data through parallel data processing and majority voting selection mechanism; Collecting real-time load data of each functional unit, calculating the load distribution state in combination with the processing capacity of the functional unit, and calculating the deployment score for the task to be deployed according to the load distribution state; The task priority is calculated by combining the task importance index with the comprehensive risk, and a task queue based on priority sorting is generated, wherein the task priority in the task queue is dynamically adjusted according to the load distribution state; An initial task allocation plan is generated according to the task queue and the deployment score, and the initial allocation plan is iteratively optimized in combination with the risk assessment matrix and the processing capacity of each functional unit to output a final task load allocation strategy including task deployment location, execution timing and load adjustment parameters.

7. The method according to claim 1, characterized in that Deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operation data of the circuit board after the repair, compare the operation data with the fault feature vector before the repair, verify the repair effect and output a diagnostic report including: Establish a state machine execution model according to the received task load distribution strategy, and generate a state transition rule base including state transition conditions and trigger thresholds, wherein the state machine execution model includes an idle state, a loading start state, a loading state, a verification state, and a switching state; Reading the state transition condition in the state transition rule base, calculating the mapping relationship between the storage address of the configuration bit stream and the reconfigurable area of ​​the FPGA, and generating a configuration bit stream loading control signal according to the mapping relationship; Building a double buffer structure based on the load control signal, setting a buffer mutex and a buffer status flag, wherein the buffer status flag indicates a read / write status of a current buffer; Detecting the buffer state flag bit, when data is written into one buffer, setting a data output selection signal of another buffer according to the mutex lock; Writing the configuration bit stream into the writable buffer of the double buffer structure, and updating the buffer status flag after writing is completed, triggering the state machine to execute the state switching of the model; Collect the working status data, timing parameter data and resource occupancy data of the functional units in the FPGA, generate the operating status feature vector, perform correlation analysis on the operating status feature vector and the preset fault feature vector, calculate the functional unit status recovery rate, timing parameter recovery rate and resource utilization optimization rate, and generate the repair effect evaluation index; A multi-layer scoring model is established based on the repair effect evaluation indicators, and each evaluation indicator is weighted and calculated according to the weight set by the task priority identification bit to generate a comprehensive repair score, and output a diagnostic report containing fault location information and repair status information.

8. A circuit board fault diagnosis system based on artificial intelligence, used to implement the method described in any one of claims 1 to 7, characterized in that: include: The first unit is used to construct a three-dimensional electromagnetic field simulation model of a circuit board, set a plurality of virtual sensor probes in the three-dimensional electromagnetic field simulation model, the virtual sensor probes correspond to the physical sensor positions of the circuit board one by one, collect measured data of the physical sensor and simulation data of the virtual sensor probes, establish an abnormal behavior pattern library of the circuit board by comparing the deviation value between the measured data and the simulation data, construct a back propagation neural network according to the abnormal behavior pattern library, calculate the electromagnetic field distortion degree of each functional area of ​​the circuit board based on the back propagation neural network, and generate an electromagnetic field distortion distribution map; The second unit is used to divide the fault-sensitive area of ​​the circuit board based on the electromagnetic field distortion distribution map, deploy an adaptive sampling array in the fault-sensitive area, the adaptive sampling array includes a temperature sensing unit, a voltage sensing unit and an electromagnetic sensing unit, construct a fault feature vector according to the multi-dimensional signal collected by the adaptive sampling array, input the fault feature vector into a pre-trained reinforcement learning model, output the performance degradation rate of each functional area of ​​the circuit board, and generate a fault risk assessment matrix according to the performance degradation rate; The third unit is used to reconstruct the functions of the circuit board according to the fault risk assessment matrix, migrate the computing tasks in the high-risk area to the low-risk area, establish a dynamic fault-tolerant mechanism for the circuit board, generate a task load distribution strategy based on the dynamic fault-tolerant mechanism, deploy the task load distribution strategy to the field programmable gate array of the circuit board, autonomously repair the circuit board by adjusting the logical structure of the field programmable gate array, collect the operating data of the repaired circuit board, compare the operating data with the fault feature vector before repair, verify the repair effect and output a diagnosis report.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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