A method for manufacturing a trench gate MOSFET and a trench gate MOSFET

Abstract

The present application relates to semiconductor device technology, and discloses a method for manufacturing a trench gate MOSFET and a trench gate MOSFET, including: forming a substrate, a buffer layer, an N-type drift region, a P+ base region, and an N+ source electrode in sequence from bottom to top, and forming a P+ source electrode on the left and right sides of the N+ source electrode; penetrating the middle of the N+ source electrode and the P+ base region, and hollowing out the middle of the upper layer of the N-type drift region to form a trench region; forming a P-type gate electrode at the bottom of the trench region; after depositing an oxide layer on the P-type gate electrode, continuing to grow an oxide layer in the trench region to form an oxide layer groove; forming a trench gate electrode in the oxide layer groove; forming a source metal layer on the N+ source electrode and the P+ source electrode; forming two N-type gate electrodes penetrating the substrate and the buffer layer and embedded in the N-type drift region from below; and forming a drain metal layer under the substrate. The present application aims to reduce the on-resistance of the MOSFET device and improve the electrical performance of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a method for manufacturing a trench gate MOSFET, a trench gate MOSFET, a computer device, and a computer-readable storage medium. Background Art

[0002] Power MOSFET devices are gate-controlled unipolar devices because only majority carriers participate in conduction during forward conduction. Therefore, they have the advantage of fast switching speed and are mainly used in medium and low voltage and high frequency fields. Since SiC (Silicon Carbide) has the characteristics of high thermal conductivity, high electron saturation velocity, high physical and chemical stability and strong breakdown field, SiCMOSFET is widely used in power switching devices.

[0003] The on-resistance of traditional planar gate SiC MOSFET is mainly composed of trench resistance, accumulation layer resistance, JFET resistance, drift region resistance and substrate resistance. The introduction of trench gate SiC MOSFET eliminates the JFET region, increases the trench density and reduces the on-resistance of the device. However, the gate oxide at the bottom of the trench will be exposed to the high electric field in the SiC drift region, which limits the breakdown characteristics of the device. In order to solve this problem, the P-type SiC MOSFET based on the bottom of the trench gate is proposed. + -SiC shielded trench gate SiC MOSFET is proposed because P + -SiC shielding region can effectively protect the gate oxide and improve the breakdown voltage of the device. + The -SiC shielding region and the P-type SiC base region will form the JFET region resistance, thereby increasing the on-resistance of the device.

[0004] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a method for manufacturing a trench gate MOSFET and a trench gate MOSFET, aiming to reduce the on-resistance of the MOSFET device and improve the electrical performance of the device.

[0006] To achieve the above object, the present application provides a method for manufacturing a trench gate MOSFET, comprising the following steps:

[0007] A substrate, a buffer layer, an N-type drift region, a P+ base region and an N+ source are formed in sequence from bottom to top, and a P+ source is formed on both sides of the N+ source;

[0008] Penetrating the middle of the N+ source and the P+ base region, and hollowing out the middle of the upper layer of the N-type drift region to form a trench region;

[0009] forming a P-type gate at the bottom of the trench region;

[0010] After an oxide layer is deposited on the P-type gate, an oxide layer is continuously grown in the trench region to form an oxide layer groove;

[0011] forming a trench gate in the oxide layer recess;

[0012] forming a source metal layer on the N+ source and the P+ source;

[0013] forming two N-type gates penetrating the substrate and the buffer layer and embedded in the N-type drift region from below;

[0014] A drain metal layer is formed below the substrate.

[0015] Optionally, the method for manufacturing the trench gate MOSFET further includes:

[0016] In the process of forming the substrate, the doping level is 1.0×10 19 ~1.0×10 20 cm -3 N+ substrate.

[0017] Optionally, in the process of forming the substrate, the doping level is 1.0×10 19 ~1.0×10 20 cm -3 After the step of forming an N+ substrate, the step further includes:

[0018] On the substrate, the doping level was 1.0×10 16 ~1.0×10 17 cm -3 N+ buffer layer.

[0019] Optionally, the doping level on the substrate is 1.0×10 16 ~1.0×10 17 cm -3 After the step of forming an N+ buffer layer, the method further comprises:

[0020] On top of the N+ buffer layer, a doping level of 1.0×10 13 ~1.0×10 14 cm -3 N-type drift region.

[0021] Optionally, the doping level on the N+ buffer layer is 1.0×10 13 ~1.0×10 14 cm -3 After the step of forming the N-type drift region, it also includes:

[0022] The doping level is 1.0×10 16 ~1.0×10 17 cm -3 P-type ions are implanted to prepare the P+ base region.

[0023] Optionally, the doping level above the N-type drift region is 1.0×10 16 ~1.0×10 17 cm -3 After the step of implanting P-type ions to prepare a P+ base region, the method further comprises:

[0024] The doping level is 1.0×10 19 ~1.0×10 20 cm -3 N-type ion implantation is performed to prepare an N+ source.

[0025] Optionally, the doping level above the P+ base region is 1.0×10 19 ~1.0×10 20 cm -3 After the step of N-type ion implantation and preparation of the N+ source, the method further includes:

[0026] After the middle part of the N+ source is protected by an oxide mask, a doping level of 1.0×10 19 ~1.0×10 20 cm -3 P-type ions are implanted to form two P+ sources on the left and right.

[0027] Optionally, the doping level of the P-type gate is 2.0×10 16 ~2.0×10 17 cm -3 ;

[0028] And / or, the doping level of the N-type gate is 2.0×10 16 ~2.0×10 17 cm -3 .

[0029] Optionally, the P-type gate has a width of 2.5-3.5 μm and a depth of 0.5-1.5 μm;

[0030] And / or, the N-type gate has a width of 1.5-2.5 μm and a depth of 5-7 μm.

[0031] To achieve the above-mentioned purpose, the present application also provides a trench gate MOSFET, which is manufactured using the trench gate MOSFET manufacturing method as described above.

[0032] The present application provides a method for manufacturing a trench gate MOSFET and a trench gate MOSFET. When manufacturing the trench gate MOSFET, a front heterojunction structure formed by a P-type gate and an N-type drift region can reduce the corresponding JFET resistance, thereby reducing the on-resistance of the device; and when the body diode of the trench gate MOSFET is turned on, holes are more likely to flow away from the back heterojunction structure formed by the N-type gate and the N-type drift region, thereby reducing its reverse recovery time, effectively improving the reverse recovery characteristics of the MOSFET body diode, and improving the overall electrical performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the steps of a method for manufacturing a trench gate MOSFET in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a manufacturing process of a trench gate MOSFET in an embodiment of the present application;

[0035] Figure 3 Another schematic diagram of the manufacturing process of a trench gate MOSFET in an embodiment of the present application;

[0036] Figure 4 is another schematic diagram of a manufacturing process of a trench gate MOSFET in an embodiment of the present application;

[0037] Figure 5 It is another schematic diagram of the manufacturing process of the trench gate MOSFET in one embodiment of the present application;

[0038] Figure 6 This is a schematic diagram of the structure of a trench gate MOSFET in an embodiment of the present application;

[0039] Figure 7 This is an energy band comparison diagram of the front heterojunction structure in one embodiment of the present application;

[0040] Figure 8 This is an energy band comparison diagram of the back heterojunction structure in one embodiment of the present application.

[0041] Description of reference numerals:

[0042] 1. Substrate; 2. Buffer layer; 3. N-type drift region; 4. P+ base region; 5. N+ source; 6. P+ source; 7. P-type gate; 8. Oxide layer; 9. Trench gate; 10. Source metal layer; 11. N-type gate; 12. Drain metal layer.

[0043] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0045] In addition, if the descriptions of "first", "second", etc. are involved in this application, they are only used for descriptive purposes (such as for distinguishing the same or similar features), and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0046] Reference Figure 1 In one embodiment, a method for manufacturing a trench gate MOSFET includes:

[0047] Step S10, forming a substrate, a buffer layer, an N-type drift region, a P+ base region and an N+ source in sequence from bottom to top, and forming a P+ source on both sides of the N+ source;

[0048] Step S20, penetrating the middle of the N+ source and the P+ base region, and hollowing out the middle of the upper layer of the N-type drift region to form a trench region;

[0049] Step S30, forming a P-type gate at the bottom of the trench region;

[0050] Step S40, after depositing an oxide layer on the P-type gate, continue to grow an oxide layer in the trench region to form an oxide layer groove;

[0051] Step S50, forming a trench gate in the oxide layer groove;

[0052] Step S60, forming a source metal layer on the N+ source and the P+ source;

[0053] Step S70, forming two N-type gates penetrating the substrate and the buffer layer and embedded in the N-type drift region from below;

[0054] Step S80: forming a drain metal layer under the substrate.

[0055] In this embodiment, as described in step S10, refer to Figure 2, high-purity SiC materials (such as N + -SiC) substrate 1 is prepared.

[0056] A buffer layer 2 is formed on the substrate 1, and a low-doped SiC material, such as an N-type SiC material, may be used to make the buffer layer 2. The buffer layer 2 is used to reduce the electric field strength between the substrate 1 and the drift region and improve the breakdown voltage.

[0057] An N-type drift region 3 is formed on the buffer layer 2. The N-type drift region 3 may be made of a highly doped N-type SiC material. The N-type drift region 3 provides a main current path and withstands high voltage stress.

[0058] A P+ base region 4 is formed on the N-type drift region 3, which can be made of a highly doped P-type SiC material. The doping concentration and thickness of the N-type drift region 3 can be set according to the breakdown voltage, forward conduction voltage drop and dynamic characteristics of the transistor.

[0059] An N+ source 5 is formed on the P+ base region 4, and N+-SiC can be made of N-type SiC material as the N+ source 5. The N+ source 5 is the power connection point of the device, responsible for quickly injecting carriers to improve the response speed.

[0060] P-type ions are injected on the left and right sides of the N+ source 5 to form a P+ source 6 on the left and right sides of the N+ source 5. The P+ source 6 is used to form additional P-type contacts on both sides of the N+ source 5 to enhance the inflow of carriers and improve the performance of the device.

[0061] As described in step S20, refer to Figure 3 Based on the photolithography process, the middle of the N+ source 5, the middle of the P+ base region 4 and the middle of the upper layer of the N-type drift region 3 on the same longitudinal axis can be etched, thereby penetrating the middle of the N+ source 5 and the P+ base region 4, and hollowing out the middle of the upper layer of the N-type drift region 3 to form a trench area.

[0062] As described in step S30, refer to Figure 4 , you can use P + -polySi material is deposited at the bottom of the trench region to form a P-type gate 7.

[0063] As described in step S40, SiO2 is deposited on the P-type gate 7 to form a gate oxide bottom oxide layer 8 of a certain thickness. Then, thermal oxidation growth is continued in the trench area to form oxide layers 8 on the left and right sides of the trench area, so that the oxide layers 8 on the left and right sides and the gate oxide bottom oxide layer 8 form an oxide layer 8 in the shape of a groove (i.e., an oxide layer groove) on the P-type gate 7.

[0064] As described in step S50, polysilicon is deposited and etched in the oxide layer groove to form a trench gate 9. The trench gate 9 can be a polysilicon gate or an aluminum gate.

[0065] As described in step S60, refer to Figure 5 , deposit a metal layer on the N+ source 5 and the P+ source 6 as the source metal layer 10, and etch away the middle part of the source metal layer 10 above the groove area, leaving the source metal layer 10 above the left and right N+ source 5 and the P+ source 6 to form a source metal connection hole. When depositing the metal, high temperature annealing can be performed to form a source ohmic contact.

[0066] Before depositing the metal layer, a layer of isolation dielectric (not shown in the figure) may be deposited on the upper surface of the trench gate 9 to protect the trench gate 9. The isolation dielectric may be silicon dioxide, silicon nitride, borophosphosilicate glass or a combination thereof.

[0067] As described in step S70, the lower part of the N-type drift region 3, the buffer layer 2 and the substrate 1 are etched to form two fabrication windows. N + -polySi, forming two N-type gates 11 penetrating through the substrate 1 and the buffer layer 2 and embedded in the N-type drift region 3 from below.

[0068] As described in step S80, refer to Figure 6 , metal deposition is performed on the back side under the substrate 1 to form a drain metal layer 12 and a drain ohmic contact.

[0069] In this way, the P-type gate 7 and the N-type drift region 3 can form a front heterojunction structure along the direction from A1 to A2 (ie, the front P + -polySi / SiC heterojunction structure); the N-type gate 11 and the N-type drift region 3 can form a back heterojunction structure along the direction from B1 to B2 (i.e., the back N + -polySi / SiC heterojunction structure).

[0070] Reference Figure 7 , the first energy band of the front heterojunction structure of the trench gate SiC MOSFET with a P-type SiC shielding region is compared with the second energy band of the front heterojunction structure of the trench gate MOSFET of the present application (including the energy band above the Fermi level E F The conduction band bottom E C , and below the Fermi level E F The valence band top E V ); and, with reference to Figure 8 , the third energy band of the back heterojunction structure of the trench gate SiC MOSFET with a P-type SiC shielding region is compared with the fourth energy band of the back heterojunction structure of the trench gate MOSFET of the present application (including the energy band above the Fermi level EF The conduction band bottom E C , and below the Fermi level E F The valence band top E V ), it can be seen that the electrical performance of the trench gate MOSFET of the present application is better (such as lower switching loss, higher current carrying capacity, etc.).

[0071] In one embodiment, when manufacturing a trench gate MOSFET, a front heterojunction structure formed by the P-type gate 7 and the N-type drift region 3 can reduce the corresponding JFET resistance, thereby reducing the on-resistance of the device; and when the body diode of the trench gate MOSFET is turned on, holes are more likely to flow away from the back heterojunction structure formed by the N-type gate 11 and the N-type drift region 3, thereby reducing its reverse recovery time, effectively improving the reverse recovery characteristics of the MOSFET body diode, and improving the overall electrical performance of the device.

[0072] In one embodiment, based on the above embodiment, the method for manufacturing the trench gate MOSFET further includes:

[0073] In the process of forming the substrate, the doping level is 1.0×10 19 ~1.0×10 20 cm -3 N+ substrate.

[0074] In this embodiment, 1.0×10 19 ~1.0×10 20 cm -3 This range ensures that the N+ substrate 1 has a high carrier concentration and can provide good conductive properties while maintaining other characteristics of the device, such as breakdown voltage and leakage current.

[0075] Optionally, the thickness of the substrate 1 is 3-5 μm.

[0076] In one embodiment, based on the above embodiment, in the process of forming the substrate, the doping level is 1.0×10 19 ~1.0×10 20 cm -3 After the step of forming an N+ substrate, the step further includes:

[0077] On the substrate, the doping level was 1.0×10 16 ~1.0×10 17 cm -3 N+ buffer layer.

[0078] In this embodiment, the low doping concentration N+ buffer layer 2 is intended to reduce the electric field strength between the substrate 1 and the subsequent N-type drift region 3 , thereby increasing the breakdown voltage while maintaining good electrical conductivity.

[0079] Optionally, the thickness of the N+ buffer layer 2 is 3-5 μm.

[0080] In one embodiment, based on the above embodiment, the doping level is 1.0×10 16 ~1.0×10 17 cm -3 After the step of forming an N+ buffer layer, the method further comprises:

[0081] On top of the N+ buffer layer, a doping level of 1.0×10 13 ~1.0×10 14 cm -3 N-type drift region.

[0082] In this embodiment, the low doping concentration N-type drift region 3 can not only achieve good conductivity, but also help control the electric field distribution of the device, optimize the switching characteristics, and improve the performance of the device. Through precise control of the doping process and subsequent quality inspection, it can be ensured that the reliability of the entire manufacturing process and the performance of the device meet the design requirements.

[0083] Optionally, the thickness of the N-type drift region 3 is 10-100 μm.

[0084] In one embodiment, based on the above embodiment, the doping level is 1.0×10 13 ~1.0×10 14 cm -3 After the step of forming the N-type drift region, it also includes:

[0085] The doping level is 1.0×10 16 ~1.0×10 17 cm -3 P-type ions are implanted to prepare the P+ base region.

[0086] In this embodiment, the higher doping concentration ensures that the P+ base region 4 has a good hole concentration, thereby improving the conductivity of the P+ base region 4 and the overall performance of the device.

[0087] Optionally, the thickness of the P+ base region 4 is 0.8-1.0 μm.

[0088] In one embodiment, based on the above embodiment, the doping level of 1.0×10 16 ~1.0×10 17 cm -3 After the step of implanting P-type ions to prepare a P+ base region, the method further comprises:

[0089] The doping level is 1.0×10 19 ~1.0×10 20 cm -3 N-type ion implantation is performed to prepare an N+ source.

[0090] In this embodiment, the high doping concentration can effectively improve the conductivity of the source and reduce the contact resistance.

[0091] Optionally, the thickness of the N+ source 5 is 0.15-0.3 μm.

[0092] In one embodiment, based on the above embodiment, the doping level of the P+ base region is 1.0×10 19 ~1.0×10 20 cm -3 After the step of N-type ion implantation and preparation of the N+ source, the method further includes:

[0093] After the middle part of the N+ source is protected by an oxide mask, a doping level of 1.0×10 19 ~1.0×10 20 cm -3 P-type ions are implanted to form two P+ sources on the left and right.

[0094] In this embodiment, the doping concentration of the P+ source 6 is controlled at 1.0×10 19 ~1.0×10 20 cm -3 to ensure a higher hole concentration, thereby improving the conductivity of the P+ source 6.

[0095] Optionally, the thickness of the P+ source 6 is 0.15-0.3 μm.

[0096] In this way, through precise control of doping concentration and implantation depth, high conductivity and appropriate thickness of the P+ source 6 are ensured, laying a solid foundation for subsequent device processing.

[0097] In one embodiment, based on the above embodiment, the doping level of the P-type gate is 2.0×10 16 ~2.0×10 17 cm -3 ;

[0098] And / or, the doping level of the N-type gate is 2.0×10 16 ~2.0×10 17 cm -3 .

[0099] In this embodiment, the doping level of the P-type gate 7 is 2.0×10 16~2.0×10 17 cm -3 The doping concentration between 100 and 100 is a medium doping concentration. This concentration is neither too low to cause insufficient channel modulation capability nor too high to cause short channel effect or increased leakage current. A moderate doping concentration helps to enhance the control of the P-type gate 7 over carriers, thereby improving the switching characteristics and threshold voltage stability of the device.

[0100] The doping level of the N-type gate 11 within this range can effectively improve the conductivity of the N-type gate 11, thereby reducing the resistance of the gate, reducing signal delay, and improving the high-frequency performance of the device.

[0101] In one embodiment, based on the above embodiment, the width of the P-type gate is 2.5-3.5 μm and the depth is 0.5-1.5 μm;

[0102] And / or, the N-type gate has a width of 1.5-2.5 μm and a depth of 5-7 μm.

[0103] In this embodiment, the width of the P-type gate 7 is in the range of 2.5-3.5 μm, which can enhance the electric field modulation capability of the trench, help form a more uniform electric field in the trench, and improve the on-performance and off-performance of the device.

[0104] The depth of the N-type gate 11 is 5-7 μm, which can increase the penetration depth of carriers and make the trench conduction characteristics more significant.

[0105] In addition, the present application also proposes a trench gate MOSFET, which is manufactured using the manufacturing method of the trench gate MOSFET described in the above embodiment.

[0106] Since the trench gate MOSFET adopts all the technical solutions of all the above embodiments, it has at least all the technical effects brought by the technical solutions of the above embodiments, which will not be described one by one here.

[0107] In summary, the present invention provides a method for manufacturing a trench gate MOSFET and a trench gate MOSFET. When manufacturing the trench gate MOSFET, a front heterojunction structure formed by a P-type gate and an N-type drift region can reduce the corresponding JFET resistance, thereby reducing the on-resistance of the device. When the body diode of the trench gate MOSFET is turned on, holes are more likely to flow away from the back heterojunction structure formed by the N-type gate and the N-type drift region, thereby reducing its reverse recovery time, effectively improving the reverse recovery characteristics of the MOSFET body diode, and improving the overall electrical performance of the device.

[0108] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0109] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for manufacturing a trench gate MOSFET, characterized in that: include: A substrate, a buffer layer, an N-type drift region, a P+ base region and an N+ source are formed in sequence from bottom to top, and a P+ source is formed on the left and right sides of the N+ source, and the P+ source and the N+ source are arranged together above the P+ base region to form a P-type contact to enhance the inflow of carriers; Penetrating the middle of the N+ source and the P+ base region, and hollowing out the middle of the upper layer of the N-type drift region to form a trench region; forming a P-type gate at the bottom of the trench region; After an oxide layer is deposited on the P-type gate, an oxide layer is continuously grown in the trench region to form an oxide layer groove; forming a trench gate in the oxide layer recess; forming a source metal layer on the N+ source and the P+ source; Two N-type gates are formed that penetrate the substrate and the buffer layer and are embedded in the N-type drift region from below, and the N-type gate and the N-type drift region form a back heterojunction structure, and the P-type gate and the N-type drift region form a front heterojunction structure; wherein the front heterojunction structure is used to reduce the JFET resistance, and the back heterojunction structure is used to flow away holes; A drain metal layer is formed below the substrate.

2. The method for manufacturing a trench gate MOSFET according to claim 1, wherein: The method for manufacturing the trench gate MOSFET further includes: In the process of forming the substrate, an N+ substrate with a doping level of 1.0×1019~1.0×1020cm-3 is produced.

3. The method for manufacturing a trench gate MOSFET according to claim 2, wherein: In the process of forming the substrate, after the step of preparing an N+ substrate with a doping level of 1.0×1019 to 1.0×1020 cm-3, the method further includes: On top of the substrate, an N+ buffer layer with a doping level of 1.0×1016~1.0×1017cm-3 is produced.

4. The method for manufacturing a trench gate MOSFET according to claim 3, wherein: After the step of forming an N+ buffer layer with a doping level of 1.0×1016 to 1.0×1017 cm-3 on the substrate, the method further includes: On top of the N+ buffer layer, an N-type drift region with a doping level of 1.0×1013~1.0×1014cm-3 is produced.

5. The method for manufacturing a trench gate MOSFET according to claim 4, wherein: After the step of forming an N-type drift region with a doping level of 1.0×1013-1.0×1014cm-3 on the N+ buffer layer, the method further includes: A P+ base region is prepared by implanting P-type ions with a doping level of 1.0×1016~1.0×1017cm-3 above the N-type drift region.

6. The method for manufacturing a trench gate MOSFET according to claim 5, wherein: After the step of preparing a P+ base region by implanting P-type ions with a doping level of 1.0×1016 to 1.0×1017 cm-3 above the N-type drift region, the method further includes: N+ source is prepared by N-type ion implantation with a doping level of 1.0×1019~1.0×1020cm-3 above the P+ base region.

7. The method for manufacturing a trench gate MOSFET according to claim 6, wherein: After the step of preparing an N+ source electrode by N-type ion implantation with a doping level of 1.0×1019 to 1.0×1020 cm-3 above the P+ base region, the method further includes: After protecting the middle part of the N+ source with an oxide mask, P-type ion implantation with a doping level of 1.0×1019~1.0×1020cm-3 is used on the left and right sides of the N+ source to form two left and right P+ sources.

8. The method for manufacturing a trench gate MOSFET according to any one of claims 1 to 7, characterized in that: The doping level of the P-type gate is 2.0×1016~2.0×1017cm-3; And / or, the doping level of the N-type gate is 2.0×1016~2.0×1017cm-3.

9. The method for manufacturing a trench gate MOSFET according to claim 1, wherein: The width of the P-type gate is 2.5-3.5 μm and the depth is 0.5-1.5 μm; And / or, the N-type gate has a width of 1.5-2.5 μm and a depth of 5-7 μm.

10. A trench gate MOSFET, characterized in that: The trench gate MOSFET is manufactured by using the method for manufacturing the trench gate MOSFET according to any one of claims 1 to 9.

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