Semiconductor packaging structure

Abstract

The invention provides a semiconductor packaging structure, which comprises a packaging substrate and a plurality of crystal grains, the plurality of crystal grains are formed on the surface of the packaging substrate, and the surface, close to the packaging substrate, of each crystal grain is provided with a plurality of power supply salient points and a plurality of signal salient points. The semiconductor packaging structure further comprises at least one group of interconnection wires formed in the packaging substrate, and part of the signal salient points of the plurality of signal salient points of the two adjacent crystal grains are electrically connected through the corresponding group of interconnection wires. The current transmitted by each signal salient point is greater than the current transmitted by any one of the plurality of power supply salient points, and the radial size of each power supply salient point is greater than the radial size of any one of the plurality of signal salient points. The structure can ensure the interconnection reliability between different crystal grains and reduce the alignment difficulty in the crystal grain packaging process while adapting to the packaging requirement of a high-computing-power chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] After the grain preparation is completed, a plurality of bumps will be formed on the surface of the grain, which are used to mount the plurality of bumps on the packaging substrate by flip-chip soldering, and then the packaging substrate is connected to the printed circuit board to complete the grain packaging.

[0003] When the bump density on the surface of the grain is relatively high, the above packaging process is suitable for high-computing-power chip packaging, but it is prone to alignment difficulties and interconnection failure problems. Summary of the invention

[0004] In response to the above problems, the present application provides a semiconductor packaging structure to meet the packaging requirements of high-computing power chips while ensuring the reliability of interconnection between different grains and reducing the difficulty of alignment during the grain packaging process.

[0005] In order to achieve the above-mentioned object, the present application provides a semiconductor packaging structure, including a packaging substrate and a plurality of crystal grains, wherein the plurality of crystal grains are formed on the surface of the packaging substrate, and each crystal grain has a plurality of power bumps and a plurality of signal bumps on the surface close to the packaging substrate;

[0006] The semiconductor package structure further comprises at least one group of interconnection wires formed in the package substrate, and some of the multiple signal bumps of two adjacent crystal grains are electrically connected through the corresponding group of interconnection wires.

[0007] The current transmitted by each signal bump is greater than the current transmitted by any one of the multiple power bumps, and the radial dimension of each power bump is greater than the radial dimension of any one of the multiple signal bumps.

[0008] In the case of adopting the above technical solution, some of the multiple signal bumps possessed by two adjacent crystal grains are electrically connected through the corresponding group interconnection wiring. In addition, since the radial dimension of each power bump is larger than the radial dimension of any one of the multiple signal bumps. In this case, the current carrying capacity of each power bump is larger than the current carrying capacity of any one of the multiple signal bumps. Therefore, when the current transmitted by each power bump is larger than the current transmitted by any one of the multiple signal bumps, if the power is supplied to the crystal grain through the power bump possessed by the crystal grain, the power bump possessed by the crystal grain can withstand a larger power current, thereby reducing the possibility of the power bump being broken down. In this case, when some of the multiple signal bumps possessed by two adjacent crystal grains are electrically connected through the corresponding group interconnection wiring, the problem of interconnection failure between different crystal grains is not likely to occur, thereby ensuring the effectiveness of the interconnection between different crystal grains and improving the chip test yield.

[0009] Moreover, since the radial dimension of each power bump is larger than the radial dimension of any one of the plurality of signal bumps, it is relatively easy to align the power bump with a larger radial dimension with the pad on the package substrate. In the process of aligning the bumps of the grain with the pad on the package substrate, after the power bump with a larger radial dimension is aligned with a part of the pad on the package substrate, the signal bump with a smaller radial dimension can be automatically aligned with another part of the pad on the package substrate. Therefore, the grain can align with a part of the pad on the package substrate using the power bump with a relatively large radial dimension, thereby reducing the overall alignment difficulty of the grain and the package substrate, reducing alignment deviation, and thus improving product yield.

[0010] In a possible implementation, there is a gap between two adjacent grains, the plurality of signal bumps include a plurality of first signal bumps close to the gap, and the plurality of first signal bumps of the two adjacent grains are electrically connected through a corresponding group of interconnection traces. Since the plurality of first signal bumps of each grain are close to the gap between the two adjacent grains, the distance between the plurality of first signal bumps of the two adjacent grains is relatively short. Therefore, when the plurality of first signal bumps of the two adjacent grains are electrically connected through the corresponding group of interconnection traces, the interconnection path between the two adjacent grains can be shortened, thereby effectively improving the signal transmission loss between the two adjacent grains.

[0011] In a possible implementation manner, the plurality of power bumps and the plurality of first signal bumps are distributed along an extension direction from the center of the die to the edge of the die.

[0012] In a possible implementation, the plurality of first signal bumps are distributed along a circumferential direction of the plurality of power bumps.

[0013] In a possible implementation, the surface of the die close to the package substrate has a first area and a second area surrounding the first area, and the plurality of signal bumps also include a plurality of second signal bumps. The plurality of power bumps and the plurality of second signal bumps are both located in the first area, and the plurality of first signal bumps are located in the second area.

[0014] In one possible implementation, the radial dimension of each power bump differs from the radial dimension of any one of the multiple signal bumps by more than a preset difference; wherein the radial dimensions of each of the multiple signal bumps are the same; or, the radial dimension of the signal bump is positively correlated with the current transmitted by the signal bump.

[0015] When the radial dimensions of each of the multiple signal bumps are the same, the die has more small-sized signal bumps among the various bumps, thereby increasing the bump density of the die and making the chip computing power applicable to the semiconductor packaging structure higher.

[0016] When the radial size of the signal bump is positively correlated with the current transmitted by the signal bump, the higher the current transmitted by the signal bump, the stronger the current carrying capacity of the signal bump. Based on this, the interconnection reliability between different dies of the semiconductor packaging device is higher.

[0017] In one possible implementation, each die has a plurality of power pads and a plurality of signal pads on a surface close to the packaging substrate, a radial dimension of each signal pad is smaller than a radial dimension of any one of the plurality of power pads, each power bump is formed on a corresponding power pad, and each signal bump is formed on a corresponding signal pad.

[0018] In the technical solution disclosed in the present application, each power bump is formed on a corresponding power pad, and each signal bump is formed on a corresponding signal pad. Therefore, the power pad actually also bears the same current transmission function as the corresponding power bump, and the signal pad actually also bears the same current transmission function as the corresponding signal bump. In this case, when the radial dimension of each signal pad is smaller than the radial dimension of any one of the multiple power pads, the current carrying capacity of each power pad is greater than the current carrying capacity of any one of the signal pads. Therefore, when the current transmitted by the power bump is greater than the current transmitted by any one of the multiple signal pads, the power pad is not easily broken down, which can effectively ensure the interconnection reliability of different grains and the chip test yield.

[0019] In one possible implementation, the surface of each grain close to the packaging substrate also has a protective layer covering multiple power pads and multiple signal pads, the protective layer has multiple first through holes and multiple second through holes, the first through holes, the power pads and the power bumps correspond to each other, and the second through holes, the signal pads and the signal bumps correspond to each other.

[0020] The aperture of each first through hole is larger than the aperture of any one of the plurality of second through holes, each power bump contacts the corresponding power pad through the corresponding first through hole, and each signal bump contacts the corresponding signal pad through the corresponding second through hole.

[0021] In the technical solution disclosed in the present application, each power bump contacts the corresponding power pad through the corresponding first through hole, and each signal bump contacts the corresponding signal pad through the corresponding second through hole, and the aperture of each first through hole is larger than the aperture of any one of the plurality of second through holes, so that each power bump can contact the corresponding power pad with a relatively large contact surface, thereby ensuring that a large power current can be stably transmitted between the power bump and the corresponding power pad. At the same time, the contact between the signal bump and the corresponding signal pad can also be achieved with a second through hole of a smaller size, so as to increase the through hole density (first through hole and second through hole) opened by the protective layer, increase the density of the signal bump on the grain, and make the chip computing power applicable to the semiconductor packaging structure higher.

[0022] In a possible implementation, the top surface of each power bump and the top surface of each signal bump are in the same plane, and each power bump and each signal bump include a conductive structure and a solder cap layer. The thickness of the conductive structure included in each power bump is less than the thickness of the conductive structure included in each signal bump, and the thickness of the solder cap layer included in each power bump is greater than the thickness of the solder cap layer of each signal bump.

[0023] In the technical solution disclosed in the present application, the radial dimension of each power bump is greater than the radial dimension of any one of the multiple signal bumps, so that when preparing the signal bump on the surface of the grain, less solder material is needed to cover the conductive structure, and then a solder cap layer is formed by a reflow process, while when preparing the power bump on the surface of the grain, more solder material is needed to cover the conductive structure, and then a solder cap layer is formed by a reflow process, so that the probability of cold solder joints is relatively low. However, since the top surface of each power bump and the top surface of each signal bump are in the same plane, when a large amount of solder material is used when preparing the power bump on the surface of the grain, the thickness of the solder cap layer included in each power bump is greater than the thickness of the solder cap layer of each signal bump, and the thickness of the conductive structure included in each power bump is less than the thickness of the conductive structure included in each signal bump.

[0024] It can be seen that the technical solution disclosed in the present application can control the thickness of the solder cap layer contained in the power bump to be greater than the thickness of the solder cap layer contained in the signal bump, so that the solder cap layer contained in the power bump can be in good contact with the underlying metal conductive layer, thereby reducing defects caused by cold soldering. At the same time, by making the thickness of the conductive structure included in each power bump smaller than the thickness of the conductive structure included in each signal bump, it is ensured that the top surface of each power bump and the top surface of each signal bump are in the same plane, so that the power bump and the signal bump included in the grain can stably contact with the packaging substrate.

[0025] In a possible implementation, the conductive structure includes a plurality of stacked conductive layers, and the thickness of each conductive layer in each power bump is less than the thickness of the corresponding conductive layer in any one of the plurality of signal bumps. Here, the difference in thickness of the solder cap layer contained in the power bump and the solder cap layer contained in the signal bump can be transferred to the thickness difference of each conductive layer, so that the structure of the signal bump and the power bump meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 A basic structural schematic diagram of a semiconductor packaging structure disclosed in an embodiment of the present application is shown;

[0028] Figure 2 Another basic structural schematic diagram of the semiconductor packaging structure disclosed in the embodiment of the present application is shown;

[0029] Figure 3A A schematic diagram of convex point distribution disclosed in an embodiment of the present application is shown;

[0030] Figure 3B Another schematic diagram of convex point distribution disclosed in an embodiment of the present application is shown;

[0031] Figure 4 A schematic diagram of the structure of the crystal grain disclosed in the embodiment of the present application is shown;

[0032] Figure 5A to Figure 5H A schematic diagram of the process of preparing the grain bumps disclosed in the embodiments of the present application at different stages is shown. DETAILED DESCRIPTION

[0033] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0034] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0035] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0037] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0038] With the rapid development of artificial intelligence and 5G technology, the demand for high-computing power chips continues to rise. Therefore, in the chip packaging process, it is necessary to reduce the radial size of the grain bumps to achieve high density of the grains, thereby improving the interconnection density between different grains in the multi-chip module (MCM) packaging format.

[0039] For the grain bumps, they can be divided into power bumps and signal bumps according to the type of transmission signal. The inventor found that the power current flowing through the power bumps is relatively large, while the signal current flowing through the signal bumps is relatively small. However, after the radial size of the grain bumps is reduced, the power bumps may not be able to withstand the large power current, resulting in the breakdown of the power bumps, thereby causing the interconnection failure between the grains, seriously affecting the test yield of the chip. Moreover, after the radial size of the grain bumps is reduced, the alignment tolerance allowed between the grain bumps and the packaging substrate becomes smaller, resulting in the problem of difficult alignment of the solder joints between the grain bumps and the packaging substrate. If the alignment deviation between the grain bumps and the packaging substrate is large, solder joint failure problems will occur in the subsequent high-temperature support or reliability verification stage, seriously reducing the product yield.

[0040] In order to solve the above problems, an embodiment of the present application provides a semiconductor packaging structure to meet the packaging requirements of high-computing power chips while ensuring the interconnection reliability between different grains and reducing the difficulty of alignment during the grain packaging process.

[0041] Figure 1 A basic structural diagram of a semiconductor packaging structure disclosed in an embodiment of the present application is shown. Figure 2Another basic structural diagram of the semiconductor packaging structure disclosed in the embodiment of the present application is shown. Figure 1 and Figure 2 As shown, the semiconductor package structure 100 of the embodiment of the present application may include: a package substrate 101 and a plurality of dies 102. It should be understood that Figure 1 The number of the crystal grains 102 in the figure is three, but in practice it may be two, or more than three.

[0042] like Figure 1 and Figure 2 As shown, the package substrate 101 can be formed on a printed circuit board ( Figure 1 (not shown). Here, the package substrate 101 can be connected to the printed circuit board through a ball grid array BGA. A plurality of crystal grains 102 are formed on the surface of the package substrate 101, and the surface of the package substrate 101 here can be the surface of the package substrate 101 away from the printed circuit board. Each crystal grain 102 has a plurality of crystal grain 102 bumps on the surface close to the package substrate 101, which are a plurality of power bumps 102a and a plurality of signal bumps 102b. At this time, the plurality of power bumps 102a and the plurality of signal bumps 102b of the package substrate 101 can be connected to the package substrate 101.

[0043] In practical applications, such as Figure 1 and Figure 2 As shown, the above-mentioned packaging substrate 101 has a first surface and a second surface relative to each other. The first surface has a large number of pads for one-to-one welding with the solder balls included in the ball grid array BGA, and the second surface also has a large number of pads for one-to-one welding with the power bumps 102a and signal bumps 102b of each grain 102.

[0044] like Figure 1 and Figure 2 As shown, the semiconductor package structure 100 disclosed in the embodiment of the present application further includes at least one group of interconnection traces 103 formed in the package substrate 101, and some of the signal bumps 102b of the plurality of signal bumps 102b of two adjacent dies 102 are electrically connected through the corresponding group of interconnection traces 103. In this case, the power supply current can be sequentially conducted to the dies 102 through the package substrate 101 and the power supply bumps 102a, and the signal current (such as high-speed signal current) of the two adjacent dies 102 can be transmitted through the signal bumps 102b and the interconnection traces 103 in the two adjacent dies 102 connected to the corresponding group of interconnection traces 103.

[0045] For example, Figure 1 and Figure 2As shown, signal bumps 102 b and power bumps 102 a may be formed on a wafer first, and then the wafer may be cut into crystal grains 102 . Then, the signal bumps 102 b and power bumps 102 a of the crystal grains 102 may be welded to a packaging substrate 101 using a flip-chip process.

[0046] For example, Figure 1 and Figure 2 As shown, the semiconductor packaging structure 100 disclosed in the embodiment of the present application may further include a protective cover 104 , which may be disposed on (eg bonded to) the packaging substrate 101 , and a plurality of crystal grains 102 may be located in a space enclosed by the protective cover 104 and the packaging substrate 101 .

[0047] For example, Figure 1 and Figure 2 As shown, the protective cover 104 may be a heat-conductive cover such as a metal cover, and the inner side of the protective cover 104 is adhered to the surface of the die 102 away from the package substrate 101 through the thermal conductive adhesive A, so that the heat generated by the die 102 can be conducted to the protective cover 104 through the thermal conductive adhesive A, and then dissipated through the protective cover 104. For another example, a filling adhesive B may be formed between the package substrate 101 and the surface of the die 102 close to the package substrate 101 to reduce the possibility of the die 102 being offset.

[0048] like Figure 1 and Figure 2 As shown, considering that the current transmitted by each signal bump 102b is greater than the current transmitted by any one of the multiple power bumps 102a, for example, the power current of the DDR memory can reach 2A, while the PCIE signal current and the IO signal current can be lower than 0.001A, generally at the mA level, therefore, the radial dimension of each power bump 102a can be set to be greater than the radial dimension of any one of the multiple signal bumps 102b. In this case, the current carrying capacity of each power bump 102a is greater than the current carrying capacity of any one of the multiple signal bumps 102b, therefore, when the current transmitted by each power bump 102a is greater than the current transmitted by any one of the multiple signal bumps 102b, if the power bump 102a of the die 102 is used to supply power to the die 102, the power bump 102a of the die 102 can withstand a larger power current, reducing the possibility of the power bump 102a being broken down. When some of the signal bumps 102b of the plurality of signal bumps 102b of two adjacent dies 102 are electrically connected through a corresponding group of interconnection traces 103, interconnection failure between different dies 102 is unlikely to occur, thereby ensuring the effectiveness of interconnection between different dies 102 and improving chip test yield.

[0049] Moreover, if Figure 1 and Figure 2As shown, since the radial dimension of each power bump 102a is larger than the radial dimension of any one of the plurality of signal bumps 102b, it is relatively easy to align the power bump 102a with a larger radial dimension with the pad on the package substrate 101. In the process of aligning the bumps of the die 102 with the pads on the package substrate 101, after the power bump 102a with a larger radial dimension is aligned with a part of the pads on the package substrate 101, the signal bump 102b with a smaller radial dimension can be automatically aligned with another part of the pads on the package substrate 101. Therefore, the die 102 can align with a part of the pads on the package substrate 101 by using the power bump 102a with a relatively large radial dimension, thereby reducing the overall alignment difficulty of the die 102 with the package substrate 101, reducing the alignment deviation, and thus improving the product yield.

[0050] For example, when the radial size of the signal bump increases, the alignment tolerance allowed in the flip-chip process is larger, which is helpful in solving problems such as solder joint failure caused by warpage changes caused by subsequent high-temperature processes or reliability processes of the chip. Therefore, whether from the perspective of electrical performance or process, increasing the radial size of the signal bump can help improve electrical and process stability.

[0051] It should be noted that if Figure 2 As shown, in a high interconnection density scenario, the above-mentioned packaging substrate 101 may include a first substrate 1011 and a second substrate 1012. The first substrate 1011 may be connected to a printed circuit board through a ball grid array BGA, and the second substrate 1012 may be arranged on a surface of the first substrate 1011 away from the packaging substrate 101 through solder balls 106, and a plurality of grains 102 are arranged on a surface of the second substrate 1012 away from the first substrate 1011.

[0052] For example, Figure 2 As shown, the first substrate 1011 can be a multi-layer substrate. For example, the first substrate 1011 can include a core board and a laminate formed on both sides of the core board. The second substrate 1012 can be an adapter board used as an intermediate board, and the adapter board can be an organic redistribution layer (RDL) adapter board or an inorganic silicon adapter board. The interconnection wiring 103 is arranged in the second substrate 1012. In addition, the semiconductor packaging structure 100 disclosed in the embodiment of the present application can also be provided with a filling glue B between the second substrate 1012 and the plurality of grains 102, and the plurality of grains 102 are encapsulated by the encapsulation material C to ensure the stability of the grains. At the same time, the encapsulation material C can also be connected to the inner side of the protective cover 104 through the thermal conductive glue A, so as to use the thermal conductive glue A to transfer the heat conducted by the encapsulation material C (the heat released by the grains) to the protective cover 104, and then dissipate the heat through the protective cover 104.

[0053] In one possible implementation, Figure 1 and Figure 2 As shown, the difference between the radial dimension of each power bump 102a and the radial dimension of any one of the plurality of signal bumps 102b is greater than a preset difference. Under such a difference, the current carrying capacity of the power bump 102a is effectively improved relative to the current carrying capacity of the signal bump 102b, thereby reducing the possibility of the power bump 102a being broken down.

[0054] In practical applications, such as Figure 1 and Figure 2 As shown, the power bump 102a and the signal bump 102b disclosed in the embodiment of the present application can have the same shape, which can be a spherical bump or a columnar bump. For example, in order to increase the bump density, it can be designed as a columnar bump according to the relevant process, and its diameter can be in the range of 20μm to 30μm, and the spacing between the signal bump 102b and the signal bump 102b is in the range of 30μm-40μm. The power bump 102a can be designed as a large-sized columnar bump according to the relevant process, and its diameter can be in the range of 70μm to 100μm.

[0055] For example, Figure 1 and Figure 2 As shown, when the radial dimensions of each signal bump 102b in the plurality of signal bumps 102b are the same. In this case, the die 102 has a large number of small-sized signal bumps 102b among the various bumps, thereby increasing the bump density of the die 102, so that the chip computing power applicable to the semiconductor package structure 100 is higher. For example, the diameter of each signal bump 102b can be set to 25μm, 20μm or 30μm, and the diameter of each power bump 102a can be set to 70μm, 100μm or 75μm.

[0056] For example, Figure 1 and Figure 2 As shown, when the radial dimension of the signal bump 102b is positively correlated with the current transmitted by the signal bump 102b, the higher the current transmitted by the signal bump 102b, the stronger the current carrying capacity of the signal bump 102b. Based on this, the interconnection reliability between different dies 102 included in the semiconductor packaging structure is higher. For example, for a signal bump 102b with a large transmission current, its diameter can be 30μm, while for a signal bump 102b with a small transmission current, its diameter can be 25μm or even 20μm.

[0057] For example, the thermal conductivity of the ball bump is 55-60W / m·k, and the resistivity is 0.12μΩ·m-0.14μΩ·m, while the thermal conductivity of the columnar bump is about 300W / m·k, and the resistivity is about 0.025μΩ·m. Compared with the ball bump, the columnar bump has better heat dissipation and electrical conductivity, and can better conduct current.

[0058] In a possible implementation, when the interconnection path between two adjacent grains is long, the signal transmission loss between the two adjacent grains is high, such as Figure 1 and Figure 2 As shown, in the technical solution disclosed in the embodiment of the present application, there is a gap between two adjacent grains 102, the multiple signal bumps 102b include multiple first signal bumps close to the gap, and the multiple first signal bumps of the two adjacent grains 102 are electrically connected through the corresponding group of interconnection wirings 103.

[0059] from Figure 1 and Figure 2 It can be seen that the multiple first signal bumps of each grain 102 are close to the gap between two adjacent grains 102, so that the distance between the multiple first signal bumps of two adjacent grains 102 is relatively short. Therefore, when the multiple first signal bumps of two adjacent grains 102 are electrically connected through the corresponding group of interconnection traces 103, the interconnection path between the two adjacent grains 102 can be shortened, thereby effectively improving the signal transmission loss between the two adjacent grains 102.

[0060] In practical applications, such as Figure 1 and Figure 2 As shown, the plurality of power bumps 102a and the plurality of first signal bumps are distributed along the extension direction from the center of the die 102 to the edge of the die 102. Since the power bump 102a mainly transmits the power current transmitted by the package substrate 101 to the corresponding die 102, when the plurality of power bumps 102a and the plurality of first signal bumps are distributed along the extension direction from the center of the die 102 to the edge of the die 102, not only can the interconnection path between two adjacent die 102 be shortened, but also the transmission path of the power current can be shortened, thereby effectively reducing the transmission loss of the power current.

[0061] Illustratively, in the technical solution disclosed in the present application, the plurality of first signal bumps may be distributed along the circumferential direction of the plurality of power bumps, or the plurality of first signal bumps may be distributed on one side of the plurality of power bumps, and the specific selection may be made based on actual conditions.

[0062] For example, Figure 1 and Figure 2 The three dies 102 in the embodiment are named as the first die, the second die and the third die in the order from left to right, and the plurality of first signal bumps of the second die can be distributed along the circumferential direction of the plurality of power bumps 102a. In this case, the first die and the third die located around the second die can be interconnected with the second die via a shorter interconnection path.

[0063] Considering that the first die and the third die are interconnected with the second die respectively, the multiple first signal bumps of the first die and the second die can be distributed along the circumferential direction of the multiple power bumps, or can be distributed along a certain fixed extension direction.

[0064] For example, the multiple power bumps and the multiple first signal bumps of the first die are distributed along the extension direction from the center of the first die to the edge of the first die, and the extension direction can be directed from the first die to the second die. In this case, the interconnection path between the multiple first signal bumps of the first die and the multiple first signal bumps of the second die can be shortened as much as possible.

[0065] The plurality of power bumps and the plurality of first signal bumps of the third die are distributed along the extension direction from the center of the third die to the edge of the second die. The extension direction may be directed from the third die to the second die. In this case, the interconnection path between the plurality of first signal bumps of the third die and the plurality of first signal bumps of the second die may be shortened as much as possible.

[0066] In an optional manner, in the technical solution disclosed in the embodiment of the present application, the plurality of signal bumps include not only a plurality of first signal bumps, but also a plurality of second signal bumps. Here, the plurality of first signal bumps can be divided into first signal bumps and second signal bumps according to whether they are connected to the corresponding group of interconnection traces.

[0067] For example, Figure 1 and Figure 2 As shown, a portion of the signal bumps on the periphery of the power bump 102a of the second die are connected to the signal bumps of the first die through the corresponding interconnection routing 103. Here, the signal bumps in the second die connected to the corresponding group of interconnection routings 103 can be defined as first signal bumps, and the signal bumps not connected to the corresponding group of interconnection routings 103 are defined as second signal bumps. Therefore, the multiple signal bumps of the second die include both the first signal bumps and the second signal bumps.

[0068] Exemplarily, the signal bumps of the first die and the signal bumps of the third die are all connected to corresponding groups of interconnection traces, so both the first die and the second die have the first signal bumps but do not have the second signal bumps.

[0069] Exemplarily, the surface of the die close to the package substrate disclosed in the embodiment of the present application has a first area and a second area surrounding the first area, a plurality of power bumps are located in the first area, and a plurality of first signal bumps are located in the second area.

[0070] Figure 3A A schematic diagram of the distribution of convex points disclosed in the embodiment of the present application is shown. Figure 3AAs shown, the number of power bumps VDD on the surface of the die 300 close to the packaging substrate may be 5, and the 5 power bumps VDD are arranged in the first area 300A. The number of first signal bumps Signal-1 may be 12, and the 12 first signal bumps Signal-1 are arranged in the second area 300B, and the 12 first signal bumps Signal-1 surround the first area along the extension direction of the second area 300B.

[0071] When the die has a plurality of second signal bumps, the plurality of second signal bumps are located in the first region. Since the first signal bump Signal-1 is located in the second region, and the second region surrounds the periphery of the first region, the first signal bump is closer to the edge of the die than the second signal bump, thereby ensuring that the interconnection path between the die is relatively short.

[0072] Figure 3B Another schematic diagram of the distribution of convex points disclosed in the embodiment of the present application is shown. Figure 3B As shown, the number of power bumps VDD on the surface of the die 300 close to the packaging substrate may be 5, and the 5 power bumps VDD are arranged in the first area 300A. The number of signal bumps is 36, specifically including 20 first signal bumps Signal-1 and 16 second signal bumps Signal-2. The 20 first signal bumps Signal-1 are arranged in the second area 300B, and the 20 first signal bumps Signal-1 surround the first area 300A along the extension direction of the second area 300B, and the 16 second signal bumps Signal-2 are arranged in the first area 300A, and the 16 second signal bumps Signal-2 surround the 5 power bumps VDD.

[0073] It should be noted that if Figure 3A and Figure 3B As shown, the surface of the grain 300 close to the packaging substrate not only has power bumps VDD and signal bumps (first signal bump Signal-1 and second signal bump Signal-2), but also has multiple ground bumps VSS through which no signal passes and multiple virtual bumps Dummy. The multiple ground bumps VSS can be located in the first area 300A, and ground bumps VSS are arranged around each power bump VDD. The multiple virtual bumps Dummy can be located in the second area 300B, and the multiple virtual bumps Dummy are arranged at the four corners of the grain 300.

[0074] In a possible implementation, the die bump is substantially formed on the die pad. When the size of the die bump changes, the size of the die pad can be adjusted to accommodate the die bump formed on the die pad.

[0075] Figure 4FIG. 1 shows a schematic diagram of the structure of the crystal grain disclosed in the embodiment of the present application. Figure 4 As shown, the surface of the die 401 close to the package substrate disclosed in the embodiment of the present application has multiple power pads 402A and multiple signal pads 402B, the radial dimension of each signal pad 402B is smaller than the radial dimension of any one of the multiple power pads 402A, each power bump 404A is formed on the corresponding power pad 402A, and each signal bump 404B is formed on the corresponding signal pad 402B. It should be understood that Figure 4 Only one signal bump 404B and one power bump 404A are shown, but in practice the number of power bumps 404A and signal bumps 404B is greater.

[0076] like Figure 4 As shown, when the power bump 404A is formed on the corresponding power pad 402A, and the signal bump 404B is formed on the corresponding signal pad 402B, the power pad 402A actually also assumes the same current transmission function as the corresponding power bump 404A, and the signal pad 402B actually also assumes the same current transmission function as the corresponding signal bump 404B. In this case, when the radial dimension of each signal pad 402B is smaller than the radial dimension of any one of the multiple power pads 402A, the current carrying capacity of each power pad 402A is greater than the current carrying capacity of any one of the multiple signal pads 402B. Therefore, when the current transmitted by each power bump 404A is greater than the current transmitted by any one of the multiple signal pads 402B, the power pad 402A is not easily broken down, which can effectively ensure the interconnection reliability of different grains and the chip test yield.

[0077] In an alternative approach, Figure 4 As shown, each die 400 has a protective layer 403 covering a plurality of power pads 402A and a plurality of signal pads 402B on a surface close to the package substrate, and the protective layer 403 has a plurality of first through holes and a plurality of second through holes. The first through holes, the power pads 402A and the power bumps 404A correspond to each other, and the second through holes, the signal pads 402B and the signal bumps 404B correspond to each other.

[0078] In practical applications, such as Figure 4 As shown, the protection layer 403 may include a passivation layer 4031 and a polyimide layer 4032. The passivation layer 4031 may be formed simultaneously during the process of preparing the die 400, and the polyimide layer 4032 may be formed on the passivation layer 4031. The first through hole and the second through hole may penetrate the passivation layer 4031 and the polyimide layer 4032.

[0079] like Figure 4As shown, when the first through hole, the power pad 402A and the power bump 404A correspond to each other, it can be that the first through hole, the power pad 402A and the power bump 404A correspond to each other in position, and each power bump 404A contacts the corresponding power pad 402A through the corresponding first through hole; when the second through hole, the signal pad 402B and the signal bump 404B correspond to each other, it can be that the second through hole, the signal pad 402B and the signal bump 404B correspond to each other in position, and each signal bump 404B contacts the corresponding signal pad 402B through the corresponding second through hole.

[0080] Exemplarily, in order to ensure that the power bump 404A and the power pad 402A are in contact with each other at the maximum contact area, and the signal bump 404B and the signal pad 402B are in contact with each other at the maximum contact area, the aperture of each first through hole can be set to be larger than the aperture of any one of the plurality of second through holes. For example, the aperture of the first through hole can be equal to the radial dimension of the power pad 402A, or smaller than the radial dimension of the power pad 402A, and the aperture of the second through hole can be equal to the radial dimension of the signal pad 402B, or smaller than the radial dimension of the signal pad 402B.

[0081] like Figure 4 As shown, when the aperture of each first through hole is larger than the aperture of any one of the plurality of second through holes, the power bump 404A can be brought into contact with the corresponding power pad 402A by using the first through hole of larger size, thereby ensuring that a larger power current can be stably transmitted between the power bump 404A and the corresponding power pad 402A. At the same time, the contact between the signal bump 404B and the corresponding signal pad 402B can also be achieved by using the second through hole of smaller size, so as to increase the through hole density (first through hole and second through hole) opened by the protective layer 403, increase the density of the signal bump 404B on the die 400, and make the chip computing power applicable to the semiconductor packaging structure higher.

[0082] For example, Figure 4 As shown, in order to ensure that the power bump 404A and the signal bump 404B can contact the package substrate at the same time, the top surface of each power bump 404A and the top surface of each signal bump 404B are in the same plane, and each power bump 404A includes a first conductive structure 404A1 and a first solder cap layer 404A2. The first conductive structure 404A1 contacts the power pad 402A through a first through hole, and the first solder cap layer 404A2 is formed on the first conductive structure 404A1; each signal bump 404B may include a second conductive structure 404B1 and a second solder cap layer 404B2, the second conductive structure 404B1 contacts the signal pad 402B through a second through hole, and the second solder cap layer 404B2 is formed on the second conductive structure 404B1.

[0083] like Figure 4 As shown, since the radial dimension of each power bump 404A is larger than the radial dimension of any one of the multiple signal bumps 404B, when preparing the signal bump 404B on the surface of the grain 400, less solder material is needed to cover the conductive structure, and then the first solder cap layer 404B2 is formed through the reflow process. When preparing the power bump 404A on the surface of the grain 400, more solder material is needed to cover the conductive structure, and then the second solder cap layer 404A2 is formed through the reflow process, so that the probability of cold solder joints during reflow soldering is relatively low. However, since the top surfaces of each power bump 404A and the top surfaces of each signal bump 404B are on the first plane L1, when the power bump 404A is prepared on the surface of the grain 400 and a large amount of solder material is used, the thickness of the first solder cap layer 404A2 included in each power bump 404A is greater than the thickness of the second solder cap layer 404B2 included in each signal bump 404B, and the thickness of the first conductive structure 404A1 included in each power bump 404A is less than the thickness of the second conductive structure 404B1 included in each signal bump 404B. In this case, the second plane L2 where the upper surface of the second conductive structure 404B1 included in the signal bump 404B is located is higher than the plane where the upper surface of the first conductive structure 404A1 included in the power bump 404A is located, so that the height difference between the first conductive structure 404A1 and the second conductive structure 404B1 is utilized to eliminate the height difference between the first solder cap layer 404A2 and the second solder cap layer 404B2, ensuring that the top surface of each first solder cap layer 404A2 and the top surface of the second solder cap layer 404B2 are in the same plane.

[0084] It can be seen that the technical solution disclosed in the present application can control the thickness of the solder cap layer contained in the power bump 404A to be greater than the thickness of the solder cap layer contained in the signal bump 404B, so that the first solder cap layer 404A2 contained in the power bump 404A can be in good contact with the first conductive structure 404A1 of the lower layer, thereby reducing the defects caused by cold soldering. At the same time, by making the thickness of the first conductive structure 404A1 included in each power bump 404A smaller than the thickness of the second conductive structure 404B1 included in each signal bump 404B, it is ensured that the top surface of each power bump 404A and the top surface of each signal bump 404B are in the same plane, so that the power bump 404A and the signal bump 404B included in the die 400 can stably contact with the packaging substrate.

[0085] Exemplarily, the first conductive structure 404A1 and the second conductive structure 404B1 include a plurality of stacked conductive layers, and the thickness of each conductive layer in each power bump 404A is less than the thickness of the corresponding conductive layer in any one of the plurality of signal bumps 404B. Here, the thickness difference between the first solder cap layer 404A2 contained in the power bump 404A and the second solder cap layer 404B2 contained in the signal bump 404B can be transferred to the thickness difference of each conductive layer, so that the structures of the signal bump 404B and the power bump 404A meet the requirements.

[0086] Considering the different radial sizes of the power bump and the signal bump, a large-sized power bump and a small-sized signal bump can be formed on the surface of the grain in a step-by-step manner. Here, a large-sized power bump can be formed on the surface of the grain first, and then a small-sized signal bump can be formed, or a small-sized signal bump can be formed first, and then a large-sized power bump can be formed. The following takes the example of first forming a small-sized signal bump and then forming a large-sized power bump. Figure 5A to Figure 5H The formation process of the grain bump disclosed in the embodiment of the present application is described.

[0087] like Figure 5A As shown, a crystal grain 501 having a passivation layer 503 is provided, a signal pad 502A and a power pad 502B are located under the passivation layer 503, and the passivation layer 503 is formed with a first passivation layer through hole 503A and a second passivation layer through hole 503B, at least a portion of the signal pad 502A is exposed through the first passivation layer through hole 503A, and at least a portion of the power pad 502B is exposed through the second passivation layer through hole 503B.

[0088] like Figure 5B As shown, polyimide is coated on the surface with the passivation layer 503 to form a polyimide layer 504. Here, the polyimide layer 504 and the passivation layer 503 can constitute a protective layer. The polyimide layer 504 can be a negative photoresist. With the cooperation of the mask, the pattern of the signal through hole and the power through hole can be projected onto the polyimide layer 504 through an optical system, and then the polyimide layer 504 is developed by a developer to open a window on the polyimide layer 504, thereby forming a first polyimide layer through hole 504A and a second polyimide layer through hole 504B, so as to expose the signal pad 502A by using the first polyimide layer through hole 504A, and expose the power pad 502B by using the second polyimide layer through hole 504B.

[0089] It can be seen that Figure 5A and Figure 5B As shown, the first polyimide layer through hole 504A and the first passivation layer through hole 503A may constitute Figure 4The protective layer 403 shown has a second through hole, and the second polyimide layer through hole 504B and the second passivation layer through hole 503B can constitute Figure 4 The protection layer 403 shown has a first through hole.

[0090] like Figure 5C As shown, a seed material layer 505 is formed on the polyimide layer 504 and the exposed power pad 502B and the signal pad 502A by physical vapor deposition. For example, the seed material layer 505 may be a Ti / Cu seed material layer.

[0091] like Figure 5D As shown, a first photoresist layer 506A is formed on the seed material layer 505, and the first photoresist layer 506A has a first photoresist through hole 506A1, so as to expose at least Figure 5B The area where the second polyimide layer through hole 504B is located is shown.

[0092] For example, Figure 5D As shown, a photoresist can be coated on the seed material layer 505, and then soft-baked to evaporate and remove the solvent (10wt% to 20wt%) remaining in the photoresist to relieve stress, and finally cooled to obtain a photoresist material layer. The grains expanded by the soft baking can be released from stress and restored to their original state by cooling. After that, the first photoresist through hole 506A1 can be obtained by exposure and development (refer to the formation process of the first polyimide layer through hole 504A and the second polyimide layer through hole 504B).

[0093] like Figure 5E As shown, a first thick copper layer 507A1, a first thin nickel layer 507A2, a first thin copper layer 507A3 and a first solder layer (SnAg1.8 is usually selected) are electroplated in sequence in the first photoresist through hole 506A1, and the first solder layer is reflowed to obtain a first solder cap layer 507A4. At this time, the first thick copper layer 507A1, the first thin nickel layer 507A2, the first thin copper layer 507A3 and the first solder cap layer 507A4 form a signal bump.

[0094] like Fig. 5F As shown, the first photoresist layer 506A is removed, and then a second photoresist layer 506B is formed on the seed material layer 505. The second photoresist layer 506B has a second photoresist through hole 506B1, so as to expose at least Figure 5B The area where the first polyimide layer through hole 504A is located is shown.

[0095] like Figure 5G As shown, reference Fig. 5F, a second thick copper layer 507B1, a second thin nickel layer 507B2, a second thin copper layer 507B3 and a second solder layer can be electroplated in the second photoresist through hole 506B1, and the second solder layer (SnAg1.8 is usually selected) is reflowed to obtain a second solder cap layer 507B4. At this time, the second thick copper layer 507B1, the second thin nickel layer 507B2, the second thin copper layer 507B3 and the second solder cap layer 507B4 form a power bump. Since the signal bump is protected by the second photoresist layer 506B, the signal bump will not be damaged in the process of forming the power bump.

[0096] like Figure 5H As shown, the second photoresist layer 506B is removed, and the seed material layer 505 is etched, thereby obtaining a first seed layer 505A located in the first through hole and a second seed layer 505B located in the second through hole. Figure 5A to Figure 5H By performing the operations described above, the signal bump 507A and the power bump 507B formed on the die 501 can be obtained.

[0097] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0098] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor packaging structure, characterized in that: It comprises a packaging substrate and a plurality of crystal grains, wherein the plurality of crystal grains are formed on the surface of the packaging substrate, and each crystal grain has a plurality of power bumps and a plurality of signal bumps on the surface close to the packaging substrate; The semiconductor package structure further includes at least one group of interconnection traces formed in the package substrate, and some of the plurality of signal bumps of two adjacent die are electrically connected through the corresponding group of interconnection traces; The current transmitted by each of the power bumps is greater than the current transmitted by any one of the plurality of signal bumps, and the radial dimension of each of the power bumps is greater than the radial dimension of any one of the plurality of signal bumps.

2. The semiconductor package structure according to claim 1, wherein: There is a gap between two adjacent crystal grains, the plurality of signal bumps include a plurality of first signal bumps close to the gap, and the plurality of first signal bumps of the two adjacent crystal grains are electrically connected through a corresponding group of interconnection wirings.

3. The semiconductor package structure according to claim 2, characterized in that: The plurality of power bumps and the plurality of first signal bumps are distributed along an extension direction from a center of the die to an edge of the die.

4. The semiconductor package structure according to claim 2, wherein: The plurality of first signal bumps are distributed along the circumferential direction of the plurality of power bumps.

5. The semiconductor package structure according to claim 2, wherein: The surface of the die close to the packaging substrate has a first area and a second area surrounding the first area, and the plurality of signal bumps further include a plurality of second signal bumps; The plurality of power bumps and the plurality of second signal bumps are both located in the first region, and the plurality of first signal bumps are located in the second region.

6. The semiconductor package structure according to claim 1, wherein: The difference between the radial dimension of each of the power bumps and the radial dimension of any one of the plurality of signal bumps is greater than a preset difference; Wherein, the radial dimensions of each of the plurality of signal bumps are the same; or, the radial dimensions of the signal bumps are positively correlated with the current transmitted by the signal bumps.

7. The semiconductor package structure according to any one of claims 1 to 6, characterized in that: Each of the grains has a plurality of power pads and a plurality of signal pads on a surface close to the packaging substrate, the radial dimension of each of the signal pads is smaller than the radial dimension of any one of the plurality of power pads, each of the power bumps is formed on the corresponding power pad, and each of the signal bumps is formed on the corresponding signal pad.

8. The semiconductor package structure according to claim 7, characterized in that: The surface of each of the crystal grains close to the packaging substrate also has a protective layer covering the multiple power pads and the multiple signal pads, the protective layer has a plurality of first through holes and a plurality of second through holes, the first through holes, the power pads and the power bumps correspond to each other, and the second through holes, the signal pads and the signal bumps correspond to each other; The aperture of each of the first through holes is larger than the aperture of any one of the plurality of second through holes, each of the power bumps contacts the corresponding power pad through the corresponding first through hole, and each of the signal bumps contacts the corresponding signal pad through the corresponding second through hole.

9. The semiconductor package structure according to any one of claims 1 to 6, characterized in that: The top surface of each of the power bumps and the top surface of each of the signal bumps are in the same plane, and each of the power bumps and each of the signal bumps includes a conductive structure and a solder cap layer; The thickness of the conductive structure included in each of the power bumps is smaller than the thickness of the conductive structure included in each of the signal bumps, and the thickness of the solder cap layer included in each of the power bumps is larger than the thickness of the metal conductive layer of each of the signal bumps.

10. The semiconductor package structure according to claim 9, wherein: The conductive structure includes a plurality of stacked conductive layers, and the thickness of each conductive layer in each of the power bumps is smaller than the thickness of the corresponding conductive layer in any one of the plurality of signal bumps.

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