Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the second gate structure is formed on the substrate in the enhanced device region; the base electrode is formed on the substrate of the bipolar device region and extends into the substrate; the passivation layer is formed on the substrate of the depletion type device region, the enhancement type device region and the bipolar device region and covers the second gate structure and the base electrode; the first gate structure is formed on the passivation layer of the depletion type device region, and the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer; the first source electrode metal and the first drain electrode metal are formed on the substrate on the two sides of the first gate structure, the second source electrode metal and the second drain electrode metal are formed on the substrate on the two sides of the second gate structure, and the emitter electrode metal and the collector electrode metal are formed on the substrate on the two sides of the base electrode. According to the technical scheme, integration of a depletion type device, an enhancement type device and a bipolar device is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Due to compatibility issues between GaN HEMT (High Electron Mobility Transistor) power devices and silicon-based driving circuits, it is necessary to develop GaN integrated circuits in order to further reduce parasitic parameters.

[0003] Among them, GaN bipolar devices can achieve high current handling capability, high current gain, and high power density, which are crucial for the realization of oscillators and various amplifiers. At present, although lateral devices based on AlGaN / GaN heterojunctions have been greatly developed, there are few studies on bipolar devices based on AlGaN / GaN lateral structures, which is not conducive to integration with other devices.

[0004] Moreover, for mature silicon-based integrated circuits, low static power consumption and high operating frequency CMOS integrated circuits can be realized based on enhanced NMOS and PMOS devices; however, due to the low activation rate and high device damage under high doping of P-type GaN HEMT devices, enhanced PMOS devices have not been realized. Therefore, at present, direct-coupled integrated circuits are mostly realized based on depletion-mode (D-mode) HEMT devices and enhancement-mode (E-mode) HEMT devices. However, due to the large difference in the structure of depletion-mode HEMT devices and enhancement-mode HEMT devices, the conventional process for realizing enhancement-mode HEMT devices is not compatible with the process of depletion-mode HEMT devices, which is not conducive to integration.

[0005] Therefore, how to integrate depletion-mode devices, enhancement-mode devices and bipolar devices is a problem that needs to be solved urgently. Summary of the invention

[0006] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, so as to realize the integration of a depletion-mode device, an enhancement-mode device and a bipolar device.

[0007] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0008] A substrate, including a depletion device region, an enhancement device region and a bipolar device region;

[0009] A second gate structure is formed on the substrate in the enhancement mode device region;

[0010] A base electrode is formed on the substrate of the bipolar device region and extends into the substrate of the bipolar device region;

[0011] A passivation layer is formed on the substrate in the depletion-mode device region, the enhancement-mode device region and the bipolar device region, and the passivation layer covers the second gate structure and the base;

[0012] A first gate structure is formed on the passivation layer in the depletion-mode device region, wherein the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer;

[0013] A first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base.

[0014] Optionally, the substrate further includes an enhanced power device region, and the semiconductor device further includes:

[0015] A third gate structure is formed on the substrate in the enhanced power device region, and the passivation layer is also formed on the substrate in the enhanced power device region and the third gate structure;

[0016] A third source metal and a third drain metal are formed on the substrate at two sides of the third gate structure.

[0017] Optionally, the first gate structure includes a first metal gate layer, the second gate structure and the third gate structure each include a nitride gate layer and a second metal gate layer from bottom to top; and the base includes a nitride base layer and a metal base layer from bottom to top.

[0018] Optionally, the semiconductor device further includes:

[0019] At least one field plate is formed on the passivation layer in the enhancement mode power device region.

[0020] Optionally, the substrate includes a substrate and a buffer layer, a first nitride layer and a second nitride layer formed on the substrate from bottom to top, the base extends from the substrate to penetrate the second nitride layer and the first nitride layer, and a two-dimensional electron gas is formed between the first nitride layer and the second nitride layer in the bipolar device region outside the base.

[0021] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0022] Providing a substrate, the substrate comprising a depletion type device region, an enhancement type device region and a bipolar device region;

[0023] A second gate structure, a base, a passivation layer and a first gate structure are formed, wherein the second gate structure is formed on the substrate of the enhancement device region; the base is formed on the substrate of the bipolar device region and extends into the substrate of the bipolar device region; the passivation layer is formed on the substrates of the depletion device region, the enhancement device region and the bipolar device region, and the passivation layer covers the second gate structure and the base; the first gate structure is formed on the passivation layer of the depletion device region, and the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer;

[0024] A first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal are formed, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base.

[0025] Optionally, the substrate further includes an enhanced power device region, and the method for manufacturing the semiconductor device further includes:

[0026] forming a third gate structure on the substrate in the enhanced power device region, wherein the passivation layer is also formed on the substrate in the enhanced power device region and the third gate structure;

[0027] A third source metal and a third drain metal are formed on the substrate at two sides of the third gate structure.

[0028] Optionally, the step of forming the second gate structure, the base, the passivation layer, the first gate structure and the third gate structure includes:

[0029] Forming a nitride gate layer and a second metal gate layer stacked on the substrate of the enhancement device region and the enhancement power device region, and forming a nitride base layer and a metal base layer stacked on the substrate of the bipolar device region, wherein the nitride base layer also extends into the substrate of the bipolar device region;

[0030] Forming a passivation layer on the substrate of the depletion-mode device region, the enhancement-mode device region, the bipolar device region and the enhancement-mode power device region, wherein the passivation layer covers the nitride gate layer, the second metal gate layer, the nitride base layer and the metal base layer;

[0031] A first metal gate layer is formed on the passivation layer in the depletion-mode device region, so that the first gate structure includes the first metal gate layer, the second gate structure and the third gate structure both include the nitride gate layer and the second metal gate layer, and the base includes the nitride base layer and the metal base layer.

[0032] Optionally, the step of forming the nitride gate layer, the second metal gate layer, the nitride base layer and the metal base layer comprises:

[0033] forming a third nitride layer on the substrate;

[0034] Performing ion implantation into a portion of the substrate and a portion of the third nitride layer in the bipolar device region to form a doping layer;

[0035] forming a metal layer on the third nitride layer, wherein the metal layer covers the doping layer;

[0036] The metal layer and the third nitride layer are etched to form the stacked nitride gate layer and the second metal gate layer on the substrate of the enhanced device area and the enhanced power device area, and the doped layer is formed into the nitride base layer, and the metal base layer is formed on the nitride base layer.

[0037] Optionally, the method for manufacturing the semiconductor device further includes:

[0038] At least one field plate is formed on the passivation layer in the enhancement mode power device region.

[0039] Optionally, the substrate includes a substrate and a buffer layer, a first nitride layer and a second nitride layer formed on the substrate from bottom to top, the base extends from the substrate to penetrate the second nitride layer and the first nitride layer, and a two-dimensional electron gas is formed between the first nitride layer and the second nitride layer in the bipolar device region outside the base.

[0040] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0041] 1. The semiconductor device of the present invention comprises: a substrate, comprising a depletion-type device region, an enhancement-type device region and a bipolar device region; a second gate structure formed on the substrate in the enhancement-type device region; a base formed on the substrate in the bipolar device region and extending into the substrate in the bipolar device region; a passivation layer formed on the substrate in the depletion-type device region, the enhancement-type device region and the bipolar device region, the passivation layer covering the second gate structure and the base; a first gate structure formed on the passivation layer in the depletion-type device region, the first gate structure formed on the passivation layer in the depletion-type device region, the second gate structure formed on the base in the enhancement-type device region, the second gate structure formed on the base in the bipolar device region, the second gate structure formed on the passivation layer in the depletion-type device region, the second gate structure formed on the base in the enhancement-type device region, the second gate structure formed on the base in the bipolar device region, the second gate structure formed on the passivation layer in the depletion-type device region, the second gate structure formed on the base in the enhancement-type device region, the second gate structure formed on the base in the bipolar device region, the second gate structure formed on the passivation layer in the depletion-type device region, the second gate structure formed on the passivation layer in the bipolar ... bipolar device region, the second gate structure formed on the passivation layer in the bipolar device region, the second gate structure formed on the passivation layer in the bipolar device region, the second gate structure formed on the passivation layer in the depletion-type device region, the second gate structure formed on the passivation layer in the bipolar device region, the second gate The passivation layer between a gate structure and the substrate serves as a gate dielectric layer; a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base, so as to realize the integration of depletion-mode devices, enhancement-mode devices and bipolar devices.

[0042] 2. The manufacturing method of the semiconductor device of the present invention comprises: providing a substrate, the substrate comprising a depletion device region, an enhancement device region and a bipolar device region; forming a second gate structure, a base, a passivation layer and a first gate structure, the second gate structure is formed on the substrate in the enhancement device region; the base is formed on the substrate in the bipolar device region and extends into the substrate in the bipolar device region; the passivation layer is formed on the substrate in the depletion device region, the enhancement device region and the bipolar device region, the passivation layer covers the second gate structure and the base; the first gate structure is formed On the passivation layer in the depletion-mode device region, the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer; a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal are formed, the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base, so that the integration of depletion-mode devices, enhancement-mode devices and bipolar devices is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0044] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0045] Figure 3a to Figure 3h yes Figure 2 A device schematic diagram of a method for manufacturing a semiconductor device is shown.

[0046] Among them, Figure 1 to Figure 3h The reference numerals are described as follows:

[0047] 10-substrate; 101-buffer layer; 102-first nitride layer; 103-second nitride layer; 104-third nitride layer; 105-metal layer; 106-patterned photoresist layer; 11-nitride base layer; 111-doping layer; 12-nitride gate layer; 131-second metal gate layer; 132-first metal base layer; 14-first metal gate layer; 15-passivation layer; 161-first source metal; 162-first drain metal; 163-second source metal; 164-second drain metal; 165-emitter metal; 166-collector metal; 167-third source metal; 168-third drain metal; 17-interlayer dielectric layer; 18-field plate. DETAILED DESCRIPTION

[0048] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below in conjunction with the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0049] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, including a depletion device region, an enhancement device region and a bipolar device region; a second gate structure, formed on the substrate of the enhancement device region; a base, formed on the substrate of the bipolar device region and extending into the substrate of the bipolar device region; a passivation layer, formed on the substrate of the depletion device region, the enhancement device region and the bipolar device region, the passivation layer covering the second gate structure and the base; a first gate structure, formed on the passivation layer of the depletion device region, the passivation layer between the first gate structure and the substrate serving as a gate dielectric layer; a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, the first source metal and the first drain metal being formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal being formed on the substrate on both sides of the second gate structure, the emitter metal and the collector metal being formed on the substrate on both sides of the base.

[0050] See below Figure 1The semiconductor device provided by this embodiment is described in more detail. Figure 1 It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0051] The substrate includes a depletion type device region A1, an enhancement type device region A2 and a bipolar type device region A3.

[0052] The depletion-type device region A1 is used to form a depletion-type device, the enhancement-type device region A2 is used to form an enhancement-type device, and the bipolar device region A3 is used to form a bipolar device.

[0053] The base includes a substrate 10 , and a buffer layer 101 , a first nitride layer 102 , and a second nitride layer 103 formed on the substrate 10 from bottom to top.

[0054] The substrate 10 may be made of any appropriate semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, GaN, InAs, InP or sapphire, and the buffer layer 101 may be made of GaN or AlGaN.

[0055] The first nitride layer 102 and the second nitride layer 103 are made of different materials. In one embodiment, the first nitride layer 102 is made of GaN, and the second nitride layer 103 is made of AlGaN, so that the first nitride layer 102 and the second nitride layer 103 can form a heterojunction structure.

[0056] The second gate structure is formed on the substrate in the enhancement mode device region A2.

[0057] The base is formed on the substrate of the bipolar device region A3 and extends into the substrate of the bipolar device region A3.

[0058] The passivation layer 15 is formed on the substrate of the depletion-type device region A1 , the enhancement-type device region A2 , and the bipolar device region A3 , and the passivation layer 15 covers the second gate structure and the base.

[0059] The first gate structure is formed on the passivation layer 15 of the depletion-mode device region A1 , and the passivation layer 15 between the first gate structure and the substrate serves as a gate dielectric layer.

[0060] In one embodiment, the substrate further includes an enhanced power device region A4, and the enhanced power device region A4 is used to form an enhanced power device.

[0061] The semiconductor device further includes: a third gate structure formed on the substrate of the enhanced power device region A4, and the passivation layer 15 is also formed on the substrate of the enhanced power device region A4 and the third gate structure.

[0062] In one embodiment, the first gate structure includes a first metal gate layer 14, and the second gate structure and the third gate structure both include a nitride gate layer 12 and a second metal gate layer 131 from bottom to top; the base includes a nitride base layer 11 and a metal base layer from bottom to top (in order to distinguish it from other metal base layers, the metal base layer here is defined as a first metal base layer 132), the nitride base layer 11 extends from the substrate of the bipolar device area A3 to the substrate, and the passivation layer 15 covers the nitride gate layer 12, the second metal gate layer 131, the nitride base layer 11 and the first metal base layer 132.

[0063] The base electrode may extend from the substrate to penetrate the second nitride layer 103 and the first nitride layer 102. The base electrode may just penetrate the second nitride layer 103 and the first nitride layer 102 and contact the top surface of the buffer layer 101, or the base electrode may penetrate the second nitride layer 103 and the first nitride layer 102 and enter the buffer layer 101. Figure 1 In the illustrated embodiment, the nitride base layer 11 in the base just penetrates the second nitride layer 103 and the first nitride layer 102 and contacts the top surface of the buffer layer 101 .

[0064] Since the first nitride layer 102 and the second nitride layer 103 can form a heterojunction structure, a two-dimensional electron gas with high concentration and high mobility is naturally formed between the first nitride layer 102 and the second nitride layer 103 of the bipolar device area A3 at the periphery of the base (also at the periphery of the nitride base layer 11), that is, the two-dimensional electron gas region is equivalent to the presence of doped ions, and the doping type of the nitride base layer 11 is different from the doping type of the two-dimensional electron gas region, thereby making the two-dimensional electron gas formed between the first nitride layer 102 and the second nitride layer 103 of the bipolar device area A3 on both sides of the nitride base layer 11 can serve as an emitter and a collector, respectively, so that the bipolar device area A3 can form a bipolar device.

[0065] In one embodiment, the doping type of the nitride base layer 11 is P-type, and the two-dimensional electron gas region is equivalent to being doped with N-type.

[0066] In the depletion mode device region A1 , the enhancement mode device region A2 , and the enhancement mode power device region A4 , the first nitride layer 102 may be used as a channel layer, and the second nitride layer 103 may be used as a barrier layer.

[0067] Preferably, a third metal gate layer (not shown) may be formed on the first metal gate layer 14 and the second metal gate layer 131, and a second metal base layer (not shown) may be formed on the first metal base layer 132, the third metal gate layer penetrates the passivation layer 15 and is connected to the second metal gate layer 131, the second metal base layer penetrates the passivation layer 15 and is connected to the first metal base layer 132, then, the first gate structure, the second gate structure and the third gate structure all include the third metal gate layer, and the base also includes the second metal base layer.

[0068] By providing the third metal gate layer and the second metal base layer, the thicknesses of the first gate structure, the second gate structure, the third gate structure and the base are increased, thereby enabling the parasitic gate resistance and the parasitic base resistance to be reduced respectively.

[0069] The material of the portion of the nitride gate layer 12 and the nitride base layer 11 located on the substrate may include GaN, AlN or AlGaN.

[0070] The materials of the first metal gate layer 14, the second metal gate layer 131, the third metal gate layer, the first metal base layer 132 and the second metal base layer may include at least one of metal (such as palladium, titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide.

[0071] The materials of the second metal gate layer 131 of the enhanced device area A2, the second metal gate layer 131 of the enhanced power device area A4, and the first metal base layer 132 may be the same or different. Since the second metal gate layer 131 of the enhanced device area A2 and the nitride gate layer 12, the second metal gate layer 131 of the enhanced power device area A4 and the nitride gate layer 12, and the first metal base layer 132 and the nitride base layer 11 may be Schottky contacts or ohmic contacts, the second metal gate layer 131 of the enhanced device area A2, the second metal gate layer 131 of the enhanced power device area A4, and the first metal base layer 132 may be selected from appropriate materials and layers according to different contact types.

[0072] The material of the passivation layer 15 may include AlN, Al 2 O3 、SiO 2 and at least one of SiN, etc.

[0073] The first source metal 161 and the first drain metal 162 are formed on the substrate of the depletion device area A1 on both sides of the first gate structure, the second source metal 163 and the second drain metal 164 are formed on the substrate of the enhancement device area A2 on both sides of the second gate structure, and the emitter metal 165 and the collector metal 166 are formed on the substrate of the bipolar device area A3 on both sides of the base.

[0074] When the substrate further includes an enhanced power device region A4, the semiconductor device further includes: a third source metal 167 and a third drain metal 168 formed on the substrate of the enhanced power device region A4 on both sides of the third gate structure.

[0075] In one embodiment, the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167, and the third drain metal 168 penetrate the passivation layer 15 and the second nitride layer 103 to make ohmic contact with the first nitride layer 102. The top surfaces of the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167, and the third drain metal 168 are flush with or higher than the top surface of the passivation layer 15.

[0076] In other embodiments, the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167 and the third drain metal 168 may also only penetrate the passivation layer 15, or penetrate the passivation layer 15 and extend into the partial thickness of the second nitride layer 103.

[0077] The semiconductor device further includes an interlayer dielectric layer 17, which is formed on the passivation layer 15 and covers the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, and the third drain metal 168. The interlayer dielectric layer 17 may include a plurality of stacked insulating layers (not shown).

[0078] Preferably, the semiconductor device further comprises: at least one field plate 18 formed on the passivation layer 15 of the enhanced power device region A4. By providing the field plate 18 on the enhanced power device region A4, the withstand voltage of the enhanced power device can be improved.

[0079] The field plate 18 may be formed between the interlayer dielectric layer 17 and the passivation layer 15 and / or inside the interlayer dielectric layer 17 .

[0080] When the field plates 18 are at least two layers, the field plates 18 of adjacent layers are insulated by the interlayer dielectric layer 17 , and the projections of the field plates 18 of adjacent layers in a direction perpendicular to the substrate surface may overlap or not overlap.

[0081] The field plate 18 may be made of at least one of metal (eg, palladium, titanium, aluminum, or tungsten), metal nitride (titanium nitride or tungsten nitride), and metal silicide.

[0082] The semiconductor device also includes: a metal interconnection structure (not shown), which is respectively formed in the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the interlayer dielectric layer 17 on the field plate 18, and the top surface of the interlayer dielectric layer 17 exposes a part of the structure of the metal interconnection structure, so that the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the field plate 18 are respectively led out through the metal interconnection structure. Among them, the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the metal interconnection structure on the field plate 18 can be connected or not connected.

[0083] The metal interconnection structure may include a plurality of layers of conductive plugs and a plurality of layers of metal interconnection lines, and the metal interconnection lines of adjacent layers are electrically connected through the conductive plugs.

[0084] In one embodiment, the depletion-mode device may be a depletion-mode HEMT (High Electron Mobility Transistor) device, the enhancement-mode device may be an enhancement-mode HEMT device, the bipolar device may be a bipolar transistor, and the enhancement-mode power device may be an enhancement-mode HEMT power device.

[0085] The threshold voltage of the depletion-mode device is less than 0V; the threshold voltage of the enhancement-mode device and the enhancement-mode power device is greater than 0V; when the bipolar device is in an amplification state, the voltage difference between the base and the emitter is greater than 0V.

[0086] Preferably, the lengths of the first gate structure, the second gate structure, the base and the third gate structure are all 0.1 μm to 2 μm, so that the performance (such as switching speed, power consumption, etc.) of the depletion-mode device, the enhancement-mode device, the bipolar device and the enhancement-mode power device is better. The length refers to the length in the direction from the first source metal 161 to the first drain metal 162.

[0087] Preferably, the thickness of the passivation layer 15 is 0-100 nm, so as to reduce the dynamic on-resistance of the depletion-mode device, the enhancement-mode device, the bipolar device and the enhancement-mode power device.

[0088] In addition, an isolation structure (not shown) is formed between any adjacent regions of the depletion device region A1, the enhancement device region A2, the bipolar device region A3 and the enhancement power device region A4, and the isolation structure may be an ion-doped region or a groove.

[0089] It can be seen from the above content that the substrate includes a depletion device region A1, an enhancement device region A2 and a bipolar device region A3. Since the base is formed on the substrate of the bipolar device region A3 and extends into the substrate of the bipolar device region A3, the bipolar device formed by the bipolar device region A3 can be integrated with the device formed by the depletion device region A1 and the enhancement device region A2; and since the passivation layer 15 is formed on the substrate of the depletion device region A1, the enhancement device region A2 and the bipolar device region A3, the passivation layer 15 covers the second gate structure and the base of the enhancement device region A2, the first gate structure is formed on the passivation layer 15 of the depletion device region A1, and the passivation layer 15 between the first gate structure and the substrate serves as a gate dielectric layer, so that the depletion device formed by the depletion device region A1 can be integrated with the enhancement device formed by the enhancement device region A2 to achieve IC. Therefore, the preparation processes of depletion-mode devices, enhancement-mode devices and bipolar devices are compatible, thereby realizing the integration of depletion-mode devices, enhancement-mode devices and bipolar devices.

[0090] Furthermore, when the substrate further includes the enhanced power device region A4, the passivation layer 15 is also formed on the substrate and the third gate structure of the enhanced power device region A4, so that the preparation processes of the depletion-type device, the enhancement-type device, the bipolar device and the enhancement-type power device are compatible, thereby realizing the integration of the depletion-type device, the enhancement-type device, the bipolar device and the enhancement-type power device. The depletion-type device and the enhancement-type device are used as digital devices, the bipolar device is used as an analog device, and the enhancement-type power device is used as a power device, that is, the integration of digital devices, analog devices and power devices is realized.

[0091] In summary, the semiconductor device provided by the present invention includes: a substrate, including a depletion device region, an enhancement device region and a bipolar device region; a second gate structure, formed on the substrate in the enhancement device region; a base, formed on the substrate in the bipolar device region and extending into the substrate in the bipolar device region; a passivation layer, formed on the substrate in the depletion device region, the enhancement device region and the bipolar device region, the passivation layer covering the second gate structure and the base; a first gate structure, formed on the passivation layer in the depletion device region, the passivation layer between the first gate structure and the substrate serving as a gate dielectric layer; a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, the first source metal and the first drain metal being formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal being formed on the substrate on both sides of the second gate structure, the emitter metal and the collector metal being formed on the substrate on both sides of the base. The semiconductor device of the present invention can realize the integration of a depletion-type device, an enhancement-type device and a bipolar device.

[0092] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 2 , Figure 2 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, wherein the method for manufacturing a semiconductor device comprises:

[0093] Step S1, providing a substrate, wherein the substrate comprises a depletion type device region, an enhancement type device region and a bipolar device region;

[0094] Step S2, forming a second gate structure, a base, a passivation layer and a first gate structure, wherein the second gate structure is formed on the substrate of the enhancement device region; the base is formed on the substrate of the bipolar device region and extends into the substrate of the bipolar device region; the passivation layer is formed on the substrates of the depletion device region, the enhancement device region and the bipolar device region, and the passivation layer covers the second gate structure and the base; the first gate structure is formed on the passivation layer of the depletion device region, and the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer;

[0095] Step S3, forming a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base.

[0096] See below Figure 3a to Figure 3h The method for manufacturing the semiconductor device provided in this embodiment is described in more detail. Figure 3a to Figure 3h It is a schematic diagram of a longitudinal cross-section of a semiconductor device.

[0097] According to step S1, Figure 3a As shown, a substrate is provided, the substrate comprising a depletion type device region A1, an enhancement type device region A2 and a bipolar type device region A3.

[0098] The depletion-type device region A1 is used to form a depletion-type device, the enhancement-type device region A2 is used to form an enhancement-type device, and the bipolar device region A3 is used to form a bipolar device.

[0099] The base includes a substrate 10 , and a buffer layer 101 , a first nitride layer 102 , and a second nitride layer 103 formed on the substrate 10 from bottom to top.

[0100] The substrate 10 may be made of any appropriate semiconductor material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, GaN, InAs, InP or sapphire, and the buffer layer 101 may be made of GaN or AlGaN.

[0101] The first nitride layer 102 and the second nitride layer 103 are made of different materials. In one embodiment, the first nitride layer 102 is made of GaN, and the second nitride layer 103 is made of AlGaN, so that the first nitride layer 102 and the second nitride layer 103 can form a heterojunction structure.

[0102] According to step S2, Figure 3a to Figure 3f As shown, a second gate structure, a base, a passivation layer 15 and a first gate structure are formed, wherein the second gate structure is formed on the substrate of the enhancement device area A2; the base is formed on the substrate of the bipolar device area A3 and extends into the substrate of the bipolar device area A3; the passivation layer 15 is formed on the substrates of the depletion device area A1, the enhancement device area A2 and the bipolar device area A3, and the passivation layer 15 covers the second gate structure and the base; the first gate structure is formed on the passivation layer 15 of the depletion device area A1, and the passivation layer 15 between the first gate structure and the substrate serves as a gate dielectric layer.

[0103] In one embodiment, the substrate further includes an enhanced power device region A4, and the enhanced power device region A4 is used to form an enhanced power device.

[0104] The method for manufacturing the semiconductor device further includes: forming a third gate structure on the substrate of the enhanced power device area A4, and the passivation layer 15 is also formed on the substrate of the enhanced power device area A4 and the third gate structure.

[0105] In one embodiment, the steps of forming the second gate structure, the base, the passivation layer 15, the first gate structure and the third gate structure may include: first, Figure 3d As shown, a nitride gate layer 12 and a second metal gate layer 131 are formed and stacked on the substrate of the enhancement device area A2 and the enhancement power device area A4, and a nitride base layer 11 and a metal base layer (in order to distinguish it from other metal base layers, the metal base layer here is defined as the first metal base layer 132) are stacked on the substrate of the bipolar device area A3, and the nitride base layer 11 also extends into the substrate of the bipolar device area A3; then, as shown Figure 3e As shown, a passivation layer 15 is formed on the substrate of the depletion device region A1, the enhancement device region A2, the bipolar device region A3 and the enhancement power device region A4, and the passivation layer 15 covers the nitride gate layer 12, the second metal gate layer 131, the nitride base layer 11 and the first metal base layer 132; then, as Figure 3fAs shown, a first metal gate layer 14 is formed on the passivation layer 15 of the depletion device area A1, so that the first gate structure includes the first metal gate layer 14, the second gate structure and the third gate structure both include the nitride gate layer 12 and the second metal gate layer 131, and the base includes the nitride base layer 11 and the first metal base layer 132.

[0106] In one embodiment, the steps of forming the nitride gate layer 12, the second metal gate layer 131, the nitride base layer 11 and the first metal base layer 132 may include: first, Figure 3a As shown, a third nitride layer 104 is formed on the substrate; then, as shown Figure 3b As shown, a patterned photoresist layer 106 is formed on the third nitride layer 104, the patterned photoresist layer 106 exposes a portion of the third nitride layer 104 in the bipolar device area A3, and ions are implanted into the portion of the third nitride layer 104 and a portion of the substrate exposed by the patterned photoresist layer 106 using the patterned photoresist layer 106 as a mask to form a doping layer 111; then, the patterned photoresist layer 106 is removed; then, as shown Figure 3c As shown, a metal layer 105 is formed on the third nitride layer 104, and the metal layer 105 covers the doping layer 111; then, as shown in Figure 3d As shown, the metal layer 105 and the third nitride layer 104 are etched to form the stacked nitride gate layer 12 and the second metal gate layer 131 on the substrate of the enhanced device area A2 and the enhanced power device area A4, and the doping layer 111 is formed into the nitride base layer 11, and the first metal base layer 132 is formed on the nitride base layer 11, that is, the third nitride layer 104 remaining on the enhanced device area A2 and the enhanced power device area A4 after etching serves as the nitride gate layer 12, the metal layer 105 remaining on the enhanced device area A2 and the enhanced power device area A4 serves as the second metal gate layer 131, and the metal layer 105 remaining on the nitride base layer 11 serves as the first metal base layer 132.

[0107] It should be noted that in Figure 3a to Figure 3dIn the embodiment shown, the nitride gate layer 12 and the nitride base layer 11 located on the substrate are formed simultaneously by the same deposition process (i.e., depositing the third nitride layer 104) and the same etching process, and the second metal gate layer 131 and the first metal base layer 132 are formed simultaneously by the same deposition process (i.e., depositing the metal layer 105) and the same etching process. The formation method of the nitride gate layer 12, the nitride base layer 11, the second metal gate layer 131 and the first metal base layer 132 is not limited to Figure 3a to Figure 3d In the embodiment shown, in other embodiments, the nitride gate layer 12 of the enhanced device area A2, the nitride gate layer 12 of the enhanced power device area A4 and the portion of the nitride base layer 11 located on the substrate can be formed in separate steps, and the second metal gate layer 131 of the enhanced device area A2, the second metal gate layer 131 of the enhanced power device area A4 and the first metal base layer 132 can be formed in separate steps.

[0108] The base electrode may extend from the substrate to penetrate the second nitride layer 103 and the first nitride layer 102. The base electrode may just penetrate the second nitride layer 103 and the first nitride layer 102 and contact the top surface of the buffer layer 101, or the base electrode may penetrate the second nitride layer 103 and the first nitride layer 102 and enter the buffer layer 101. Figure 3d In the illustrated embodiment, the nitride base layer 11 in the base just penetrates the second nitride layer 103 and the first nitride layer 102 and contacts the top surface of the buffer layer 101 .

[0109] Since the first nitride layer 102 and the second nitride layer 103 can form a heterojunction structure, a two-dimensional electron gas with high concentration and high mobility is naturally formed between the first nitride layer 102 and the second nitride layer 103 of the bipolar device area A3 at the periphery of the base (also at the periphery of the nitride base layer 11), that is, the two-dimensional electron gas region is equivalent to the presence of doped ions, and the doping type of the nitride base layer 11 is different from the doping type of the two-dimensional electron gas region, thereby making the two-dimensional electron gas formed between the first nitride layer 102 and the second nitride layer 103 of the bipolar device area A3 on both sides of the nitride base layer 11 can serve as an emitter and a collector, respectively, so that the bipolar device area A3 can form a bipolar device.

[0110] In one embodiment, the doping type of the nitride base layer 11 is P-type, and the two-dimensional electron gas region is equivalent to being doped with N-type.

[0111] In the depletion mode device region A1 , the enhancement mode device region A2 , and the enhancement mode power device region A4 , the first nitride layer 102 may be used as a channel layer, and the second nitride layer 103 may be used as a barrier layer.

[0112] Preferably, after forming the first metal gate layer 14, a third metal gate layer (not shown) may be formed on the first metal gate layer 14 and the second metal gate layer 131, and a second metal base layer (not shown) may be formed on the first metal base layer 132, the third metal gate layer penetrates the passivation layer 15 and is connected to the second metal gate layer 131, the second metal base layer penetrates the passivation layer 15 and is connected to the first metal base layer 132, then, the first gate structure, the second gate structure and the third gate structure all also include the third metal gate layer, and the base also includes the second metal base layer.

[0113] By providing the third metal gate layer and the second metal base layer, the thicknesses of the first gate structure, the second gate structure, the third gate structure and the base are increased, thereby enabling the parasitic gate resistance and the parasitic base resistance to be reduced respectively.

[0114] The material of the portion of the nitride gate layer 12 and the nitride base layer 11 located on the substrate may include GaN, AlN or AlGaN.

[0115] The materials of the first metal gate layer 14, the second metal gate layer 131, the third metal gate layer, the first metal base layer 132 and the second metal base layer may include at least one of metal (such as palladium, titanium, aluminum or tungsten), metal nitride (titanium nitride or tungsten nitride) and metal silicide.

[0116] The materials of the second metal gate layer 131 of the enhanced device area A2, the second metal gate layer 131 of the enhanced power device area A4, and the first metal base layer 132 may be the same or different. Since the second metal gate layer 131 of the enhanced device area A2 and the nitride gate layer 12, the second metal gate layer 131 of the enhanced power device area A4 and the nitride gate layer 12, and the first metal base layer 132 and the nitride base layer 11 may be Schottky contacts or ohmic contacts, the second metal gate layer 131 of the enhanced device area A2, the second metal gate layer 131 of the enhanced power device area A4, and the first metal base layer 132 may be selected from appropriate materials and layers according to different contact types.

[0117] The material of the passivation layer 15 may include AlN, Al 2 O 3 、SiO 2 and at least one of SiN, etc.

[0118] According to step S3, Figure 3g As shown, a first source metal 161, a first drain metal 162, a second source metal 163, a second drain metal 164, an emitter metal 165 and a collector metal 166 are formed, the first source metal 161 and the first drain metal 162 are formed on the substrate of the depletion-type device area A1 on both sides of the first gate structure, the second source metal 163 and the second drain metal 164 are formed on the substrate of the enhancement-type device area A2 on both sides of the second gate structure, and the emitter metal 165 and the collector metal 166 are formed on the substrate of the bipolar device area A3 on both sides of the base.

[0119] When the substrate further includes an enhanced power device region A4, the method for manufacturing the semiconductor device further includes: forming a third source metal 167 and a third drain metal 168 on the substrate of the enhanced power device region A4 at both sides of the third gate structure.

[0120] In one embodiment, the step of forming the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167 and the third drain metal 168 may include: etching the passivation layer 15 and the second nitride layer 103 on both sides of the first gate structure, the second gate structure, the base and the third gate structure to form a plurality of through holes (not shown) exposing the first nitride layer 102, and filling the through holes with metal material to form the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167 and the third drain metal 168 in ohmic contact with the first nitride layer 102. The top surfaces of the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167, and the third drain metal 168 are flush with or higher than the top surface of the passivation layer 15. In other embodiments, the first source metal 161, the first drain metal 162, the second source metal 163, the second drain metal 164, the emitter metal 165, the collector metal 166, the third source metal 167, and the third drain metal 168 may also only penetrate the passivation layer 15, or penetrate the passivation layer 15 and extend into the second nitride layer 103 of a partial thickness.

[0121] like Figure 3h As shown, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer 17, wherein the interlayer dielectric layer 17 is formed on the passivation layer 15, and the interlayer dielectric layer 17 covers the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, and the third drain metal 168. The interlayer dielectric layer 17 may include a plurality of stacked insulating layers (not shown).

[0122] Preferably, the method for manufacturing the semiconductor device further comprises: forming at least one field plate 18 on the passivation layer 15 of the enhanced power device region A4. By providing the field plate 18 on the enhanced power device region A4, the withstand voltage of the enhanced power device can be improved.

[0123] The field plate 18 may be formed between the interlayer dielectric layer 17 and the passivation layer 15 and / or inside the interlayer dielectric layer 17 .

[0124] When the field plates 18 are at least two layers, the field plates 18 of adjacent layers are insulated by the interlayer dielectric layer 17 , and the projections of the field plates 18 of adjacent layers in a direction perpendicular to the substrate surface may overlap or not overlap.

[0125] In one embodiment, the field plate 18 between the interlayer dielectric layer 17 and the passivation layer 15 is formed simultaneously with the first metal gate layer 14 to simplify the process.

[0126] The field plate 18 may be made of at least one of metal (eg, palladium, titanium, aluminum, or tungsten), metal nitride (titanium nitride or tungsten nitride), and metal silicide.

[0127] The manufacturing method of the semiconductor device also includes: forming a metal interconnection structure (not shown) in the interlayer dielectric layer 17 on the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the field plate 18, respectively, and the top surface of the interlayer dielectric layer 17 exposes a part of the structure of the metal interconnection structure, so that the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the field plate 18 are led out through the metal interconnection structure. Among them, the first source metal 161, the first gate structure, the first drain metal 162, the second source metal 163, the second gate structure, the second drain metal 164, the emitter metal 165, the base, the collector metal 166, the third source metal 167, the third gate structure, the third drain metal 168 and the metal interconnection structure on the field plate 18 can be connected or not connected.

[0128] The metal interconnection structure may include a plurality of layers of conductive plugs and a plurality of layers of metal interconnection lines, and the metal interconnection lines of adjacent layers are electrically connected through the conductive plugs.

[0129] In one embodiment, the depletion-mode device may be a depletion-mode HEMT (High Electron Mobility Transistor) device, the enhancement-mode device may be an enhancement-mode HEMT device, the bipolar device may be a bipolar transistor, and the enhancement-mode power device may be an enhancement-mode HEMT power device.

[0130] The threshold voltage of the depletion-mode device is less than 0V; the threshold voltage of the enhancement-mode device and the enhancement-mode power device is greater than 0V; when the bipolar device is in an amplification state, the voltage difference between the base and the emitter is greater than 0V.

[0131] Preferably, the lengths of the first gate structure, the second gate structure, the base and the third gate structure are all 0.1 μm to 2 μm, so that the performance (such as switching speed, power consumption, etc.) of the depletion-mode device, the enhancement-mode device, the bipolar device and the enhancement-mode power device is better. The length refers to the length in the direction from the first source metal 161 to the first drain metal 162.

[0132] Preferably, the thickness of the passivation layer 15 is 0-100 nm, so as to reduce the dynamic on-resistance of the depletion-mode device, the enhancement-mode device, the bipolar device and the enhancement-mode power device.

[0133] In addition, an isolation structure (not shown) is formed between any adjacent regions of the depletion device region A1, the enhancement device region A2, the bipolar device region A3 and the enhancement power device region A4, and the isolation structure may be an ion-doped region or a groove.

[0134] It can be seen from the above content that the substrate includes a depletion device region A1, an enhancement device region A2 and a bipolar device region A3. Since the base is formed on the substrate of the bipolar device region A3 and extends into the substrate of the bipolar device region A3, the bipolar device formed by the bipolar device region A3 can be integrated with the device formed by the depletion device region A1 and the enhancement device region A2; and since the passivation layer 15 is formed on the substrate of the depletion device region A1, the enhancement device region A2 and the bipolar device region A3, the passivation layer 15 covers the second gate structure and the base of the enhancement device region A2, the first gate structure is formed on the passivation layer 15 of the depletion device region A1, and the passivation layer 15 between the first gate structure and the substrate serves as a gate dielectric layer, so that the depletion device formed by the depletion device region A1 can be integrated with the enhancement device formed by the enhancement device region A2 to achieve IC. Therefore, the processes for preparing depletion-mode devices, enhancement-mode devices and bipolar devices are compatible, thereby realizing the integration of depletion-mode devices, enhancement-mode devices and bipolar devices.

[0135] Furthermore, when the substrate further includes the enhanced power device region A4, the passivation layer 15 is also formed on the substrate and the third gate structure of the enhanced power device region A4, so that the processes for preparing depletion-type devices, enhancement-type devices, bipolar devices and enhancement-type power devices are compatible, thereby realizing the integration of depletion-type devices, enhancement-type devices, bipolar devices and enhancement-type power devices. Among them, the depletion-type device and the enhancement-type device are used as digital devices, the bipolar device is used as an analog device, and the enhancement-type power device is used as a power device, that is, the integration of digital devices, analog devices and power devices is realized.

[0136] In summary, the manufacturing method of the semiconductor device provided by the present invention comprises: providing a substrate, wherein the substrate comprises a depletion-type device region, an enhancement-type device region and a bipolar device region; forming a second gate structure, a base, a passivation layer and a first gate structure, wherein the second gate structure is formed on the substrate in the enhancement-type device region; the base is formed on the substrate in the bipolar device region and extends into the substrate in the bipolar device region; the passivation layer is formed on the depletion-type device region, the enhancement-type device region and the substrate in the bipolar device region, and the passivation layer covers the second gate structure and the base. The base; the first gate structure is formed on the passivation layer of the depletion device region, and the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer; a first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal are formed, the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base. The manufacturing method of the semiconductor device of the present invention realizes the integration of depletion-mode devices, enhancement-mode devices and bipolar devices.

[0137] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, including a depletion device region, an enhancement device region and a bipolar device region; A second gate structure is formed on the substrate in the enhancement mode device region; A base electrode is formed on the substrate of the bipolar device region and extends into the substrate of the bipolar device region; A passivation layer is formed on the substrate of the depletion-mode device region, the enhancement-mode device region and the bipolar device region, and the passivation layer covers the second gate structure and the base; A first gate structure is formed on the passivation layer in the depletion-mode device region, wherein the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer; A first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base.

2. The semiconductor device according to claim 1, wherein The substrate further includes an enhanced power device region, and the semiconductor device further includes: A third gate structure is formed on the substrate in the enhanced power device region, and the passivation layer is also formed on the substrate in the enhanced power device region and the third gate structure; A third source metal and a third drain metal are formed on the substrate at two sides of the third gate structure.

3. The semiconductor device according to claim 2, wherein: The first gate structure includes a first metal gate layer, the second gate structure and the third gate structure each include a nitride gate layer and a second metal gate layer from bottom to top; the base includes a nitride base layer and a metal base layer from bottom to top.

4. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: At least one field plate is formed on the passivation layer in the enhancement mode power device region.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The substrate includes a substrate and a buffer layer, a first nitride layer and a second nitride layer formed on the substrate from bottom to top, the base extends from the substrate to penetrate the second nitride layer and the first nitride layer, and a two-dimensional electron gas is formed between the first nitride layer and the second nitride layer in the bipolar device region outside the base.

6. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a depletion type device region, an enhancement type device region and a bipolar device region; forming a second gate structure, a base, a passivation layer and a first gate structure, wherein the second gate structure is formed on the substrate in the enhancement mode device region; The base is formed on the substrate of the bipolar device region and extends into the substrate of the bipolar device region; the passivation layer is formed on the depletion device region, the enhancement device region and the substrate of the bipolar device region, and the passivation layer covers the second gate structure and the base; The first gate structure is formed on the passivation layer in the depletion-mode device region, and the passivation layer between the first gate structure and the substrate serves as a gate dielectric layer; A first source metal, a first drain metal, a second source metal, a second drain metal, an emitter metal and a collector metal are formed, wherein the first source metal and the first drain metal are formed on the substrate on both sides of the first gate structure, the second source metal and the second drain metal are formed on the substrate on both sides of the second gate structure, and the emitter metal and the collector metal are formed on the substrate on both sides of the base.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The substrate further includes an enhanced power device region, and the method for manufacturing the semiconductor device further includes: forming a third gate structure on the substrate in the enhanced power device region, wherein the passivation layer is also formed on the substrate in the enhanced power device region and the third gate structure; A third source metal and a third drain metal are formed on the substrate at two sides of the third gate structure.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The steps of forming the second gate structure, the base, the passivation layer, the first gate structure and the third gate structure include: Forming a nitride gate layer and a second metal gate layer stacked on the substrate of the enhancement device region and the enhancement power device region, and forming a nitride base layer and a metal base layer stacked on the substrate of the bipolar device region, wherein the nitride base layer also extends into the substrate of the bipolar device region; Forming a passivation layer on the substrate of the depletion-mode device region, the enhancement-mode device region, the bipolar device region and the enhancement-mode power device region, wherein the passivation layer covers the nitride gate layer, the second metal gate layer, the nitride base layer and the metal base layer; A first metal gate layer is formed on the passivation layer in the depletion-mode device region, so that the first gate structure includes the first metal gate layer, the second gate structure and the third gate structure both include the nitride gate layer and the second metal gate layer, and the base includes the nitride base layer and the metal base layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The steps of forming the nitride gate layer, the second metal gate layer, the nitride base layer and the metal base layer include: forming a third nitride layer on the substrate; Performing ion implantation into a portion of the substrate and a portion of the third nitride layer in the bipolar device region to form a doping layer; forming a metal layer on the third nitride layer, wherein the metal layer covers the doping layer; The metal layer and the third nitride layer are etched to form the stacked nitride gate layer and the second metal gate layer on the substrate of the enhanced device area and the enhanced power device area, and the doped layer is formed into the nitride base layer, and the metal base layer is formed on the nitride base layer.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The method for manufacturing the semiconductor device further includes: At least one field plate is formed on the passivation layer in the enhancement mode power device region.

11. The method for manufacturing a semiconductor device according to any one of claims 6 to 10, wherein: The substrate includes a substrate and a buffer layer, a first nitride layer and a second nitride layer formed on the substrate from bottom to top, the base extends from the substrate to penetrate the second nitride layer and the first nitride layer, and a two-dimensional electron gas is formed between the first nitride layer and the second nitride layer in the bipolar device region outside the base.

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