Integrated device and preparation method thereof
By designing integrated devices in wireless optical communication systems, integrating light emitting structures and transistors using the groove structure of channel layer and barrier layer, direct electrical connection, the problems of low modulation bandwidth and large ohmic loss are solved, and higher modulation frequency and communication efficiency.
Patent Information
- Application Number
- CN202411057206.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-02
- Publication Date
- 2024-12-27
AI Technical Summary
In the existing wireless optical communication systems, the modulation bandwidth of the integrated devices is low, and the carrier frequency of wireless light cannot be fully utilized. In addition, the ohmic loss is large during the modulation process, which limits the communication efficiency.
An integrated device is designed to form grooves on the channel layer and barrier layer, integrate light emitting structures and transistors, reduce volume, directly electrically connect, avoid heat loss, and etch on the channel layer to form concaves. The groove is used to repair side wall damage and improve electron mobility and photoelectric efficiency.
The modulation frequency and photoelectric efficiency are improved, the integrated device volume and dislocation density are reduced, and the communication efficiency of wireless optical communication systems is improved.
Smart Images
Figure CN119208350A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of power electronics, and in particular to an integrated device and a method for preparing the same. Background Art
[0002] Wireless optical communication technology is a high-bandwidth, high-confidentiality and high-stability technology. Wireless optical communication technology is usually implemented using integrated devices.
[0003] In the related art, integrated devices include light emitting diodes (LEDs) and high electron mobility transistors (HEMTs), wherein LEDs are used as light sources to emit wireless light, and HEMTs are used for modulation.
[0004] However, the modulation bandwidth of the integrated device in the related technology is relatively low and cannot fully utilize the carrier frequency of the wireless light, which greatly limits the communication efficiency of the entire wireless optical communication system; and the ohmic loss of the integrated device during the modulation process is also large. Summary of the invention
[0005] The embodiment of the present disclosure provides an integrated device and a method for manufacturing the same, which can increase the modulation frequency, reduce the size of the integrated device, and reduce the ohmic loss of the integrated device. The technical solution is as follows:
[0006] On the one hand, an embodiment of the present disclosure provides an integrated device, which includes: a channel layer, a barrier layer, a light-emitting structure, a gate, a drain and a source; the channel layer and the barrier layer are stacked in sequence, the barrier layer has a groove exposing the channel layer, the light-emitting structure is located in the groove, the light-emitting structure includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence in the groove, the first semiconductor layer is electrically connected to the channel layer, and the second semiconductor layer is insulated from the channel layer; the source and the gate are both located on a side of the barrier layer away from the channel layer, the source is electrically connected to the channel layer through a through hole, and the drain is located on the surface of the second semiconductor layer and is electrically connected to the second semiconductor layer.
[0007] Optionally, the groove extends at least into the channel layer, the sidewall of the first semiconductor layer is electrically connected to the sidewall of the channel layer exposed by the groove, and the depth of the portion of the groove located in the channel layer is less than or equal to the thickness of the first semiconductor layer.
[0008] Optionally, the integrated device also includes a third semiconductor layer, the third semiconductor layer, the channel layer and the barrier layer are stacked in sequence, the conductivity type of the third semiconductor layer is the same as the conductivity type of the first semiconductor layer; the groove extends into the third semiconductor layer, the first semiconductor layer is located on the surface of the third semiconductor layer exposed by the groove, and the first semiconductor layer is electrically connected to the third semiconductor layer; the depth of the groove located in the channel layer and the third semiconductor layer is less than or equal to the thickness of the first semiconductor layer.
[0009] Optionally, the integrated device further includes a first reflective layer, which is located on a side of the channel layer away from the barrier layer; the first reflective layer includes multiple first material layers and multiple second material layers alternately stacked, and the refractive indexes of the first material layers and the second material layers are different.
[0010] Optionally, the first material layer is an AlN layer, and the second material layer is a GaN layer; or, the first material layer is a GaN layer, and the second material layer is a porous GaN layer.
[0011] Optionally, the channel layer includes a GaN layer, and the barrier layer includes at least one of an AlGaN layer and an AlN layer.
[0012] Optionally, the integrated device further includes a second reflective layer, which is located on a side of the second semiconductor layer away from the first semiconductor layer, and the orthographic projection of the groove on the surface of the channel layer away from the barrier layer is located within the orthographic projection of the second reflective layer on the surface of the channel layer away from the barrier layer.
[0013] Optionally, the groove has a width of 1 μm to 100 μm.
[0014] Optionally, the integrated device further includes: a passivation layer, a first pad, a second pad and a third pad, the passivation layer is located on the surface of the barrier layer away from the channel layer and the surface of the second semiconductor layer, and covers the source, the gate and the drain; the passivation layer has through holes respectively exposing the source, the gate and the drain, the first pad, the second pad and the third pad are all located on the surface of the passivation layer away from the second semiconductor layer, the first pad is connected to the source through the through hole, the second pad is connected to the gate through the through hole, and the third pad is connected to the drain through the through hole.
[0015] On the other hand, an embodiment of the present disclosure provides a method for preparing an integrated device, the preparation method comprising: providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence, the barrier layer having a groove exposing the channel layer; forming a light-emitting structure in the groove, the light-emitting structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked in the groove, the first semiconductor layer being electrically connected to the channel layer, and the second semiconductor layer being insulated from the channel layer; forming a source and a gate on a side of the barrier layer away from the channel layer, the source being electrically connected to the channel layer through a through hole; forming a drain on the surface of the second semiconductor layer, the drain being electrically connected to the second semiconductor layer.
[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:
[0017] In the integrated device provided by the embodiment of the present disclosure, the transistor and the light-emitting structure formed by the channel layer and the barrier layer are integrated into one device, which can improve the performance of the modulated light source in many aspects. First, from a structural point of view, the light-emitting structure and the transistor without metal connection are integrated together, which undoubtedly greatly reduces the volume of the final integrated device, allowing the transmitting end of the communication system to be further miniaturized. Secondly, from the perspective of energy efficiency, the direct electrical connection between the transistor and the light-emitting structure avoids the need to set up an additional connection structure between the two, which would cause heat loss, and further improves the power conversion efficiency of the integrated device.
[0018] In addition, the light-emitting device area on the integrated device is smaller, which means a smaller equivalent capacitor area, which can improve electron mobility and shorten the distance from the modulated gate to the multi-quantum well layer of the light-emitting structure. In addition, etching a groove on the channel layer and allowing the light-emitting diode to grow directly in the groove can repair the damage caused by etching on the sidewall of the groove, thereby reducing the dislocation density of the integrated device. These advantages combined improve the upper limit of the final modulation frequency and the overall photoelectric efficiency of the integrated device from multiple angles, can fully utilize the carrier frequency of the wireless light, and greatly improve the communication efficiency of the entire wireless optical communication system. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0020] Figure 1 is a schematic diagram of the structure of an integrated device provided by an embodiment of the present disclosure;
[0021] Figure 2 is a schematic diagram of a partial structure of an integrated device provided by an embodiment of the present disclosure;
[0022] Figure 3 is a partial structural schematic diagram of another integrated device provided by an embodiment of the present disclosure;
[0023] Figure 4 is a flow chart of a method for preparing an integrated device provided in an embodiment of the present disclosure;
[0024] Figure 5 is a diagram of a preparation state of an integrated device provided by an embodiment of the present disclosure;
[0025] Figure 6 It is a preparation state diagram of an integrated device provided in an embodiment of the present disclosure.
[0026] The descriptions of the marks in the figure are as follows:
[0027] 10. Substrate;
[0028] 21. channel layer; 22. barrier layer; 220. groove; 23. third semiconductor layer;
[0029] 24, first reflective layer; 241, first material layer; 242, second material layer;
[0030] 30. Light-emitting structure;
[0031] 31. first semiconductor layer; 32. multi-quantum well layer; 33. second semiconductor layer;
[0032] 34, second reflective layer; 341, third material layer; 342, fourth material layer;
[0033] 41. Source; 42. Drain; 43. Gate;
[0034] 51, first pad; 52, second pad; 53, third pad;
[0035] 60. Passivation layer;
[0036] 70. Mask layer;
[0037] 80. Buffer layer; 81. Non-intentionally doped gallium nitride layer; 82. Superlattice structure layer. DETAILED DESCRIPTION
[0038] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0039] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0040] Wireless optical communication technology, as a high-bandwidth, high-confidentiality and high-stability technology, has long been widely concerned. Among them, ultraviolet light communication in the 200nm to 300nm band has a special position in the near-ground communication environment due to the existence of the solar blind zone.
[0041] Specifically, because the ultraviolet light in the 200nm to 300nm band of sunlight is absorbed by the ozone layer, the background noise in this band in the near-ground atmospheric environment is reduced to an almost negligible level. This makes ultraviolet light in this band naturally suitable for various wireless optical communication scenarios near the ground, indoors and outdoors. In addition, various particles in the air also have a strong scattering effect on deep ultraviolet light, and these scattering effects can be used as a good non-line-of-sight communication link in wireless communication to reduce the need for directionality during communication.
[0042] However, on the one hand, the modulation bandwidth of the currently common ultraviolet modulated light source is still relatively low, and the frequency of the ultraviolet carrier cannot be fully utilized, which greatly limits the communication efficiency of the entire ultraviolet light communication system. On the other hand, ultraviolet light communication also has certain requirements on the radiation light power of the ultraviolet transmitter.
[0043] To this end, the embodiments of the present disclosure provide an integrated device with a higher modulation frequency. Figure 1 Schematic diagram of the structure of an integrated device provided by an embodiment of the present disclosure. Figure 1 As shown, the integrated device includes: a channel layer 21 , a barrier layer 22 , a light emitting structure 30 , a gate 43 , a drain 42 and a source 41 .
[0044] like Figure 1As shown, the channel layer 21 and the barrier layer 22 are stacked in sequence, the barrier layer 22 has a groove 220 exposing the channel layer 21 , and the light emitting structure 30 is located in the groove 220 .
[0045] Figure 2 FIG. 1 is a schematic diagram of a partial structure of an integrated device provided by an embodiment of the present disclosure. Figure 2 As shown, the light emitting structure 30 includes a first semiconductor layer 31 , a multi-quantum well layer 32 and a second semiconductor layer 33 sequentially stacked in the groove 220 . The first semiconductor layer 31 is electrically connected to the channel layer 21 , and the second semiconductor layer 33 is insulated from the channel layer 21 .
[0046] like Figure 1 , 2 As shown, the source 41 and the gate 43 are both located on the side of the barrier layer 22 away from the channel layer 21 , the source 41 is electrically connected to the channel layer 21 through a through hole, and the drain 42 is located on the surface of the second semiconductor layer 33 , and the drain 42 is electrically connected to the second semiconductor layer 33 .
[0047] In the integrated device provided by the embodiment of the present disclosure, the transistor formed by the channel layer 21 and the barrier layer 22 and the light-emitting structure 30 are integrated into one device, which can improve the performance of the modulated light source in many aspects. First, from a structural point of view, the light-emitting structure 30 and the transistor without metal connection are integrated together, which undoubtedly greatly reduces the volume of the final integrated device, allowing the transmitting end of the communication system to be further miniaturized. Secondly, from the perspective of energy efficiency, the direct electrical connection between the transistor and the light-emitting structure 30 avoids the need to set an additional connection structure between the two, which would cause heat loss, and further improves the power conversion efficiency of the integrated device.
[0048] In addition, the light-emitting device area on the integrated device is smaller, which means a smaller equivalent capacitor area, which can improve electron mobility and make the distance from the modulated gate 43 to the multi-quantum well layer 32 of the light-emitting structure 30 shorter. In addition, etching a groove on the channel layer and allowing the light-emitting diode to grow directly in the groove can repair the damage caused by etching on the side wall of the groove, thereby reducing the dislocation density of the integrated device. These advantages combined improve the upper limit of the final modulation frequency and the overall photoelectric efficiency of the integrated device from multiple angles, can fully utilize the carrier frequency of the wireless light, and greatly improve the communication efficiency of the entire wireless optical communication system.
[0049] Optionally, the surface of the barrier layer 22 has a plurality of grooves 220, and the plurality of grooves 220 are arranged in an array. In this way, a plurality of light-emitting structures 30 can be integrated on the transistor, thereby improving the emission intensity of the wireless light.
[0050] Exemplarily, the width of the groove 220 is 1 μm to 100 μm.
[0051] The width of the groove 220 refers to the maximum length of the groove 220 in a direction parallel to the surface of the channel layer 21 .
[0052] Exemplarily, the radial cross section of the groove 220 is circular. The width of the groove 220 is the diameter of the groove 220 .
[0053] The radial cross section of the groove 220 refers to a cross section parallel to the surface of the channel layer 21 .
[0054] Exemplarily, the width of the groove 220 may be 20 μm.
[0055] It should be noted that the radial cross-section of the groove 220 may also be a polygon, an ellipse or other shapes, which is not limited in the embodiment of the present disclosure.
[0056] Alternatively, if Figure 2 As shown, the groove 220 at least extends into the channel layer 21 , and the sidewall of the first semiconductor layer 31 is electrically connected to the sidewall of the channel layer 21 exposed by the groove 220 .
[0057] By etching the groove 220 into the channel layer 21, the first semiconductor layer 31 can be electrically connected to the channel layer 21 in addition to the bottom surface thereof. The side walls of the first semiconductor layer 31 can also be electrically connected to the side walls of the channel layer 21 exposed by the groove 220, thereby increasing the electrical connection area between the first semiconductor layer 31 and the channel layer 21, avoiding heat loss caused by setting an intermediate connection structure between the first semiconductor layer 31 and the channel layer 21, and improving the power conversion efficiency of the integrated device.
[0058] For example, Figure 2 As shown, the depth of the portion of the groove 220 located in the channel layer 21 is less than or equal to the thickness of the first semiconductor layer 31 .
[0059] In this way, the first semiconductor layer 31 protrudes from the groove of the channel layer 21, so that the side wall of the channel layer 21 can only be electrically connected to the first semiconductor layer 31, but not to other film layers of the light emitting structure 30, thereby preventing leakage or short circuit problems.
[0060] Optionally, the channel layer 21 includes a GaN layer, and the barrier layer 22 includes at least one of an AlGaN layer and an AlN layer.
[0061] Exemplarily, the channel layer 21 is a GaN layer, and the barrier layer 22 includes an AlGaN layer.
[0062] Exemplarily, the channel layer 21 is a GaN layer, and the barrier layer 22 includes an AlGaN layer and an AlN layer sequentially stacked on the channel layer 21. By providing an additional AlN layer in the barrier layer 22, a higher barrier can be formed, which is beneficial to improving the electron mobility of the transistor.
[0063] In one implementation, the light emitting structure 30 is an ultraviolet light emitting structure 30 , that is, the light emitted by the light emitting structure 30 is ultraviolet light.
[0064] Optionally, in the light emitting structure 30 , one of the first semiconductor layer 31 and the second semiconductor layer 33 is a p-type layer, and the other of the first semiconductor layer 31 and the second semiconductor layer 33 is an n-type layer.
[0065] Exemplarily, the first semiconductor layer 31 is an n-type layer, and the second semiconductor layer 33 is a p-type layer.
[0066] Optionally, the n-type layer may be an n-type GaN layer, and the thickness of the n-type GaN layer may be 0.5 μm to 2 μm.
[0067] Considering the absorption of ultraviolet light by GaN material, the n-type layer may also be an n-type AlGaN layer with indefinite composition.
[0068] Optionally, the n-type layer may be an n-type AlGaN layer, and the thickness of the n-type AlGaN layer may be 0.5 μm to 3 μm.
[0069] Optionally, the multi-quantum well layer 32 includes a plurality of Al x Ga 1-x N quantum well layer and multiple Al y Ga 1-y N quantum barrier layers.
[0070] Among them, 0<x<y<1, and the number of quantum well layers and quantum well layers can be 3 to 8 layers.
[0071] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 32 includes five layers of Al2O3 stacked alternately. x Ga 1-x N quantum well layers and 5 layers of Al y Ga 1-y N quantum barrier layers.
[0072] By way of example, the thickness of the multi-quantum well layer 32 may be 150 nm to 200 nm.
[0073] As an example, the quantum well layers and quantum barrier layers of the multi-quantum well layer 32 may also be AlInGaN layers of different compositions.
[0074] As an example, the quantum well layer of the multi-quantum well layer 32 may be a GaN layer, and the quantum barrier layer may be AlGaN.
[0075] As an example, the quantum well layer of the multi-quantum well layer 32 may be an InGaN layer, and the quantum barrier layer may be AlGaN.
[0076] Alternatively, the p-type layer may be a p-type AlGaN layer. The p-type AlGaN layer may have a thickness of 0.5 μm to 3 μm.
[0077] Alternatively, the p-type layer may be a Mg-doped p-type GaN layer. The p-type GaN layer may have a thickness of 0.5 μm to 2 μm.
[0078] In other implementations, the light emitting structure 30 may also be a light emitting structure 30 that emits light of other colors. For example, the wavelength of the light emitted by the light emitting structure 30 is 400 nm to 650 nm.
[0079] Alternatively, if Figure 1 , 2 As shown, the integrated device further includes a third semiconductor layer 23 . The third semiconductor layer 23 , the channel layer 21 and the barrier layer 22 are stacked in sequence. The conductivity type of the third semiconductor layer 23 is the same as that of the first semiconductor layer 31 .
[0080] Exemplarily, the first semiconductor layer 31 is an n-type AlGaN layer, so the third semiconductor layer 23 may be an n-type GaN layer. By providing an n-type GaN layer below the channel layer 21, the carrier concentration of the entire transistor can be uniformly increased.
[0081] like Figure 2 As shown, the groove 220 extends into the third semiconductor layer 23 , the first semiconductor layer 31 is located on the surface of the third semiconductor layer 23 exposed in the groove 220 , and the first semiconductor layer 31 is electrically connected to the third semiconductor layer 23 .
[0082] Since the groove 220 extends into the third semiconductor layer 23, the sidewall of the HEMT structure exposed by the groove 220 can be directly connected to a portion of the surface of the first semiconductor layer 31, thereby eliminating the connection structure between the transistor and the light-emitting structure 30 and directly reducing the related losses caused by the connection structure such as the electrode.
[0083] At the same time, since the third semiconductor layer 23 is an n-type GaN layer and the first semiconductor layer 31 is an n-type AlGaN layer, the regrown n-type AlGaN layer as the first semiconductor layer 31 can also well repair the sidewall of the n-type GaN layer damaged by etching, thereby reducing the performance loss caused thereby.
[0084] For example, Figure 2 As shown, the depth of the groove 220 located in the channel layer 21 and the third semiconductor layer 23 is less than or equal to the thickness of the first semiconductor layer 31 .
[0085] In this way, the first semiconductor layer 31 protrudes from the groove body formed by the third semiconductor and the channel layer 21, so that the side wall of the channel layer 21 and the side wall of the third semiconductor layer 23 can only be electrically connected to the first semiconductor layer 31, and will not be electrically connected to other film layers of the light-emitting structure 30, thereby preventing leakage or short circuit problems.
[0086] Alternatively, if Figure 1 As shown, the integrated device further includes a first reflective layer 24 , which is located on a side of the channel layer 21 away from the barrier layer 22 .
[0087] like Figure 1 As shown, the first reflective layer 24 includes a plurality of first material layers 241 and a plurality of second material layers 242 that are alternately stacked, and the first material layers 241 and the second material layers 242 have different refractive indexes.
[0088] When light passes through the first reflective layer 24, due to the different optical paths, the phases of the reflected light are also different. After mutual interference, the light of a specific wavelength will be strongly reflected to enhance the light output intensity of the light emitting device.
[0089] On the one hand, the central wavelength of the reflected light is determined by the thickness of the film layer. The smaller the refractive index of the film material and the longer the wavelength, the thicker the required film thickness. On the other hand, the reflectivity intensity of the reflection area is determined by the difference in refractive index of the two material layers in the area and the number of periods of the two material layers. The greater the difference in refractive index of the two material layers and the greater the number of periods of the film layer, the stronger the final reflectivity. In addition, the wavelength stopband width of the light reflected in the reflection area is also a relatively important indicator. This indicator is related to the central wavelength of reflection and the difference in refractive index of the two material layers in the area. The longer the wavelength, the greater the difference in refractive index of the two film materials, and the wider the stopband width. Therefore, the material layer selection standard for the reflection area is that the greater the difference in refractive index between the two, the better.
[0090] As an example, the first material layer 241 is an AlN layer, and the second material layer 242 is a GaN layer.
[0091] The first reflective layer 24 formed by combining AlN and GaN layers can be directly obtained by epitaxial growth, but the difference in refractive index between the AlN and GaN layers is small, more film structure periods are required, the final stopband width is narrow, and the peak reflectivity is difficult to reach an extremely high value.
[0092] As another example, the first material layer 241 is a GaN layer, and the second material layer 242 is a porous GaN layer.
[0093] Among them, the refractive index difference between the GaN layer and the porous GaN layer is very large, the required film layer period is fewer, the final group band width is wider, and the peak reflectivity is more ideal.
[0094] It should be noted that when preparing the porous GaN layer, it is necessary to first epitaxially grow the GaN layer and then perform an electrochemical etching process to etch a plurality of through holes on the surface of the GaN layer.
[0095] Alternatively, if Figure 1 As shown, the integrated device further includes: a substrate 10 and a buffer layer 80 , wherein the substrate 10 , the buffer layer 80 , the first reflective layer 24 , the third semiconductor layer 23 , the channel layer 21 and the barrier layer 22 are stacked in sequence.
[0096] Exemplarily, the substrate 10 is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.
[0097] Exemplarily, the buffer layer 80 may include a non-intentionally doped gallium nitride layer 81 and a superlattice structure layer 82 sequentially stacked on the substrate 10 .
[0098] The superlattice structure layer may be a periodic Al(Ga)N layer and a GaN layer for adjusting stress.
[0099] Exemplarily, at least one of an aluminum nitride layer, an aluminum gallium nitride layer and a gallium nitride layer may be disposed between the non-intentionally doped gallium nitride layer and the superlattice structure layer for buffering transition.
[0100] It should be noted that the buffer layer and the substrate 10 have no special role in the present disclosure after the epitaxial growth is completed, and can be peeled off or retained in subsequent processes depending on the arrangement.
[0101] Figure 3 FIG. 1 is a schematic diagram of a partial structure of another integrated device provided by an embodiment of the present disclosure. Figure 3 As shown, the integrated device further includes a second reflective layer 34 , and the second reflective layer 34 is located on a side of the second semiconductor layer 33 away from the first semiconductor layer 31 .
[0102] like Figure 3 As shown, the second reflective layer 34 includes a plurality of third material layers 341 and a plurality of fourth material layers 342 that are alternately stacked, and the third material layers 341 and the fourth material layers 342 have different refractive indexes.
[0103] By way of example, the third material layer 341 may be a silicon oxide layer, and the fourth material layer 342 may be a silicon nitride layer.
[0104] When light passes through the second reflective layer 34, due to the different optical paths, the phases of the reflected light are also different. After mutual interference, it will produce strong reflection on the light of a specific wavelength to change the light emitting direction of the light emitting device.
[0105] At the same time, the second reflective layer 34 can form a Fabry-Perot resonant cavity with the first reflective layer 24 to achieve amplification of the optical signal, thereby improving the sensitivity and accuracy of the integrated device.
[0106] It should be noted that when the Fabry-Perot cavity is not necessary, only the first reflection layer 24 or the second reflection layer 34 may be used to enhance reflection in a specific direction.
[0107] The orthographic projection of the groove 220 on the surface of the channel layer 21 away from the barrier layer 22 is located within the orthographic projection of the second reflective layer 34 on the surface of the channel layer 21 away from the barrier layer 22 .
[0108] In this way, the second reflective layer 34 is only disposed above the light emitting structure 30 , thereby avoiding the problem that the second reflective layer 34 is stacked on other regions of the integrated device and increases the thickness of the integrated device.
[0109] Alternatively, if Figure 2 As shown, the integrated device also includes: a passivation layer 60, a first pad 51, a second pad 52 and a third pad 53, the passivation layer 60 is located on the surface of the barrier layer 22 away from the channel layer 21 and the surface of the second semiconductor layer 33, and covers the source 41, the gate 43 and the drain 42.
[0110] like Figure 2 As shown, the passivation layer 60 has through holes that expose the source 41, the gate 43 and the drain 42 respectively, and the first pad 51, the second pad 52 and the third pad 53 are all located on the surface of the passivation layer 60 away from the second semiconductor layer 33. The first pad 51 is connected to the source 41 through the through hole, the second pad 52 is connected to the gate 43 through the through hole, and the third pad 53 is connected to the drain 42 through the through hole.
[0111] Exemplarily, the passivation layer may be a silicon oxide layer.
[0112] By providing a passivation layer to cover the barrier layer 22, the light emitting device, the gate 43, the drain 42 and the source 41, the epitaxial material and the electrode can be protected and leakage and short circuit problems can be prevented.
[0113] In the embodiment of the present disclosure, the first pad 51, the second pad 52 and the third pad 53 are used for an external power supply. The first pad 51 supplies power to the first semiconductor layer 31 of the light-emitting structure 30 through the source electrode 41, and the third pad 53 supplies power to the second semiconductor layer 33 of the light-emitting structure 30 through the drain electrode 42. The second pad 52 is electrically connected to the gate electrode 43 to control whether the source electrode 41 and the first semiconductor layer 31 are conductive, thereby controlling whether the light-emitting device emits light.
[0114] Figure 4 FIG. 1 is a flow chart of a method for preparing an integrated device provided by an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:
[0115] S11: providing a substrate 10.
[0116] Exemplarily, the substrate 10 is a sapphire substrate. The sapphire substrate has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the transistor has good stability.
[0117] S12 : forming a channel layer 21 and a barrier layer 22 in sequence on the substrate 10 .
[0118] The barrier layer 22 has a groove 220 exposing the channel layer 21 .
[0119] S13 : forming a light emitting structure 30 in the groove 220 .
[0120] The light emitting structure 30 includes a first semiconductor layer 31 , a multi-quantum well layer 32 and a second semiconductor layer 33 sequentially stacked in the groove 220 . The first semiconductor layer 31 is electrically connected to the channel layer 21 , and the second semiconductor layer 33 is insulated from the channel layer 21 .
[0121] S14 : forming the source electrode 41 and the gate electrode 43 on the side of the barrier layer 22 away from the channel layer 21 .
[0122] The source electrode 41 is electrically connected to the channel layer 21 through a through hole.
[0123] S15 : forming a drain electrode 42 on the surface of the second semiconductor layer 33 .
[0124] The drain electrode 42 is electrically connected to the second semiconductor layer 33 .
[0125] In the integrated device prepared by this preparation method, the transistor formed by the channel layer 21 and the barrier layer 22 and the light-emitting structure 30 are integrated into one device, which can improve the performance of the modulated light source in many aspects. First of all, from a structural point of view, the light-emitting structure 30 and the transistor without metal connection are integrated together, which undoubtedly greatly reduces the volume of the final integrated device, allowing the transmitting end of the communication system to be further miniaturized. Secondly, from the perspective of energy efficiency, the direct electrical connection between the transistor and the light-emitting structure 30 avoids the need to set an additional connection structure between the two, which would cause heat loss, and further improves the power conversion efficiency of the integrated device.
[0126] In addition, the light-emitting device area on the integrated device is smaller, which means a smaller equivalent capacitor area, which can improve electron mobility and make the distance from the modulated gate 43 to the multi-quantum well layer 32 of the light-emitting structure 30 shorter. In addition, etching a groove on the channel layer and allowing the light-emitting diode to grow directly in the groove can repair the damage caused by etching on the side wall of the groove, thereby reducing the dislocation density of the integrated device. These advantages combined improve the upper limit of the final modulation frequency and the overall photoelectric efficiency of the integrated device from multiple angles, can fully utilize the carrier frequency of the wireless light, and greatly improve the communication efficiency of the entire wireless optical communication system.
[0127] The specific process of the method for preparing the integrated device in the embodiment of the present disclosure may include the following steps:
[0128] In the first step, a non-intentionally doped gallium nitride layer and a superlattice structure layer are grown on a sapphire substrate using a MOCVD (Metal-organic Chemical Vapor Deposition) process to obtain a buffer layer.
[0129] The second step is to grow a first reflective layer 24 on the buffer layer.
[0130] Exemplarily, the first reflective layer 24 is located on a side of the channel layer 21 away from the barrier layer 22 .
[0131] The first reflective layer 24 includes a plurality of first material layers 241 and a plurality of second material layers 242 that are alternately stacked, and the first material layers 241 and the second material layers 242 have different refractive indexes.
[0132] As an example, the first material layer 241 is an AlN layer, and the second material layer 242 is a GaN layer.
[0133] As another example, the first material layer 241 is a GaN layer, and the second material layer 242 is a porous GaN layer.
[0134] The porous GaN layer refers to a GaN layer having a plurality of through holes with a scale of several nanometers to several hundred nanometers distributed in a direction perpendicular to the surface normal of the GaN layer.
[0135] The third step is Figure 5 As shown, the third semiconductor layer 23 is grown on the surface of the first reflective layer 24 .
[0136] Exemplarily, the third semiconductor layer 23 may be an n-type GaN layer.
[0137] The fourth step is Figure 5 As shown, a channel layer 21 and a barrier layer 22 are sequentially grown on the surface of the third semiconductor layer 23 .
[0138] Optionally, the channel layer 21 includes a GaN layer, and the barrier layer 22 includes at least one of an AlGaN layer and an AlN layer.
[0139] Exemplarily, the channel layer 21 is a GaN layer, and the barrier layer 22 includes an AlGaN layer.
[0140] Exemplarily, the channel layer 21 is a GaN layer, and the barrier layer 22 includes an AlGaN layer and an AlN layer sequentially stacked on the channel layer 21. By providing an additional AlN layer in the barrier layer 22, a higher barrier can be formed, which is beneficial to improving the electron mobility of the transistor.
[0141] Step 5: Figure 5 As shown, a mask layer 70 is formed on the surface of the barrier layer 22 , and a groove 220 exposing at least the third semiconductor layer 23 is formed by etching on the mask layer 70 .
[0142] Exemplarily, the mask layer may be a silicon oxide layer.
[0143] Optionally, the surface of the barrier layer 22 has a plurality of grooves 220, and the plurality of grooves 220 are arranged in an array. In this way, a plurality of light-emitting structures 30 can be integrated on the transistor, thereby improving the emission intensity of the wireless light.
[0144] Exemplarily, the width of the groove 220 is 1 μm to 100 μm.
[0145] The width of the groove 220 refers to the maximum length of the groove 220 in a direction parallel to the surface of the channel layer 21 .
[0146] Exemplarily, the radial cross section of the groove 220 is circular. The width of the groove 220 is the diameter of the groove 220 .
[0147] The radial cross section of the groove 220 refers to a cross section parallel to the surface of the channel layer 21 .
[0148] Exemplarily, the width of the groove 220 may be 20 μm.
[0149] It should be noted that the radial cross-section of the groove 220 may also be a polygon, an ellipse or other shapes, which is not limited in the embodiment of the present disclosure.
[0150] Step 6: Figure 5 As shown, a first semiconductor layer 31 , a multi-quantum well layer 32 and a second semiconductor layer 33 are sequentially grown in the groove 220 to obtain a light emitting structure 30 .
[0151] The first semiconductor layer 31 and the third semiconductor layer 23 have the same conductivity type.
[0152] Exemplarily, the first semiconductor layer 31 is an n-type AlGaN layer, and the third semiconductor layer 23 may be an n-type GaN layer.
[0153] In the disclosed embodiment, the groove 220 formed by etching exposes the n-type GaN layer, and the side wall of the channel layer 21 thus exposed is directly connected to the subsequently grown n-type AlGaN layer, thereby eliminating the need to set up a metal connection structure and directly reducing the related losses caused by the metal connection. At the same time, the regrown n-type AlGaN layer can also well repair the side wall of the channel layer 21 damaged by etching, reducing the performance loss caused by it.
[0154] Step 7: Figure 6 As shown, the mask layer is removed, a source electrode 41 and a gate electrode 43 are formed on the surface of the barrier layer 22 , and a drain electrode 42 is formed on the surface of the second semiconductor layer 33 .
[0155] Specifically, the process may include: wet etching the mask layer and the epitaxial part outside the groove 220 attached thereto, using photoresist to protect the required light emitting structure 30, and then etching the required Mesa pattern. After obtaining the Mesa pattern, the source 41, the drain 42 and the gate 43 are sequentially deposited step by step according to the designed structure.
[0156] While the electrodes are being manufactured, if a current spreading layer needs to be additionally prepared above the light emitting structure 30 , the current spreading layer can also be deposited and prepared in this step.
[0157] Step 8: Figure 6 As shown, a passivation layer is formed on the surface of the barrier layer 22 and the surface of the second semiconductor layer 33 , and a first pad 51 , a second pad 52 and a third pad 53 are formed on the surface of the passivation layer.
[0158] It should be noted that in the case where a second reflective layer 34 is required to be provided above the light-emitting structure 30, material layers with different refractive indexes can be used here, for example, silicon oxide layers and silicon nitride layers are evaporated to form a periodic structure with a specific film thickness, thereby forming a suitable distributed Bragg reflector above the light-emitting area of the light-emitting structure 30.
[0159] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.
Claims
1. An integrated device, characterized in that: The integrated device comprises: a channel layer (21), a barrier layer (22), a light emitting structure (30), a gate (43), a drain (42) and a source (41); The channel layer (21) and the barrier layer (22) are stacked in sequence, the barrier layer (22) has a groove (220) exposing the channel layer (21), the light-emitting structure (30) is located in the groove (220), and the light-emitting structure (30) comprises a first semiconductor layer (31), a multi-quantum well layer (32), and a second semiconductor layer (33) stacked in sequence in the groove (220), the first semiconductor layer (31) is electrically connected to the channel layer (21), and the second semiconductor layer (33) is insulated from the channel layer (21); The source electrode (41) and the gate electrode (43) are both located on a side of the barrier layer (22) away from the channel layer (21); the source electrode (41) is electrically connected to the channel layer (21) via a through hole; and the drain electrode (42) is located on a surface of the second semiconductor layer (33) and is electrically connected to the second semiconductor layer (33).
2. The integrated device according to claim 1, characterized in that: The groove (220) at least extends into the channel layer (21), the side wall of the first semiconductor layer (31) is electrically connected to the side wall of the channel layer (21) exposed by the groove (220), and the depth of the portion of the groove (220) located in the channel layer (21) is less than or equal to the thickness of the first semiconductor layer (31).
3. The integrated device according to claim 2, characterized in that: The integrated device further comprises a third semiconductor layer (23), wherein the third semiconductor layer (23), the channel layer (21) and the barrier layer (22) are stacked in sequence, and the conductivity type of the third semiconductor layer (23) is the same as the conductivity type of the first semiconductor layer (31); The groove (220) extends into the third semiconductor layer (23), the first semiconductor layer (31) is located on the surface of the third semiconductor layer (23) exposed in the groove (220), and the first semiconductor layer (31) is electrically connected to the third semiconductor layer (23); The depth of a portion of the groove (220) located in the channel layer (21) and the third semiconductor layer (23) is less than or equal to the thickness of the first semiconductor layer (31).
4. The integrated device according to any one of claims 1 to 3, characterized in that: The integrated device further comprises a first reflective layer (24), wherein the first reflective layer (24) is located on a side of the channel layer (21) away from the barrier layer (22); The first reflective layer (24) comprises a plurality of first material layers (241) and a plurality of second material layers (242) which are alternately stacked, and the first material layers (241) and the second material layers (242) have different refractive indexes.
5. The integrated device according to claim 4, characterized in that: The first material layer (241) is an AlN layer, and the second material layer (242) is a GaN layer; or, The first material layer (241) is a GaN layer, and the second material layer (242) is a porous GaN layer.
6. The integrated device according to any one of claims 1 to 3, characterized in that: The channel layer (21) includes a GaN layer, and the barrier layer (22) includes at least one of an AlGaN layer and an AlN layer.
7. The integrated device according to any one of claims 1 to 3, characterized in that: The integrated device further comprises a second reflective layer (34), wherein the second reflective layer (34) is located on a side of the second semiconductor layer (33) away from the first semiconductor layer (31), and an orthographic projection of the groove (220) on a surface of the channel layer (21) away from the barrier layer (22) is located within an orthographic projection of the second reflective layer (34) on a surface of the channel layer (21) away from the barrier layer (22).
8. The integrated device according to any one of claims 1 to 3, characterized in that: The width of the groove (220) is 1 μm to 100 μm.
9. The integrated device according to any one of claims 1 to 3, characterized in that: The integrated device further comprises: a passivation layer (60), a first pad (51), a second pad (52) and a third pad (53); the passivation layer (60) is located on a surface of the barrier layer (22) away from the channel layer (21) and on a surface of the second semiconductor layer (33), and covers the source electrode (41), the gate electrode (43) and the drain electrode (42); The passivation layer (60) has through holes respectively exposing the source electrode (41), the gate electrode (43) and the drain electrode (42); the first pad (51), the second pad (52) and the third pad (53) are all located on a surface of the passivation layer (60) away from the second semiconductor layer (33); the first pad (51) is connected to the source electrode (41) through the through hole, the second pad (52) is connected to the gate electrode (43) through the through hole, and the third pad (53) is connected to the drain electrode (42) through the through hole.
10. A method for preparing an integrated device, characterized in that: The preparation method comprises: providing a substrate; forming a channel layer and a barrier layer on the substrate in sequence, wherein the barrier layer has a groove exposing the channel layer; forming a light-emitting structure in the groove, the light-emitting structure comprising a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer sequentially stacked in the groove, the first semiconductor layer being electrically connected to the channel layer, and the second semiconductor layer being insulated from the channel layer; A source electrode and a gate electrode are formed on a side of the barrier layer away from the channel layer, wherein the source electrode is electrically connected to the channel layer through a through hole; A drain electrode is formed on the surface of the second semiconductor layer, and the drain electrode is electrically connected to the second semiconductor layer.