Array substrate and manufacturing method of array substrate

Abstract

The invention discloses an array substrate and a manufacturing method of the array substrate. The array substrate comprises a display area and a non-display area, and the non-display area is at least arranged on one side of the display area; the substrate comprises a first surface and a second surface which are oppositely arranged, and a side surface connected with the first surface and the second surface; the driving circuit layer is arranged on the first surface, the driving circuit layer comprises a signal layer, and the signal layer extends from the display area to the non-display area; the bonding pad layer is arranged in the display area, the bonding pad layer comprises at least one bonding pad, and the bonding pad is electrically connected with the signal layer. By arranging the bonding pad layer in the display area, the bonding pad layer can be prevented from forming a stacked structure with the signal layer in the non-display area, and the thickness of the stacked structure is reduced, so that residual organic substances near the stacked structure are reduced, the bad probability of short circuit caused by the residual organic substances is reduced, and the reliability of the display panel is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of display, and in particular to an array substrate and a method for manufacturing the array substrate. Background Art

[0002] Micro Light Emitting Diode (Micro-LED / Mini-LED) display technology has become one of the hot spots in the development of future display technology because of its characteristics such as independent control of the picture, independent light control, high brightness, low power consumption, ultra-high resolution and high color.

[0003] Current Micro-LED / Mini-LED display panels can set up circuits on the back and use side routing to connect the circuits on the back with the circuits on the front to reduce the border of the Micro-LED / Mini-LED display panel. Summary of the invention

[0004] The invention provides an array substrate and a method for manufacturing the array substrate, so as to improve the reliability of the array substrate.

[0005] In a first aspect, an embodiment of the present invention provides an array substrate, comprising a display area and a non-display area, wherein the non-display area is at least arranged on one side of the display area; the array substrate further comprises:

[0006] A substrate, the substrate comprising a first surface and a second surface arranged opposite to each other, and a side surface connected to the first surface and the second surface;

[0007] A driving circuit layer, disposed on the first surface, the driving circuit layer comprising a signal layer, and the signal layer extends from the display area to the non-display area;

[0008] The pad layer is arranged in the display area, and the pad layer includes at least one pad, and the pad is electrically connected to the signal layer.

[0009] Optionally, the array substrate further includes side wiring and a circuit layer arranged on the second surface;

[0010] The side routing is arranged on the side of the substrate, one end of the side routing is connected to the signal layer, and the other end is connected to the circuit layer.

[0011] Optionally, the signal layer in the non-display area extends to the edge of the first surface, and one end of the side wiring overlaps with the surface of the signal layer; or,

[0012] A certain distance is reserved between the signal layer in the non-display area and the edge of the first surface, and one end of the side wiring extends along the first surface and overlaps with the surface of the signal layer.

[0013] Optionally, the signal layer includes a first signal layer and a second signal layer; in the non-display area, the first signal layer covers the second signal layer; one end of the side wiring at least covers a portion of the surface of the first signal layer; or,

[0014] In the non-display area, the first signal layer at most covers a portion of the second signal layer; one end of the side wiring at least covers a portion of the surface of the first signal layer and / or a portion of the second signal layer.

[0015] Optionally, the driving circuit layer further includes a first insulating layer, and the first insulating layer is arranged in the display area and located between the first signal layer and the second signal layer.

[0016] Optionally, the circuit layer in the non-display area extends to the edge of the second surface, and the other end of the side wiring overlaps with the surface of the circuit layer; or,

[0017] A certain distance is reserved between the circuit layer in the non-display area and the edge of the second surface, and the other end of the side wiring extends along the second surface and overlaps with the surface of the circuit layer.

[0018] Optionally, the circuit layer includes at least a first sub-circuit layer and a second sub-circuit layer; in the non-display area, the first sub-circuit layer covers the second sub-circuit layer, and the other end of the side wiring at least covers a portion of the surface of the first sub-circuit layer; or,

[0019] In the non-display area, the first sub-circuit layer at most covers a portion of the second sub-circuit layer, and one end of the side wiring at least covers a portion of the surface of the second sub-circuit layer.

[0020] Optionally, the array substrate further includes a second insulating layer, wherein the second insulating layer is disposed on the driving circuit layer, and the second insulating layer covers the signal layer of the display area.

[0021] In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, wherein the array substrate comprises a display area and a non-display area, wherein the non-display area is at least arranged on one side of the display area, and the method comprises:

[0022] Forming a driving circuit layer on the first surface of the substrate, the driving circuit layer comprising a signal layer, and the signal layer extends from the display area to the non-display area;

[0023] A pad layer is formed on a side of the driving circuit layer away from the substrate; the pad layer is arranged in the display area, the pad layer includes at least one pad, and the pad is electrically connected to the signal layer.

[0024] Optionally, forming a pad layer on a side of the driving circuit layer away from the substrate includes:

[0025] forming an initial pad layer on a side of the driving circuit layer away from the substrate; the initial pad layer covers the display area and the non-display area;

[0026] The initial pad layer is patterned to form the pad layer.

[0027] The technical solution of the embodiment of the present invention, by setting the pad layer in the display area, can avoid the pad layer from forming a stacked structure with the signal layer in the non-display area, thereby reducing the thickness of the stacked structure, thereby reducing the residual organic substances near the stacked structure, reducing the probability of circuit short circuit caused by the residual organic substances, and improving the reliability of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0029] Figure 2 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0030] Figure 3 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0031] Figure 4 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0032] Figure 5 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0033] Figure 6 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0034] Figure 7 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0035] Figure 8 A schematic structural diagram of another array substrate provided by an embodiment of the present invention;

[0036] Fig. 9 A schematic flow chart of a method for manufacturing an array substrate provided in an embodiment of the present invention;

[0037] Fig.10 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to step S10 provided in an embodiment of the present invention;

[0038] Fig.11 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to step S10 provided in an embodiment of the present invention;

[0039] Fig.12 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to step S11 provided in an embodiment of the present invention;

[0040] Fig.13 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to step S11 provided in an embodiment of the present invention;

[0041] Fig.14 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to forming a second insulating layer provided by an embodiment of the present invention;

[0042] Fig.15 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to forming a second insulating layer provided by an embodiment of the present invention;

[0043] Fig.16 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to forming an initial pad layer provided by an embodiment of the present invention;

[0044] Fig.17 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to forming an initial pad layer provided by an embodiment of the present invention;

[0045] Fig.18 A schematic diagram of a front cross-sectional structure of a non-display area of ​​an array substrate corresponding to a patterned initial pad layer provided in an embodiment of the present invention;

[0046] Fig.19 A schematic diagram of a side cross-sectional structure of a non-display area of ​​an array substrate corresponding to a patterned initial pad layer provided in an embodiment of the present invention;

[0047] Fig. 20 A structural schematic diagram of an array substrate corresponding to a development process when a test pad is removed after forming a pad provided in the related art;

[0048] Fig.21 A schematic diagram of the structure of an array substrate corresponding to the formation of a pad and the removal of a test pad provided in the related art;

[0049] Fig. 22 A schematic structural diagram of an array substrate with a patterned protective layer provided by an embodiment of the present invention;

[0050] Fig.23A schematic diagram of the structure of an array substrate after removing the pad layer in the non-display area provided by an embodiment of the present invention;

[0051] Fig.24 A schematic diagram of the structure of an array substrate after removing the second insulating layer in the non-display area provided by an embodiment of the present invention;

[0052] Fig.25 A schematic diagram of the structure of an array substrate after the protective layer of the display area is peeled off according to an embodiment of the present invention;

[0053] Fig.26 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0055] In the related art, the Micro-LED / Mini-LED display panel includes a thick copper layer, which is used to form a pad and is connected to the electrode of the Micro-LED / Mini-LED to provide a driving signal for the Micro-LED / Mini-LED. In the process of manufacturing the Micro-LED / Mini-LED display panel, it is necessary to retain the thick copper layer in the non-display area to avoid damaging other conductive film layers when patterning the thick copper layer. At this time, the signal line in the display area is connected to the side wiring through the thick copper layer in the non-display area. Since the thickness of the stacked structure formed by the thick copper layer in the non-display area and the signal line is relatively large, when the organic substances in the etching process are removed after the thick copper layer is patterned, it is easy to have residues between the stacked structures. When the side wiring is formed by the laser cutting process, the residual organic substances are easy to cause short circuits to form poor lines, reducing the reliability of the display panel. Figure 1 FIG. 1 is a schematic diagram of the structure of an array substrate provided by an embodiment of the present invention. Figure 1 As shown, the array substrate includes a display area 101 and a non-display area 102, and the non-display area 102 is at least arranged on one side of the display area 101; the array substrate also includes:

[0056] A substrate 110, the substrate 110 includes a first surface 111 and a second surface 112 that are opposite to each other, and a side surface 113 that is connected to the first surface 111 and the second surface 112;

[0057] The driving circuit layer 120 is disposed on the first surface 111 . The driving circuit layer 120 includes a signal layer 121 . The signal layer 121 extends from the display area 101 to the non-display area 102 .

[0058] The pad layer 130 is disposed in the display area 101 . The pad layer 130 includes at least one pad 131 . The pad 131 is electrically connected to the signal layer 121 .

[0059] Specifically, the substrate 110 is used to carry the driving circuit layer 120. Exemplarily, the material of the substrate 110 can be glass or polyimide (PI). The driving circuit layer 120 may include an active layer, a multi-layer conductive layer and a multi-layer insulating layer, which are used to form transistors, capacitors and connecting lines in the pixel driving circuit. And a signal layer 121, the signal layer 121 includes a signal line, and the signal line can provide a driving signal for the pixel driving circuit. The signal line on the signal layer 121 extends from the display area 101 to the non-display area 102, and is connected to the driving chip to receive the driving signal provided by the driving chip. Exemplarily, the signal line of the signal layer 121 may include a first power signal line, a second power signal line and a data signal line. The array substrate may also include side routing, the driving chip may be arranged on the back of the array substrate, and the signal line of the signal layer 121 may be connected to the driving chip through the side routing to reduce the side frame of the array substrate. Among them, the first power signal line, the second power signal line and the data signal line can be respectively provided with one or more as needed. The pad layer 130 is arranged in the display area 101, and the pad layer 130 includes at least one pad 131, and is electrically connected to the signal layer 121, and can receive the driving signal provided by the signal line of the signal layer 121. At the same time, the pad 131 can be connected to the light-emitting device to provide a driving current for the light-emitting device so that the light-emitting device emits light. Moreover, the pad layer 130 is only arranged in the display area 101, avoiding the formation of a stacking structure with the signal layer 121 in the non-display area 102, reducing the thickness of the stacking structure, thereby reducing the residual organic substances near the stacking structure, reducing the probability of a short circuit caused by the residual organic substances, and improving the reliability of the display panel. Exemplarily, when the pad 131 is formed on the pad layer 130, the pad layer 130 can be patterned by a photolithography process to form the pad 131. At this time, it is necessary to cover the non-pad area of ​​the pad layer 130 with a photoresist so that there is a residual photoresist near the stacking structure. The pad layer 130 is only arranged in the display area 101, which can reduce the thickness of the stacking structure in the non-display area. The smaller the thickness of the stacking structure, the less residual photoresist is near the stacking structure. In the subsequent process, the probability of circuit short circuit caused by carbonization of the photoresist can be reduced, thereby improving the reliability of the display panel.

[0060] The technical solution of this embodiment, by arranging the pad layer in the display area, can avoid the pad layer from forming a stacked structure with the signal layer in the non-display area, thereby reducing the thickness of the stacked structure, thereby reducing the residual organic substances near the stacked structure, reducing the probability of circuit short circuit caused by the residual organic substances, and improving the reliability of the display panel.

[0061] Figure 2 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 2 As shown, the array substrate also includes a side trace 140 and a circuit layer 150 disposed on the second surface 112 ; the side trace 140 is disposed on the side 113 of the substrate 110 , one end of the side trace 140 is connected to the signal layer 121 , and the other end is connected to the circuit layer 150 .

[0062] Specifically, the side wiring 140 can be arranged corresponding to the signal layer 121, and one end is connected to the signal line of the signal layer 121, and the other end is connected to the circuit layer 150, so that the circuit layer 150 is electrically connected to the signal layer 121 through the side wiring 140. The circuit layer 150 is arranged on the second surface 112, and can be connected to the driver chip to provide a driving signal for the signal layer 121. By setting the side wiring 140 and the circuit layer 150, the driver chip can be arranged on the second surface 112, which is conducive to reducing the frame of the array substrate. The side wiring 140 can be formed by a laser cutting process. After the pad 131 is formed on the pad layer 130, a side wiring layer can be formed in the non-display area 102, and overlapped with the stacked structure formed by the signal layer 121, and then the side wiring layer is cut by a laser cutting process to form the side wiring 140. Since the thickness of the stacked structure is relatively small, when the organic substance is removed during the formation of the solder pad 131, relatively little organic substance remains near the stacked structure. The carbonization of the organic substance can be reduced during laser cutting of the side wiring layer, thereby reducing the probability of short circuits caused by residual organic substances and improving the reliability of the display panel.

[0063] Continue to refer Figure 2 The signal layer 121 of the non-display area 102 extends to the edge of the first surface 111 , and one end of the side wiring 140 overlaps the surface of the signal layer 121 .

[0064] Specifically, Figure 2 As shown, when the signal layer 121 of the non-display area 102 extends to the edge of the first surface 111, the signal line of the signal layer 121 extends to the edge of the first surface 111. At this time, the side wiring 140 can overlap the signal layer 121 at the edge of the first surface 111 to achieve electrical connection between the side wiring 140 and the signal layer 121.

[0065] Figure 3FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 3 As shown, in other embodiments, a certain distance is reserved between the signal layer 121 of the non-display area 102 and the edge of the first surface 111 , and one end of the side trace 140 extends along the first surface 111 and overlaps the surface of the signal layer 121 .

[0066] Specifically, Figure 2 The difference is that in Figure 3 In the embodiment, when the signal layer 121 extends along the first surface 111, the edge of the signal layer 121 is at a certain distance from the edge of the first surface 111, that is, the signal line of the signal layer 121 is at a certain distance from the edge of the first surface 111 at one end of the non-display area 102. At this time, the side wiring 140 can extend on the first surface 111, so that the side wiring 140 and the signal layer 121 overlap on the first surface 111 to achieve electrical connection between the side wiring 140 and the signal layer 121.

[0067] It should be noted that the distance between the signal layer 121 in the non-display area 102 and the edge of the first surface 111 can be set as required and is not limited here.

[0068] Figure 4 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 4 As shown, the signal layer 121 includes a first signal layer 1211 and a second signal layer 1212 ; in the non-display area 102 , the first signal layer 1211 covers the second signal layer 1212 ; one end of the side wiring 140 at least covers a portion of the surface of the first signal layer 1211 .

[0069] Specifically, the signal layer 121 may include a plurality of signal lines for transmitting different drive signals. Exemplarily, the signal lines may include a first power signal line, a second power signal line, and a data signal line. Different signal lines may be respectively arranged in the first signal layer 1211 and the second signal layer 1212, which is conducive to simplifying the arrangement of the signal lines when the number of signal lines is relatively large. Alternatively, different signal lines may be arranged in the same signal layer, while another signal layer is used to set jumpers of signal lines of different directions at overlapping positions to avoid short circuits of signal lines of different directions. Exemplarily, the first signal layer 1211 is used to set signal lines of different directions, and the second signal layer 1212 is used to set jumpers of signal lines of different directions at overlapping positions. In the non-display area 102, when the first signal layer 1211 covers the second signal layer 1212, the surface of the signal layer 121 away from the substrate 110 is the surface of the first signal layer 1211. At this time, one end of the side wiring 140 is set to cover at least part of the surface of the first signal layer 1211, so that the side wiring 140 and the signal layer 121 can be overlapped, and the connection reliability between the side wiring 140 and the signal layer 121 can be ensured. For example, Figure 4 As shown, one end of the side wiring 140 covers the surface of the first signal layer 1211 , which can further ensure the connection reliability between the side wiring 140 and the signal layer 121 .

[0070] It should be noted that Figure 4 exemplarily shows a situation where the first signal layer 1211 covers the second signal layer 1212 when a certain distance is reserved between the signal layer 121 of the non-display area 102 and the edge of the first surface 111. In other embodiments, it can also be arranged that when the signal layer 121 of the non-display area 102 extends to the edge of the first surface 111, the first signal layer 1211 covers the second signal layer 1212, which is not limited here.

[0071] Figure 5 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 5 As shown, in other embodiments, the signal layer 121 includes a first signal layer 1211 and a second signal layer 1212; in the non-display area 102, the first signal layer 1211 at most covers a portion of the second signal layer 1212; one end of the side routing 140 at least covers a portion of the surface of the first signal layer 1211 and / or a portion of the second signal layer 1212.

[0072] Specifically, in the non-display area 102, when the first signal layer 1211 covers at most a portion of the second signal layer 1212, the surface of the signal layer 121 away from the substrate 110 includes the surface of the first signal layer 1211 and the surface of the second signal layer 1212 not covered by the first signal layer 1211. In this case, the side wiring 140 can at least cover a portion of the surface of the first signal layer 1211 and / or a portion of the second signal layer 1212, and the side wiring 140 can be electrically connected to the signal layer 121. For example, Figure 5 As shown, the side trace 140 can cover the surface of the first signal layer 1211 and the surface of the second signal layer 1212 not covered by the first signal layer 1211 , thereby ensuring the connection reliability between the side trace 140 and the signal layer 121 .

[0073] It should be noted that Figure 5 exemplarily shows that the signal layer 121 of the non-display area 102 extends to the edge of the first surface 111. In other embodiments, when a certain distance is reserved between the signal layer 121 of the non-display area 102 and the edge of the first surface 111, the first signal layer 1211 at most covers a portion of the second signal layer 1212, which is not limited here. In addition, Figure 5exemplarily shows a technical solution in which the first signal layer 1211 covers part of the second signal layer 1212. In other embodiments, in the non-display area 102, the vertical projections of the first signal layer 1211 and the second signal layer 1212 on the substrate 110 may not overlap but contact, so as to realize electrical connection between the first signal layer 1211 and the second signal layer 1212.

[0074] in addition, Figure 5 The technical solution in which the side routing 140 covers the surface of the first signal layer 1211 and the second signal layer 1212 is exemplarily shown. In other embodiments, a technical solution in which the side routing 140 covers at least part of the surface of the first signal layer 1211 or part of the surface of the second signal layer 1212 can also be provided, and the overlap between the side routing 140 and the signal layer 121 can also be achieved, which is not limited here.

[0075] Continue to refer Figure 5 The driving circuit layer 120 further includes a first insulating layer 122 . The first insulating layer 122 is disposed in the display area 101 and is located between the first signal layer 1211 and the second signal layer 1212 .

[0076] Specifically, in the display area 101, a first insulating layer 122 is provided between the first signal layer 1211 and the second signal layer 1212 to achieve insulation between the first signal layer 1211 and the second signal layer 1212. At the same time, vias can be provided on the first insulating layer 122 to achieve electrical connection between the first signal layer 1211 and the second signal layer 1212. The first insulating layer 122 can be an inorganic insulating layer, and the first insulating layer 122 is only provided in the display area 101, which can reduce the thickness of the inorganic film layer in the non-display area 102, avoid the first insulating layer 122 from remaining in the non-display area 102, and reduce the risk of short circuit of the signal line and the side wiring 140 in the non-display area 102.

[0077] Continue to refer Figure 5 The circuit layer 150 of the non-display area 102 extends to the edge of the second surface 112 , and the other end of the side trace 140 overlaps with the surface of the circuit layer 150 .

[0078] Specifically, the circuit layer 150 includes circuits, and is arranged corresponding to the side wiring 140, that is, the circuits of the circuit layer 150 are arranged corresponding to the signal lines of the signal layer 121, and overlap with the side wiring 140, so that they are connected to the signal layer 121 through the side wiring 140, so that the circuits of the circuit layer 150 can provide driving signals to the signal lines of the signal layer 121 through the side wiring 140. In addition, the other end of the circuit layer 150 can be connected to the driving chip to obtain the driving signal. Figure 5As shown, when the circuit layer 150 of the non-display area 102 extends to the edge of the second surface 112 , the side trace 140 can overlap with the circuit layer 150 at the edge of the second surface 112 to achieve electrical connection between the other end of the side trace 140 and the circuit layer 150 .

[0079] Figure 6 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 6 As shown, in other embodiments, a certain distance is reserved between the circuit layer 150 of the non-display area 102 and the edge of the second surface 112 , and the other end of the side trace 140 extends along the second surface 112 to overlap the surface of the circuit layer 150 .

[0080] Specifically, Figure 5 The difference is that in Figure 6 In the embodiment, when the circuit layer 150 extends along the second surface 112, the edge of the circuit layer 150 is at a certain distance from the edge of the second surface 112, that is, the circuit of the circuit layer 150 is at a certain distance from the edge of the second surface 112 at one end of the non-display area 102. At this time, the side wiring 140 can extend on the second surface 111, so that the side wiring 140 and the circuit layer 150 overlap on the second surface 112 to achieve electrical connection between the side wiring 140 and the circuit layer 150.

[0081] Figure 7 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 7 As shown, the circuit layer 150 includes at least a first sub-circuit layer 151 and a second sub-circuit layer 152 ; in the non-display area 102 , the first sub-circuit layer 151 covers the second sub-circuit layer 152 , and the other end of the side trace 140 at least covers a portion of the surface of the first sub-circuit layer 151 .

[0082] Specifically, the circuit layer 150 includes a plurality of circuits, which are respectively arranged corresponding to the signal lines of the signal layer 121 through the side routing 140, and are used to provide different driving signals for the signal lines. Exemplarily, when the signal line includes a first power signal line, a second power signal line and a data signal line, the circuit layer 150 includes a first circuit, a second circuit and a third circuit, which are respectively connected to the first power signal line, the second power signal line and the data signal line, and provide driving signals for the first power signal line, the second power signal line and the data signal line. The circuit layer 150 may include a first sub-circuit layer 151 and a second sub-circuit layer 152, and a plurality of circuits may be respectively arranged in the first sub-circuit layer 151 and the second sub-circuit layer 152, which is conducive to simplifying the arrangement of the circuits when the number of circuits is relatively large. Alternatively, when different circuits have different directions, different circuits may be arranged in the same sub-circuit layer, and at the same time, another sub-circuit layer may be provided with jumpers of circuits of different directions at overlapping positions to avoid short circuits of circuits of different directions. Exemplarily, the first sub-circuit layer 151 is used to set circuits with different directions, and the second sub-circuit layer 152 is used to set jumpers at overlapping positions of circuits with different directions. In the non-display area 102, when the first sub-circuit layer 151 covers the second sub-circuit layer 152, the surface of the circuit layer 150 away from the substrate 110 is the surface of the first sub-circuit layer 151. At this time, the other end of the side wiring 140 is set to cover at least part of the surface of the first sub-circuit layer 151, so that the side wiring 140 and the circuit layer 150 can be overlapped, and the connection reliability between the side wiring 140 and the circuit layer 150 can be ensured. Exemplarily, as Figure 7 As shown, the other end of the side wiring 140 covers the surface of the first sub-circuit layer 151 , which can further ensure the connection reliability between the side wiring 140 and the circuit layer 150 .

[0083] It should be noted that Figure 7 The example shows that the first sub-circuit layer 151 covers the second sub-circuit layer 152 when the circuit layer 150 of the non-display area 102 extends to the edge of the second surface 112. In other embodiments, it can also be arranged that when a certain distance is reserved between the circuit layer 150 of the non-display area 102 and the edge of the second surface 112, the first sub-circuit layer 151 covers the second sub-circuit layer 152, which is not limited here.

[0084] Figure 8 FIG. 1 is a schematic diagram of the structure of another array substrate provided by an embodiment of the present invention. Figure 8 As shown, the circuit layer 150 includes at least a first sub-circuit layer 151 and a second sub-circuit layer 152; in the non-display area 102, the first sub-circuit layer 151 at most covers a portion of the second sub-circuit layer 152, and one end of the side wiring 140 at least covers a portion of the surface of the second sub-circuit layer 152.

[0085] Specifically, in the non-display area 102, when the first sub-circuit layer 151 covers at most a portion of the second sub-circuit layer 152, the surface of the circuit layer 150 away from the substrate 110 includes the surface of the first sub-circuit layer 151 and the surface of the second sub-circuit layer 152 not covered by the first sub-circuit layer 151. In this case, the side wiring 140 can at least cover a portion of the surface of the second sub-circuit layer 152, and the electrical connection between the side wiring 140 and the circuit layer 150 can be achieved. For example, Figure 8 As shown, the side routing 140 can cover the surface of the first sub-circuit layer 151 and the surface of the second sub-circuit layer 152 not covered by the first sub-circuit layer 151, which can ensure the connection reliability between the side routing 140 and the circuit layer 150.

[0086] It should be noted that Figure 8 exemplarily shows a technical solution in which the first sub-circuit layer 151 covers part of the second sub-circuit layer 152. In other embodiments, in the non-display area 102, it is also possible to set the vertical projections of the first sub-circuit layer 151 and the second sub-circuit layer 152 on the substrate 110 not to overlap but to contact, so as to achieve electrical connection between the first sub-circuit layer 151 and the second sub-circuit layer 152.

[0087] in addition, Figure 8 The technical solution in which the side wiring 140 covers the surface of the first sub-circuit layer 151 and the second sub-circuit layer 152 is exemplarily shown. In other embodiments, a technical solution in which the side wiring 140 covers at least part of the surface of the second sub-circuit layer 152 can also be set, and the overlap between the side wiring 140 and the circuit layer 150 can also be achieved, which is not limited here.

[0088] Continue to refer Figure 8 The array substrate further includes a second insulating layer 160 , which is disposed on the driving circuit layer 120 , and covers the signal layer 121 of the display area 101 .

[0089] Specifically, in the display area 101, the second insulating layer 160 is disposed between the signal layer 121 and the pad layer 130 to achieve insulation between the signal layer 121 and the pad layer 130. At the same time, a via hole can be provided on the second insulating layer 160 to achieve electrical connection between the signal layer 121 and the pad layer 130. When forming the second insulating layer 160, the entire second insulating layer 160 can be first formed in the display area 101 and the non-display area 102, and then the pad layer 130 is formed on the second insulating layer 160, and the pad layer 130 is patterned so that the pad layer 130 is only disposed in the display area 101. Then, the entire second insulating layer 160 is patterned so that the second insulating layer 160 is only disposed in the display area 101 and covers the signal layer 121. Thereafter, the pad layer 130 is patterned to form the pad 131. When the pad layer 130 is patterned for the first time, the second insulating layer 160 in the non-display area 102 may be used as a protective layer to prevent the signal layer 121 from being lost when the pad layer 130 is patterned.

[0090] Continue to refer Figure 8 The driving circuit layer 120 also includes a pixel circuit layer 123; the pixel circuit layer 123 is arranged on the substrate 110, and the signal layer 121 is arranged on the side of the pixel circuit layer 123 away from the substrate 110; the pixel circuit layer 123 is used to form a pixel circuit, and the signal layer 121 is used to form a signal line. The signal layer 121 is connected to the pixel circuit to provide a driving signal for the pixel circuit.

[0091] Specifically, the pixel circuit layer 123 has a multi-layer structure, which is used to form transistors, capacitors and connecting lines in the pixel circuit. Exemplarily, the pixel circuit layer 123 may include an active layer, a first metal layer, a gate insulating layer, a second metal layer, an interlayer insulating layer and a third metal layer. Among them, the active layer is used to form the channel region, the source region and the drain region in the transistor; the first metal layer is used to form the gate of the transistor, the first electrode of the capacitor and the connecting line; the second metal layer is used to form the second electrode of the capacitor, and the third metal layer is used to form the source, drain and connecting line of the transistor. The signal layer 121 may include multiple conductive layers for forming signal lines. Exemplarily, as Figure 8 As shown, the signal layer 121 may include a fourth metal layer and a fifth metal layer. When the signal layer 121 includes a data signal line, a first power signal line, and a second power signal line, the fourth metal layer may be used to form the data signal line, and the fifth metal layer may be used to form the first power signal line and the second power signal line. Alternatively, the fourth metal layer may be used to form a jumper, and the fifth metal layer may be used to form a data signal line, a first power signal line, and a second power signal line. The data signal line and the first power signal line have different extension directions. At the overlapping position of the data signal line and the first power signal line, a jumper may be used to jumper the data signal line or the first power signal line to avoid overlapping and short-circuiting the data signal line and the first power signal line.

[0092] The present invention also provides a method for manufacturing an array substrate, which can be used to manufacture the array substrate provided by any embodiment of the present invention. The array substrate includes a display area 101 and a non-display area 102 , and the non-display area 102 is at least arranged on one side of the display area 101 . Fig. 9 The present invention provides a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present invention. Fig. 9 As shown, the method includes:

[0093] S10, forming a driving circuit layer on the first surface of the substrate, wherein the driving circuit layer includes a signal layer, and the signal layer extends from the display area to the non-display area;

[0094] in, Fig.10 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to step S10 provided in an embodiment of the present invention, Fig.11 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to step S10 provided in an embodiment of the present invention. Fig.10 and Fig.11 As shown, the driving circuit layer 120 is disposed on the first surface 111 of the substrate 110, and a signal layer 121 is disposed on the driving circuit layer 120, and the signal layer 121 extends from the display area 101 to the non-display area 102. The signal layer 121 has a plurality of signal lines, Fig.11 FIG. 4 exemplarily shows that the signal layer 121 has two signal lines.

[0095] S11, forming a pad layer on a side of the driving circuit layer away from the substrate; the pad layer is arranged in the display area, the pad layer includes at least one pad, and the pad is electrically connected to the signal layer.

[0096] Specifically, Fig.12 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to step S11 provided in an embodiment of the present invention, Fig.13 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to step S11 provided in an embodiment of the present invention. Fig.12 and Fig.13 As shown, when the pad layer 130 is formed, the pad layer 130 is set only in the display area 101 to avoid forming a stacking structure with the signal layer 121 in the non-display area 102, thereby reducing the thickness of the stacking structure, thereby reducing the residual organic substances near the stacking structure, reducing the probability of circuit short circuit caused by the residual organic substances, and improving the reliability of the display panel.

[0097] The technical solution of this embodiment is to form a pad layer so that the pad layer is only located in the display area, so that only the signal layer forms a stacked structure in the non-display area, thereby reducing the thickness of the stacked structure, thereby reducing the residual organic substances near the stacked structure, reducing the probability of circuit short circuit caused by the residual organic substances, and improving the reliability of the display panel.

[0098] On the basis of the above technical solution, a pad layer is formed on a side of the driving circuit layer away from the substrate, including:

[0099] An initial pad layer is formed on a side of the driving circuit layer away from the substrate; the initial pad layer covers the display area and the non-display area;

[0100] Specifically, before forming the initial pad layer, a second insulating layer may be formed on the driving circuit layer, and the second insulating layer covers the signal layer. Fig.14 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to forming a second insulating layer provided by an embodiment of the present invention, Fig.15 A schematic diagram of a side cross-sectional structure of an array substrate corresponding to a second insulating layer provided by an embodiment of the present invention. Fig.14 and Fig.15 As shown, the second insulating layer 160 is disposed on the driving circuit layer 120 and covers the signal layer 121, so that the second insulating layer can protect the signal layer 121 of the display area 101 and the non-display area 102. After forming the second insulating layer 160, an initial pad layer is formed on the second insulating layer 160, and the initial pad layer covers the display area 101 and the non-display area 102. Exemplarily, Fig.16 A schematic diagram of a front cross-sectional structure of an array substrate corresponding to forming an initial pad layer provided by an embodiment of the present invention, Fig.17 The following is a schematic diagram of a side cross-sectional structure of an array substrate corresponding to an initial pad layer provided by an embodiment of the present invention. Fig.16 and Fig.17 As shown, the initial pad layer covers the display area 101 and the non-display area 102. Exemplarily, the initial pad layer may be a thick copper layer, which is used to form the pad layer 130.

[0101] The initial pad layer is patterned to form a pad layer.

[0102] Specifically, Fig.18 A schematic diagram of a main cross-sectional structure of a non-display area of ​​an array substrate corresponding to a patterned initial pad layer provided in an embodiment of the present invention, Fig.19 The following is a schematic diagram of a side cross-sectional structure of a non-display area of ​​an array substrate corresponding to a patterned initial pad layer provided by an embodiment of the present invention. Fig.18 and Fig.19As shown, when patterning the initial pad layer, the initial pad layer of the non-display area 102 can be removed first. Then the second insulating layer 160 of the non-display area 102 is removed, so that only the signal layer 121 in the non-display area 102 forms a stacked structure, reducing the thickness of the stacked structure, thereby reducing the organic substances remaining near the stacked structure, reducing the probability of a short circuit caused by the residual organic substances, and improving the reliability of the display panel. Then the initial pad layer of the display area 101 is patterned again to form a pad 131. Among them, when the initial pad layer of the display area 101 is patterned again to form a pad 131, organic substances can be covered at the non-pad of the display area 101 and the non-display area 102 to avoid affecting the signal layer 121 when patterning the initial pad layer, thereby ensuring the reliability of the signal layer 121. At the same time, it can avoid adding a patterning process, saving the cost of making an array substrate.

[0103] in addition, Fig. 20 A structural schematic diagram of an array substrate corresponding to a development process when a test pad is removed after forming a pad is provided in the related art. Fig.21 A schematic diagram of the structure of an array substrate corresponding to the formation of a pad and the removal of a test pad is provided for the related art. Fig. 20 and Fig.21 As shown, when the pad layer 130 is patterned to form the pad 131 in the display area 101, a test pad ( Fig. 20 and Fig.21 The pad layer 130 is patterned again after the test to remove the test pads in the non-display area 102. The specific process can be as follows: Fig. 20 and Fig.21 As shown, the test pad is first exposed by a developing process, then the test pad is removed by etching, and finally the organic glue 180 is peeled off. Based on the patterning process for removing the test pad in the related art. This embodiment utilizes the patterning process for removing the test pad in the related art to pattern the pad layer of the display area to form the pad, which can avoid the additional patterning process and save the cost of manufacturing the array substrate.

[0104] On the basis of the above technical solutions, when removing the initial pad layer of the non-display area, the following steps may be included:

[0105] A protection layer is formed on the pad layer.

[0106] The protective layer may be an organic glue, which can be used as a mask for later patterning of a pad layer after the organic glue is patterned.

[0107] The protective layer is patterned to remove the protective layer in the non-display area.

[0108] The protective layer may be patterned using a development process. Fig. 22 The schematic diagram of the structure of an array substrate after a patterned protective layer is provided in an embodiment of the present invention. Fig. 22 As shown, after the protective layer 170 is patterned, the protective layer 170 in the display area 101 is used to protect the pad layer 130 , and the pad layer 130 in the non-display area 102 is exposed.

[0109] The pad layer is etched to remove the pad layer in the non-display area.

[0110] in, Fig.23 The structure diagram of an array substrate after removing the pad layer in the non-display area provided by an embodiment of the present invention is shown in FIG. Fig.23 As shown, after etching the pad layer 130, only the second insulating layer 160 and the signal layer 121 are left in the non-display area 102. At this time, a protective layer 170 is also provided on the pad layer 130 of the display area 101 to prevent the subsequent etching of the second insulating layer 160 from affecting the lower film structure in the display area 101.

[0111] On the basis of the above technical solutions, when removing the second insulating layer in the non-display area, the method may include:

[0112] Etching the second insulating layer to remove the second insulating layer in the non-display area;

[0113] in, Fig.24 The structure diagram of an array substrate after removing the second insulating layer of the non-display area provided by an embodiment of the present invention is shown in FIG. Fig.24 As shown, after etching the pad layer 130, the protective layer 170 can protect the pad layer 130 of the display area 101. When etching the second insulating layer, etching can be performed directly to avoid setting up an additional protective layer for protecting the film layer of the display area 101, thereby simplifying the process flow.

[0114] Preferably, a dry etching process is used when etching the insulating layer.

[0115] Peeling off the protective layer of the display area;

[0116] in, Fig.25 The structure diagram of an array substrate after the protective layer of the display area is peeled off according to an embodiment of the present invention. Fig.25 As shown, after etching the second insulating layer 160 , the protective layer of the display area 101 is peeled off so as to subsequently pattern the pad layer 130 of the display area 101 .

[0117] On the basis of the above technical solutions, the pad layer further includes a test pad located in the non-display area.

[0118] Specifically, the pad layer can simultaneously form a test pad in the non-display area for connecting the test signal to the array substrate to test the reliability of the array substrate. After the test is completed, the pad layer is patterned again to remove the test pad in the non-display area. The specific process can be as follows Fig. 20 and Fig.21 As shown, the test pad is first exposed by a developing process, then the test pad is removed by etching, and finally the organic glue is peeled off. Based on the patterning process including removing the test pad in the related art. This embodiment, based on the above technical solutions, also includes:

[0119] Remove the test pads in the non-display area.

[0120] Among them, after patterning the pad layer to remove the pad layer of the non-display area, the patterning process of removing the test pad in the related technology is used to pattern the pad layer of the display area to form a pad, and at the same time remove the test pad of the non-display area, thereby avoiding the additional patterning process and saving the cost of manufacturing the array substrate.

[0121] On the basis of the above technical solutions, after forming the pad layer on the side of the driving circuit layer away from the substrate, a circuit layer can also be formed on the second surface of the substrate, and its specific formation process can adopt the conventional process of the relevant technology. And a side wiring is formed on the side of the substrate, which can be formed by a laser cutting process. The circuit layer can be electrically connected to the signal layer through the side wiring, and connected to the driving chip to provide a driving signal for the signal layer. An embodiment of the present invention also provides a display panel. Fig.26 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. Fig.26 As shown, the display panel 20 includes an array substrate 21 provided by any embodiment of the present invention.

[0122] Specifically, the array substrate 21 is an array substrate provided by any embodiment of the present invention. When the display panel 20 includes the array substrate provided by any embodiment of the present invention, it has the same beneficial effects as the array substrate provided by any embodiment of the present invention, which will not be described in detail here. The display panel 20 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0123] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a display area and a non-display area, wherein the non-display area is at least arranged on one side of the display area; the array substrate further comprises: A substrate, the substrate comprising a first surface and a second surface arranged opposite to each other, and a side surface connected to the first surface and the second surface; A driving circuit layer, disposed on the first surface, the driving circuit layer comprising a signal layer, and the signal layer extends from the display area to the non-display area; A pad layer, wherein the pad is arranged in the display area, the pad layer comprises at least one pad, and the pad is electrically connected to the signal layer.

2. The array substrate according to claim 1, characterized in that: It also includes side routing and a circuit layer arranged on the second surface; The side routing is arranged on the side of the substrate, one end of the side routing is connected to the signal layer, and the other end is connected to the circuit layer.

3. The array substrate according to claim 2, characterized in that: The signal layer in the non-display area extends to the edge of the first surface, and one end of the side wiring overlaps the surface of the signal layer; or, A certain distance is reserved between the signal layer in the non-display area and the edge of the first surface, and one end of the side wiring extends along the first surface and overlaps with the surface of the signal layer.

4. The array substrate according to claim 3, characterized in that: The signal layer includes a first signal layer and a second signal layer; in the non-display area, the first signal layer covers the second signal layer; one end of the side wiring at least covers a portion of the surface of the first signal layer; or, In the non-display area, the first signal layer at most covers a portion of the second signal layer; one end of the side wiring at least covers a portion of the surface of the first signal layer and / or a portion of the second signal layer.

5. The array substrate according to claim 4, characterized in that: The driving circuit layer further includes a first insulating layer, which is disposed in the display area and between the first signal layer and the second signal layer.

6. The array substrate according to claim 2, characterized in that: The circuit layer in the non-display area extends to the edge of the second surface, and the other end of the side wiring overlaps the surface of the circuit layer; or, A certain distance is reserved between the circuit layer in the non-display area and the edge of the second surface, and the other end of the side wiring extends along the second surface and overlaps with the surface of the circuit layer.

7. The array substrate according to claim 6, characterized in that: The circuit layer includes at least a first sub-circuit layer and a second sub-circuit layer; in the non-display area, the first sub-circuit layer covers the second sub-circuit layer, and the other end of the side wiring at least covers a portion of the surface of the first sub-circuit layer; or, In the non-display area, the first sub-circuit layer at most covers a portion of the second sub-circuit layer, and one end of the side wiring at least covers a portion of the surface of the second sub-circuit layer.

8. The array substrate according to claim 1, characterized in that: It also includes a second insulating layer, which is arranged on the driving circuit layer and covers the signal layer in the display area.

9. A method for manufacturing an array substrate, characterized in that: The array substrate comprises a display area and a non-display area, wherein the non-display area is at least arranged on one side of the display area, and the method comprises: Forming a driving circuit layer on the first surface of the substrate, wherein the driving circuit layer includes a signal layer, and the signal layer extends from the display area to the non-display area; A pad layer is formed on a side of the driving circuit layer away from the substrate; the pad layer is arranged in the display area, the pad layer includes at least one pad, and the pad is electrically connected to the signal layer.

10. The method for manufacturing an array substrate according to claim 9, characterized in that: A pad layer is formed on a side of the driving circuit layer away from the substrate, comprising: forming an initial pad layer on a side of the driving circuit layer away from the substrate; the initial pad layer covers the display area and the non-display area; The initial pad layer is patterned to form the pad layer.

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