Wave-by-wave current limiting circuit based on Heric circuit, control method and inverter

Abstract

The invention relates to the technical field of photovoltaic energy storage inverters, and discloses a cycle-by-cycle current limiting circuit based on a Helic circuit, a control method and an inverter, in the cycle-by-cycle current limiting circuit, an inductive current sampling signal of the Helic circuit is input into the input end of a first-stage overcurrent protection circuit, the output end of the first-stage overcurrent protection circuit is connected with the first input end of a DSP chip, and the second input end of the DSP chip is connected with the second input end of the Helic circuit; a first output end of the DSP chip is connected with a main switch tube in the Heric circuit; the input end of the secondary overcurrent protection circuit inputs an inductive current sampling signal of the Helic circuit, the output end of the secondary overcurrent protection circuit is respectively connected with the second input end of the DSP chip and the first input end of the trigger, the second output end of the DSP chip is connected with the second input end of the trigger, and the output end of the trigger is connected with a follow current switch tube in the Helic circuit. Two-stage overcurrent protection is set, the respective advantages are taken, and the respective defects are made up, so that a better wave-by-wave current limiting strategy is provided for the inverter.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic energy storage inverters, and in particular to a wave-by-wave current limiting circuit, a control method and an inverter based on a Heric circuit. Background Art

[0002] The Heric circuit is a common DC / AC topology, which is widely used in single-phase low-power photovoltaic inverters and bidirectional photovoltaic storage inverters. In photovoltaic storage inverters, the inverter needs to be able to operate off-grid, and generally needs to have a certain overload capacity and the ability to carry impact loads. Therefore, the inverter needs to have a good wave-by-wave current limiting logic and overcurrent blocking control logic to solve the problem of excessive stress on switching devices caused by overcurrent, overload, and output short circuit.

[0003] In many common DC / AC topologies, there is a wave-closing logic for wave-by-wave current limiting. When using the wave-by-wave current limiting strategy, the most commonly used solution is to use the peak inductor current for protection, which responds promptly. However, this solution has a disadvantage. When the bus voltage is very high, the ripple current of the inductor is very large, and a larger current protection threshold needs to be set. Otherwise, the current value of the wave-by-wave current limiting will be smaller than the expected value and will not reach the current value we need; when the bus voltage is low, the ripple current of the inductor is very small, and a smaller current protection threshold needs to be set. Otherwise, the current value of the wave-by-wave current limiting will be larger than the expected value and will also not reach our expected value. If the average inductor current after filtering is used as the protection value, the problem of inconsistent peak current caused by excessive voltage difference can be well solved, but the average inductor current responds too slowly as a protection value, and does not respond in time to some faults such as short circuits. Summary of the invention

[0004] In view of this, the present invention provides a wave-by-wave current limiting circuit, control method and inverter based on the Heric circuit to solve the problem that there are many defects in the current wave-by-wave current limiting strategy, whether it is using peak inductor current for protection or using average inductor current for protection.

[0005] In a first aspect, the present invention provides a wave-by-wave current limiting circuit based on the Heric circuit, the circuit comprising: a primary overcurrent protection circuit, a secondary overcurrent protection circuit, a DSP chip and a trigger, wherein:

[0006] The input end of the primary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the primary overcurrent protection circuit is connected to the first input end of the DSP chip, and the first output end of the DSP chip is connected to the main switch tube in the Heric circuit;

[0007] The input end of the secondary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the secondary overcurrent protection circuit is respectively connected to the second input end of the DSP chip and the first input end of the trigger, the second output end of the DSP chip is connected to the second input end of the trigger, and the output end of the trigger is connected to the freewheeling switch tube in the Heric circuit;

[0008] The primary overcurrent protection circuit is used to compare the processed inductor current sampling signal with the average inductor current overcurrent threshold to generate a primary overcurrent signal, and the DSP chip performs wave-by-wave current limiting on the main switch tube according to the primary overcurrent signal;

[0009] The secondary overcurrent protection circuit is used to compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal and a secondary hardware overcurrent signal. The DSP chip performs wave-by-wave current limiting on the main switch tube according to the secondary software overcurrent signal, and the trigger blocks the freewheeling switch tube according to the secondary hardware overcurrent signal.

[0010] The present invention provides a wave-by-wave current limiting circuit based on the Heric circuit, which is a two-stage overcurrent protection circuit in hardware. In the first-stage overcurrent protection circuit, the average inductor current is used for wave-by-wave current limiting to cope with the working condition with long-term impact load; in the second-stage overcurrent protection circuit, the peak inductor current is used for overcurrent protection to cope with instantaneous sudden working conditions. By setting up two-stage overcurrent protection circuits, each takes advantage of its own strengths and makes up for their own shortcomings, thereby providing a better wave-by-wave current limiting strategy for the inverter.

[0011] In an optional implementation, the primary overcurrent protection circuit includes: a low-pass filter, a first resistor, a first comparator and a second comparator, wherein:

[0012] The threshold of the non-inverting input terminal of the first comparator is the positive half-wave average inductor current over-current threshold, the inverting input terminal of the first comparator is respectively connected to the output terminal of the low-pass filter and the non-inverting input terminal of the second comparator, and the output terminal of the first comparator is respectively connected to one end of the first resistor and the output terminal of the second comparator;

[0013] The input end of the low-pass filter is connected to the inductor current sampling signal;

[0014] The threshold of the inverting input terminal of the second comparator is the negative half-wave average inductor current overcurrent threshold, and the output terminal of the second comparator is connected to the first input terminal of the DSP chip;

[0015] The other end of the first resistor is connected to an external DC power supply.

[0016] By adopting a primary overcurrent protection circuit, the inverter can adapt to long-term impact loads. And by utilizing the controllable output current of the average inductor current, the problem of unstable output current triggered by the peak current can be compensated. And when limiting the current wave by wave, the path of the inductor current is not changed, which can effectively reduce the stress of the switch tube.

[0017] In an optional implementation, the primary overcurrent protection circuit further includes: a second resistor, a third resistor, a first capacitor, a fourth resistor, a fifth resistor, and a second capacitor, wherein:

[0018] The non-inverting input terminal of the first comparator is respectively connected to one end of the second resistor, one end of the third resistor and one end of the first capacitor, the other end of the third resistor and the other end of the first capacitor are both connected to an external DC power supply, and the other end of the second resistor is grounded;

[0019] The inverting input terminal of the second comparator is respectively connected to one end of the fourth resistor, one end of the fifth resistor and one end of the second capacitor, the other end of the fourth resistor is connected to an external DC power supply, and the other end of the fifth resistor and the other end of the second capacitor are both grounded.

[0020] In an optional implementation, the secondary overcurrent protection circuit includes: a third comparator, a fourth comparator and a sixth resistor, wherein:

[0021] The threshold of the non-inverting input terminal of the third comparator is the positive half-wave peak inductor current over-current threshold, the inductor current sampling signal is respectively input into the inverting input terminal of the third comparator and the non-inverting input terminal of the fourth comparator, and the output terminal of the third comparator is respectively connected to one end of the sixth resistor and the output terminal of the fourth comparator;

[0022] The threshold of the inverting input terminal of the fourth comparator is the negative half-wave peak inductor current overcurrent threshold, and the output terminal of the fourth comparator is connected to the second input terminal of the DSP chip;

[0023] The other end of the sixth resistor is connected to an external DC power supply.

[0024] By adopting a secondary overcurrent protection circuit, the inverter can cope with instantaneous sudden working conditions. And by utilizing the fast response of the peak inductor current, the problem of slow response of the average inductor current can be compensated.

[0025] In an optional implementation, the secondary overcurrent protection circuit further includes: a fifth comparator, a first transistor, a seventh resistor and a third capacitor, wherein:

[0026] The non-inverting input terminal of the fifth comparator is connected to an external DC power supply, the inverting input terminal of the fifth comparator is connected to the output terminals of the third comparator and the fourth comparator respectively, and the output terminal of the fifth comparator is connected to one end of the seventh resistor, one end of the third capacitor and the control terminal of the first transistor respectively;

[0027] The other end of the seventh resistor and the first end of the first transistor are both connected to an external DC power supply, the second end of the first transistor and the other end of the third capacitor are both grounded, and the first end of the first transistor is also connected to the first input end of the trigger.

[0028] Compared with using DSP interrupt to delay the wave, the present invention adopts a solution combining software and hardware, which saves DSP resources, and also well controls the delay time and reduces the stress of the switch tube.

[0029] In an optional implementation, the secondary overcurrent protection circuit further includes: an eighth resistor, a ninth resistor, a fourth capacitor, a tenth resistor, an eleventh resistor and a fifth capacitor, wherein:

[0030] The non-inverting input terminal of the third comparator is respectively connected to one end of the eighth resistor, one end of the ninth resistor and one end of the fourth capacitor, the other end of the ninth resistor and the other end of the fourth capacitor are both connected to an external DC power supply, and the other end of the eighth resistor is grounded;

[0031] The inverting input terminal of the fourth comparator is respectively connected to one end of the tenth resistor, one end of the eleventh resistor and one end of the fifth capacitor, the other end of the eleventh resistor and the other end of the fifth capacitor are both grounded, and the other end of the tenth resistor is connected to an external DC power supply.

[0032] In an optional implementation, the peak inductor current overcurrent threshold is greater than the peak inductor current of the average inductor current, and the peak inductor current is the peak inductor current calculated when the bus voltage is the highest.

[0033] In a second aspect, the present invention provides a wave-by-wave current limiting control method based on a Heric circuit, based on the wave-by-wave current limiting circuit based on a Heric circuit of the first aspect or any corresponding embodiment thereof, the control method comprises:

[0034] Obtain the inductor current sampling signal in the Heric circuit;

[0035] Converting the inductor current sampling signal into an average inductor current signal, and comparing the average inductor current signal with an average inductor current overcurrent threshold to generate a primary overcurrent signal;

[0036] Compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal, and generate a secondary hardware overcurrent signal after a preset delay time, wherein the peak inductor current overcurrent threshold is greater than the average inductor current overcurrent threshold, and the peak inductor current overcurrent threshold is the peak inductor current calculated when the bus voltage is the highest;

[0037] The main switch tube is current limited wave by wave according to the secondary software overcurrent signal, and the freewheeling switch tube is blocked according to the secondary hardware overcurrent signal after a preset delay time, or the main switch tube is current limited wave by wave according to the primary overcurrent signal.

[0038] The present invention provides a wave-by-wave current limiting control method based on the Heric circuit. In the primary overcurrent protection, the average inductor current is used for wave-by-wave current limiting to cope with the working condition with long-term impact load; in the secondary overcurrent protection, the peak inductor current is used for overcurrent protection to cope with instantaneous sudden working conditions. By setting two levels of overcurrent protection, each takes advantage of its own strengths and makes up for their own shortcomings, thereby providing a better wave-by-wave current limiting strategy for the inverter.

[0039] In an optional embodiment,

[0040] According to the resistance values ​​of the second resistor and the third resistor, a positive half-wave average inductor current overcurrent threshold is set;

[0041] The negative half-wave average inductor current overcurrent threshold is set according to the resistance values ​​of the fourth resistor and the fifth resistor.

[0042] In an optional embodiment,

[0043] The delay time is set according to the resistance value of the seventh resistor and the capacitance value of the third capacitor.

[0044] In a third aspect, the present invention provides an inverter, comprising a Heric circuit and a wave-by-wave current limiting circuit based on the Heric circuit according to the first aspect or any corresponding embodiment thereof.

[0045] By setting a wave-by-wave current limiting circuit based on the Heric circuit in any of the above-mentioned embodiments in the inverter, the wave-by-wave current limiting logic and the overcurrent blocking control logic of the inverter can be optimized, thereby solving the problem of excessive stress of the switching devices caused by overcurrent, overload, and output short circuit, and improving the overload capacity and impact load carrying ability of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 is a schematic diagram of a Heric circuit according to an embodiment of the present invention;

[0048] Figure 2 is a principle block diagram of a wave-by-wave current limiting circuit based on a Heric circuit according to an embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of a primary overcurrent protection circuit according to an embodiment of the present invention;

[0050] Figure 4 is a schematic diagram of a secondary overcurrent protection circuit according to an embodiment of the present invention;

[0051] Figure 5 is a flow chart of a wave-by-wave current limiting control method based on a Heric circuit according to an embodiment of the present invention;

[0052] Figure 6 Schematic diagram of a freewheeling path of an inductor current according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0054] In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal connection of two elements, and it can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0056] Figure 1 This is a schematic diagram of the Heric circuit. Figure 1 As shown, the Heric circuit consists of an H-type inverter bridge and a freewheeling path. Among them, the four main switch tubes Q1-Q4 form an H-type inverter bridge, and the freewheeling switch tubes Q5 and Q6 form a freewheeling path. In the positive half cycle, Q1 and Q4 are turned on and are both driven by PWM1A; Q5 is normally open in the positive half cycle; Q6 is a freewheeling tube, which is complementary to Q1 and Q4 and driven by PWM1B. In the negative half cycle, Q2 and Q3 are turned on and are both driven by PWM2A; Q6 is normally open in the negative half cycle; Q5 is a freewheeling tube, which is complementary to Q2 and Q3 and driven by PWM2B. The role of Q5 and Q6 is to provide a freewheeling channel in the freewheeling stage so that the main switch tubes Q1-Q4 can be completely turned off to isolate the connection between the photovoltaic components and the grid. In order to protect the inverter, it is usually necessary to implement current limiting protection on the output current. Common protection methods include wave-by-wave current limiting protection and other methods. Taking the current wave-by-wave current limiting method as an example, when the peak inductor current is used for overcurrent protection, although the response is timely, when the input-output voltage difference is large, the output current is very different from the expected value when the peak inductor current is used for wave-by-wave current limiting. When the average inductor current after filtering is used for overcurrent protection, the problem of inconsistent peak current caused by excessive voltage difference can be well solved. However, the average inductor current is too slow to respond when performing overcurrent protection, and it does not respond in time under some faults such as short circuit.

[0057] To this end, the present invention provides a wave-by-wave current limiting circuit based on the Heric circuit, such as Figure 2 As shown, it includes: a primary overcurrent protection circuit, a secondary overcurrent protection circuit, a DSP chip and a trigger. Among them, the input end of the primary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the primary overcurrent protection circuit is connected to the first input end of the DSP chip, and the first output end of the DSP chip is connected to the main switch tube in the Heric circuit; the input end of the secondary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the secondary overcurrent protection circuit is respectively connected to the second input end of the DSP chip and the first input end of the trigger, the second output end of the DSP chip is connected to the second input end of the trigger, and the output end of the trigger is connected to the freewheeling switch tube in the Heric circuit.

[0058] Specifically, the primary overcurrent protection circuit is used to convert the inductor current sampling signal into an average inductor current signal, and then compare the average inductor current signal with the average inductor current overcurrent threshold to generate a primary overcurrent signal, and send the primary overcurrent signal to the DSP chip, and the DSP chip performs wave-by-wave current limiting on the main switch tube according to the primary overcurrent signal. The secondary overcurrent protection circuit is used to compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal and a secondary hardware overcurrent signal, and then send the secondary software overcurrent signal to the DSP chip, and send the secondary hardware overcurrent signal to the trigger IC, the DSP chip performs wave-by-wave current limiting on the main switch tube according to the secondary software overcurrent signal, and the trigger IC performs wave blocking on the freewheeling switch tube according to the secondary hardware overcurrent signal. The peak inductor current overcurrent threshold is greater than the peak inductor current of the average inductor current, and the peak inductor current is the peak inductor current calculated when the bus voltage is the highest.

[0059] In the embodiment of the present invention, in the hardware design, the average inductor current overcurrent threshold that triggers the first-level overcurrent signal should be set to the peak value of the maximum output effective value current, and the current value is equal to the average inductor current value at the peak or trough. Since the first-level overcurrent protection circuit and the second-level overcurrent protection circuit have the same wave-closing logic, in order to prevent the two-level overcurrent conflict, the peak inductor current overcurrent threshold in the second-level overcurrent protection circuit should be greater than the peak inductor current of the average inductor current in the first-level overcurrent protection circuit, and the peak inductor current must be the peak inductor current calculated when the bus voltage is the highest, so that the two-level overcurrent will not conflict with each other. The first-level overcurrent protection circuit is generally easy to trigger when overloaded or short-circuited for a long time, and the second-level overcurrent protection circuit is easy to trigger at the moment of short circuit or sudden RCD load. The first-level overcurrent protection circuit must go through a switching cycle before it can be triggered, and it can be triggered for a long time. The output current is also controllable and can adapt to long-term impact loads. The second-level overcurrent protection circuit is instantaneous, generally triggered instantly, mainly to deal with instantaneous sudden working conditions, cannot be triggered for a long time, and generally shuts down after being triggered for 2-3 switching cycles. The two-stage overcurrent protection circuit has its own advantages and disadvantages. The first-stage overcurrent protection circuit uses the average inductor current as the overcurrent trigger value, resulting in a slow response. Therefore, the peak inductor current of the second-stage overcurrent protection circuit is used to compensate for this shortcoming. The second-stage overcurrent protection circuit uses the peak inductor current as the overcurrent trigger value. Since the output current is unstable, the average inductor current of the first-stage overcurrent protection circuit is controllable to compensate for this shortcoming, and each takes its own advantages.

[0060] The present invention provides a wave-by-wave current limiting circuit based on the Heric circuit, which is a two-stage overcurrent protection circuit in hardware. In the first-stage overcurrent protection circuit, the average inductor current is used for wave-by-wave current limiting to cope with the working condition with long-term impact load; in the second-stage overcurrent protection circuit, the peak inductor current is used for overcurrent protection to cope with instantaneous sudden working conditions. By setting up two-stage overcurrent protection circuits, each takes advantage of its own strengths and makes up for their own shortcomings, thereby providing a better wave-by-wave current limiting strategy for the inverter.

[0061] In an optional embodiment, if Figure 3 As shown, the first-level overcurrent protection circuit includes: a low-pass filter, a first resistor R1, a first comparator U1 and a second comparator U2. Among them, the threshold of the in-phase input terminal of the first comparator U1 is the positive half-wave average inductor current overcurrent threshold, the inverting input terminal of the first comparator U1 is respectively connected to the output terminal of the low-pass filter and the in-phase input terminal of the second comparator U2, and the output terminal of the first comparator U1 is respectively connected to one end of the first resistor R1 and the output terminal of the second comparator U2. The input terminal of the low-pass filter is connected to the inductor current sampling signal. The threshold of the inverting input terminal of the second comparator U2 is the negative half-wave average inductor current overcurrent threshold, and the output terminal of the second comparator U2 is connected to the first input terminal of the DSP chip. The other end of the first resistor R1 is connected to an external DC power supply.

[0062] Specifically, Figure 3 As shown, the first-level overcurrent protection circuit also includes: a second resistor R2, a third resistor R3, a first capacitor C1, a fourth resistor R4, a fifth resistor R5, and a second capacitor C2. Among them, the non-inverting input end of the first comparator U1 is respectively connected to one end of the second resistor R2, one end of the third resistor R3 and one end of the first capacitor C1, the other end of the third resistor R3 and the other end of the first capacitor C1 are both connected to an external DC power supply, and the other end of the second resistor R2 is grounded. The inverting input end of the second comparator U2 is respectively connected to one end of the fourth resistor R4, one end of the fifth resistor R5 and one end of the second capacitor C2, the other end of the fourth resistor R4 is connected to an external DC power supply, and the other end of the fifth resistor R5 and the other end of the second capacitor C2 are both grounded.

[0063] In the embodiment of the present invention, Figure 3As shown, the primary overcurrent protection circuit uses the average inductor current for wave-by-wave current limiting. Signal INV_I is the inductor current sampling signal, which is a triangular wave signal. After the triangular wave signal is filtered by the low-pass filter composed of R4 and C4, it becomes a fixed voltage value when input into the first comparator U1 and the second comparator U2. This value is the sampling value of the average inductor current. DSP_OCP_I is a primary overcurrent signal, connected to the GPIO of the DSP chip. It is high level normally and low level when it fails. The first comparator U1 is a positive half-wave overcurrent comparator. The voltage threshold is set to be positive according to the resistance values ​​of R2 and R3. This value is the positive half-wave average inductor current overcurrent threshold. The second comparator U2 is a negative half-wave overcurrent comparator. The voltage threshold is set to be negative according to the resistance values ​​of R4 and R5. This value is the negative half-wave average inductor current overcurrent threshold. The output peak current of the Heric circuit is equal to the average inductor current. When overloaded or short-circuited for a long time, the output current increases. When the output current value reaches the average inductor current overcurrent threshold, the current limiting starts wave by wave. In the software, only PWM1A and PWM2A are blocked, that is, only the main switch tubes Q1, Q2, Q3, and Q4 are blocked, and the freewheeling switch tubes Q5 and Q6 are not blocked, and the freewheeling path of the inductor current is not changed. At this time, the output current is equal to the average inductor current overcurrent threshold. If the peak inductor current is used to block the wave for this level of overcurrent, the effect cannot be achieved, and the output current will change with the change of the bus voltage. Of course, using the average inductor current as a trigger condition for blocking the wave has some limitations, that is, the response is too slow, and it will not be able to protect in the case of instantaneous overcurrent (such as short circuit moment, sudden RCD load moment). Therefore, a secondary overcurrent protection is set, and the peak inductor current is used as the overcurrent trigger value.

[0064] The primary overcurrent protection circuit uses the average inductor current to limit the current wave by wave, and adopts pure software to block the wave. By adopting the primary overcurrent protection circuit, the inverter can adapt to long-term impact loads; and the controllable output current when the average inductor current is used as the overcurrent trigger value can make up for the problem of unstable output current when the peak inductor current is used as the overcurrent trigger value; and when limiting the current wave by wave, the path of the inductor current is not changed, which can well reduce the stress of the switch tube.

[0065] In an optional embodiment, if Figure 4As shown, the secondary overcurrent protection circuit includes: a third comparator U3, a fourth comparator U4 and a sixth resistor R6. Among them, the threshold of the in-phase input terminal of the third comparator U3 is the positive half-wave peak inductor current overcurrent threshold, the inductor current sampling signal INV_I is respectively input into the inverting input terminal of the third comparator U3 and the in-phase input terminal of the fourth comparator U4, and the output terminal of the third comparator U3 is respectively connected to one end of the sixth resistor R6 and the output terminal of the fourth comparator U4. The threshold of the inverting input terminal of the fourth comparator U4 is the negative half-wave peak inductor current overcurrent threshold, and the output terminal of the fourth comparator U4 is connected to the second input terminal of the DSP chip. The other end of the sixth resistor R6 is connected to an external DC power supply.

[0066] Specifically, the secondary overcurrent protection circuit also includes: a fifth comparator U5, a first transistor Q7, a seventh resistor R7 and a third capacitor C3. Among them, the in-phase input terminal of the fifth comparator U5 is connected to an external DC power supply, the inverting input terminal of the fifth comparator U5 is respectively connected to the output terminals of the third comparator U3 and the fourth comparator U4, and the output terminal of the fifth comparator U5 is respectively connected to one end of the seventh resistor R7, one end of the third capacitor C3 and the control terminal of the first transistor Q7. The other end of the seventh resistor R7 and the first end of the first transistor Q7 are both connected to the external DC power supply, the second end of the first transistor Q7 and the other end of the third capacitor C3 are both grounded, and the first end of the first transistor Q7 is also connected to the first input terminal of the trigger.

[0067] In the embodiment of the present invention, Figure 4 As shown, the secondary overcurrent protection circuit uses the peak inductor current as the overcurrent trigger value. The inductor current sampling signal INV_I is not filtered and directly enters the third comparator U3 and the fourth comparator U4. The output of the third comparator U3 and the fourth comparator U4 is a square wave signal. When the inverter inductor current reaches the peak inductor current overcurrent threshold, the secondary overcurrent protection will be triggered. DSP_OCP_II is a secondary software overcurrent signal, which is connected to the GPIO port of the DSP chip. It is high level normally and low level when it fails. Hard_OCP_II is a secondary hardware overcurrent signal, which is high level normally and low level when it fails. This signal is connected to the trigger IC. The input of the trigger IC is connected to the PWM signal and the Hard_OCP_II signal from the DSP chip. When the Hard_OCP_II signal is low level, the trigger IC is self-locked and has no output, thereby realizing hardware blocking. The function of the fifth comparator U5 is to separate the DSP_OCP_II and Hard_OCP_II signals to achieve mutual non-influence. By adjusting the values ​​of R7 and C3, the secondary hardware overcurrent signal Hard_OCP_II can be delayed relative to the secondary software overcurrent signal DSP_OCP_II, and the delayed wave sealing is realized in hardware, thereby not changing the freewheeling path of the inductor current.

[0068] In an optional embodiment, if Figure 4 As shown, the secondary overcurrent protection circuit also includes: an eighth resistor R8, a ninth resistor R9, a fourth capacitor C4, a tenth resistor R10, an eleventh resistor R11 and a fifth capacitor C5. Among them, the in-phase input end of the third comparator U3 is respectively connected to one end of the eighth resistor R8, one end of the ninth resistor R9 and one end of the fourth capacitor C4, the other end of the ninth resistor R9 and the other end of the fourth capacitor C4 are both connected to an external DC power supply, and the other end of the eighth resistor R8 is grounded. The inverting input end of the fourth comparator U4 is respectively connected to one end of the tenth resistor R10, one end of the eleventh resistor R11 and one end of the fifth capacitor C5, the other end of the eleventh resistor R11 and the other end of the fifth capacitor C5 are both grounded, and the other end of the tenth resistor R10 is connected to an external DC power supply.

[0069] Specifically, the third comparator U3 is a positive half-wave overcurrent comparator, and the voltage threshold value can be set to be positive according to the resistance values ​​of R8 and R9, and this value is the positive half-wave peak inductor current overcurrent threshold value. The fourth comparator U4 is a negative half-wave overcurrent comparator, and the voltage threshold value can be set to be negative according to the resistance values ​​of R10 and R11, and this value is the negative half-wave peak inductor current overcurrent threshold value.

[0070] The secondary overcurrent protection circuit uses the peak inductor current to perform overcurrent protection, and the software and hardware are combined to block the wave. By adopting the secondary overcurrent protection circuit, the inverter can cope with instantaneous sudden working conditions. And the fast response characteristics of the peak inductor current can make up for the problem of slow response of the average inductor current. Compared with using DSP interrupts to delay the blocking of the wave, the present invention adopts a combination of software and hardware, which saves DSP resources, and also controls the delay time very well, and reduces the stress of the switch tube.

[0071] The present invention provides a wave-by-wave current limiting control method based on Heric circuit. Figure 2 , Figure 3 and Figure 4 The wave-by-wave current limiting circuit based on the Heric circuit is shown in FIG. Figure 5 As shown, the control method includes the following steps:

[0072] Step S11, obtaining an inductor current sampling signal in the Heric circuit.

[0073] Specifically, a current sensor is used to collect an inductor current sampling signal in a Heric circuit.

[0074] Step S12: converting the inductor current sampling signal into an average inductor current signal, and comparing the average inductor current signal with the average inductor current overcurrent threshold to generate a primary overcurrent signal.

[0075] Specifically, the inductor current sampling signal is input to the primary overcurrent protection circuit, and the average inductor current is used for wave-by-wave current limiting. The collected inductor current sampling signal is a triangular wave signal. After being filtered by the low-pass filter composed of R4 and C4, the triangular wave signal becomes a fixed voltage value when input into the first comparator U1 and the second comparator U2. This value is the average inductor current signal. During the positive half-cycle, in the first comparator U1, the positive half-wave average inductor current signal is compared with the positive half-wave average inductor current overcurrent threshold, and the primary overcurrent signal DSP_OCP_I is output; during the negative half-cycle, in the second comparator U2, the negative half-wave average inductor current signal is compared with the negative half-wave average inductor current overcurrent threshold, and the primary overcurrent signal DSP_OCP_I is output. DSP_OCP_I is a primary overcurrent signal, connected to the GPIO of the DSP chip, which is high level normally and low level in case of failure.

[0076] Step S13, compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal, and generate a secondary hardware overcurrent signal after a preset delay time, the peak inductor current overcurrent threshold is greater than the average inductor current overcurrent threshold, and the peak inductor current overcurrent threshold is the peak inductor current calculated when the bus voltage is the highest.

[0077] Specifically, the inductor current sampling signal is input into the secondary overcurrent protection circuit, and the peak inductor current is used for wave-by-wave current limiting. The inductor current sampling signal INV_I enters the third comparator U3 and the fourth comparator U4 without filtering. In the positive half cycle, in the third comparator U3, the positive half-wave inductor current signal is compared with the positive half-wave peak inductor current overcurrent threshold, and the secondary software overcurrent signal DSP_OCP_II is output when the inductor current reaches the peak inductor current overcurrent threshold; in the negative half cycle, in the fourth comparator U4, the negative half-wave inductor current signal is compared with the negative half-wave peak inductor current overcurrent threshold, and the secondary software overcurrent signal DSP_OCP_II is output when the inductor current reaches the peak inductor current overcurrent threshold. DSP_OCP_II is a secondary software overcurrent signal, connected to the GPIO port of the DSP chip, which is high level normally and low level in case of failure.

[0078] In addition, by setting R7 and C3, the secondary hardware overcurrent signal Hard_OCP_II is generated with a delay. Hard_OCP_II is a secondary hardware overcurrent signal, which is high level normally and low level when faulty. This signal is connected to the trigger IC. The input of the trigger IC is connected to the PWM signal and the Hard_OCP_II signal coming out of the DSP chip. When the Hard_OCP_II signal is low level, the trigger is self-locked and has no output, thereby realizing hardware blocking. The function of the fifth comparator U5 is to separate the DSP_OCP_II and Hard_OCP_II signals so that they do not affect each other. By adjusting the values ​​of R7 and C3, the secondary hardware overcurrent signal Hard_OCP_II can be delayed relative to the secondary software overcurrent signal DSP_OCP_II, and the delayed blocking is realized in hardware, thereby not changing the freewheeling path of the inductor current.

[0079] Since the first-level overcurrent protection circuit and the second-level overcurrent protection circuit have the same wave blocking logic, in order to prevent the two-level overcurrent conflict, the peak inductor current overcurrent threshold in the second-level overcurrent protection circuit should be greater than the peak inductor current of the average inductor current in the first-level overcurrent protection circuit, and the peak inductor current must be the peak inductor current calculated when the bus voltage is the highest, so that the two-level overcurrent will avoid conflict with each other.

[0080] Step S14, current limiting is performed on the main switch tube wave by wave according to the secondary software overcurrent signal, and after a preset delay, the freewheeling switch tube is blocked according to the secondary hardware overcurrent signal, or current limiting is performed on the main switch tube wave by wave according to the primary overcurrent signal.

[0081] Specifically, when encountering an overload or a long-term short circuit, the first-level overcurrent protection is triggered, and a first-level overcurrent signal is generated. The DSP chip performs wave-by-wave current limiting on the main switch tube according to the first-level overcurrent signal. When encountering a short circuit or a sudden RCD load, the second-level overcurrent protection is triggered, and a second-level hardware overcurrent signal is generated after a preset delay after the second-level software overcurrent signal is generated. The DSP chip performs wave-by-wave current limiting on the main switch tube according to the second-level software overcurrent signal, and after a preset delay, the second-level hardware overcurrent signal is sent to the trigger IC. The trigger IC blocks the freewheeling switch tube according to the second-level hardware overcurrent signal.

[0082] In software control, if the DSP_OCP_I signal is triggered, the software will only block PWM1A and PWM2A, that is, Q1, Q2, Q3, Q4, and will not block PWM1B and PWM2B, that is, Q5 and Q6 are in the on state. Therefore, the freewheeling path of the inductor current is as follows: Figure 6As shown, L1→C2→L2→Q6→Q5 does not change the path of the inverter inductor current, which can effectively reduce the stress of the switch tube. The output current is equal to the average inductor current of DSP_OCP_I. This current is used for wave-by-wave current limiting, which can continuously trigger multiple power frequency cycles. It can adapt to long-term short circuits and loads, and can also be used to start some RCD loads. The first-level overcurrent protection is a pure software wave blocking, and no hardware wave blocking is performed. The first-level overcurrent protection is easily triggered under conditions such as long-term short circuits and overloads. If the DSP_OCP_II signal is triggered, the software wave blocking logic is the same as the first-level overcurrent protection. Only PWM1A and PWM2A are blocked, that is, Q1, Q2, Q3, and Q4, and PWM1B and PWM2B are not blocked, that is, Q5 and Q6 are in the on state. Therefore, the freewheeling path of the inductor current is as follows Figure 6 As shown in the figure, L1→C2→L2→Q6→Q5 does not change the path of the inverter inductor current, which can effectively reduce the stress of the switch tube. If DSP_OCP_II is triggered to block all the switch tubes, the stress of the switch tube will be very large. It is also difficult to achieve delayed blocking in software when DSP control is used alone. In order to reduce the stress of the switch tube, PWM1B and PWM2B are not blocked in software, and the trigger IC is used to block the wave through circuit delay in hardware.

[0083] The present invention provides a wave-by-wave current limiting control method based on the Heric circuit. In the primary overcurrent protection, the average inductor current is used for wave-by-wave current limiting to cope with the working condition with long-term impact load; in the secondary overcurrent protection, the peak inductor current is used for overcurrent protection to cope with instantaneous sudden working conditions. By setting two levels of overcurrent protection, each takes advantage of its own strengths and makes up for their own shortcomings, thereby providing a better wave-by-wave current limiting strategy for the inverter.

[0084] In an optional implementation, the positive half-wave average inductor current overcurrent threshold is set according to the resistance values ​​of the second resistor R2 and the third resistor R3, and the negative half-wave average inductor current overcurrent threshold is set according to the resistance values ​​of the fourth resistor R4 and the fifth resistor R5.

[0085] Specifically, the first comparator U1 is a positive half-wave overcurrent comparator, and the voltage threshold is set to be positive according to the resistance values ​​of R2 and R3, and the value is the positive half-wave average inductor current overcurrent threshold. The second comparator U2 is a negative half-wave overcurrent comparator, and the voltage threshold is set to be negative according to the resistance values ​​of R4 and R5, and the value is the negative half-wave average inductor current overcurrent threshold.

[0086] In an optional implementation, the delay time is set according to the resistance of the seventh resistor R7 and the capacitance of the third capacitor C3.

[0087] Specifically, by adjusting the values ​​of R7 and C3 and performing delayed sealing in hardware, the secondary hardware overcurrent signal Hard_OCP_II can be generated with a delayed generation relative to the secondary software overcurrent signal DSP_OCP_II.

[0088] The present invention provides an inverter, comprising a Heric circuit and a wave-by-wave current limiting circuit based on the Heric circuit of any one of the above implementations.

[0089] Specifically, by setting a wave-by-wave current limiting circuit based on the Heric circuit in any of the above-mentioned embodiments in the inverter, the wave-by-wave current limiting logic and the overcurrent blocking control logic of the inverter can be optimized, thereby solving the problem of excessive stress of switching devices caused by overcurrent, overload, and output short circuit, and improving the overload capacity and impact load carrying ability of the inverter.

[0090] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A wave-by-wave current limiting circuit based on Heric circuit, characterized in that: The circuit includes: a primary overcurrent protection circuit, a secondary overcurrent protection circuit, a DSP chip and a trigger, wherein: The input end of the primary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the primary overcurrent protection circuit is connected to the first input end of the DSP chip, and the first output end of the DSP chip is connected to the main switch tube in the Heric circuit; The input end of the secondary overcurrent protection circuit inputs the inductor current sampling signal of the Heric circuit, the output end of the secondary overcurrent protection circuit is respectively connected to the second input end of the DSP chip and the first input end of the trigger, the second output end of the DSP chip is connected to the second input end of the trigger, and the output end of the trigger is connected to the freewheeling switch tube in the Heric circuit; The primary overcurrent protection circuit is used to compare the processed inductor current sampling signal with the average inductor current overcurrent threshold to generate a primary overcurrent signal, and the DSP chip performs wave-by-wave current limiting on the main switch tube according to the primary overcurrent signal; The secondary overcurrent protection circuit is used to compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal and a secondary hardware overcurrent signal. The DSP chip performs wave-by-wave current limiting on the main switch tube according to the secondary software overcurrent signal, and the trigger blocks the freewheeling switch tube according to the secondary hardware overcurrent signal.

2. The Heric circuit-based wave-by-wave current limiting circuit according to claim 1, characterized in that: The primary overcurrent protection circuit comprises: a low-pass filter, a first resistor, a first comparator and a second comparator, wherein: The threshold of the non-inverting input terminal of the first comparator is the positive half-wave average inductor current over-current threshold, the inverting input terminal of the first comparator is respectively connected to the output terminal of the low-pass filter and the non-inverting input terminal of the second comparator, and the output terminal of the first comparator is respectively connected to one end of the first resistor and the output terminal of the second comparator; The input end of the low-pass filter is connected to the inductor current sampling signal; The threshold of the inverting input terminal of the second comparator is the negative half-wave average inductor current overcurrent threshold, and the output terminal of the second comparator is connected to the first input terminal of the DSP chip; The other end of the first resistor is connected to an external DC power supply.

3. The Heric circuit-based wave-by-wave current limiting circuit according to claim 2, characterized in that: The primary overcurrent protection circuit further includes: a second resistor, a third resistor, a first capacitor, a fourth resistor, a fifth resistor, and a second capacitor, wherein: The non-inverting input terminal of the first comparator is respectively connected to one end of the second resistor, one end of the third resistor and one end of the first capacitor, the other end of the third resistor and the other end of the first capacitor are both connected to an external DC power supply, and the other end of the second resistor is grounded; The inverting input terminal of the second comparator is respectively connected to one end of the fourth resistor, one end of the fifth resistor and one end of the second capacitor, the other end of the fourth resistor is connected to an external DC power supply, and the other end of the fifth resistor and the other end of the second capacitor are both grounded.

4. The Heric circuit-based wave-by-wave current limiting circuit according to claim 1, characterized in that: The secondary overcurrent protection circuit comprises: a third comparator, a fourth comparator and a sixth resistor, wherein: The threshold of the non-inverting input terminal of the third comparator is the positive half-wave peak inductor current over-current threshold, the inductor current sampling signal is respectively input into the inverting input terminal of the third comparator and the non-inverting input terminal of the fourth comparator, and the output terminal of the third comparator is respectively connected to one end of the sixth resistor and the output terminal of the fourth comparator; The threshold of the inverting input terminal of the fourth comparator is the negative half-wave peak inductor current overcurrent threshold, and the output terminal of the fourth comparator is connected to the second input terminal of the DSP chip; The other end of the sixth resistor is connected to an external DC power supply.

5. The Heric circuit-based wave-by-wave current limiting circuit according to claim 4, characterized in that: The secondary overcurrent protection circuit further includes: a fifth comparator, a first transistor, a seventh resistor and a third capacitor, wherein: The non-inverting input terminal of the fifth comparator is connected to an external DC power supply, the inverting input terminal of the fifth comparator is connected to the output terminals of the third comparator and the fourth comparator respectively, and the output terminal of the fifth comparator is connected to one end of the seventh resistor, one end of the third capacitor and the control terminal of the first transistor respectively; The other end of the seventh resistor and the first end of the first transistor are both connected to an external DC power supply, the second end of the first transistor and the other end of the third capacitor are both grounded, and the first end of the first transistor is also connected to the first input end of the trigger.

6. The Heric circuit-based wave-by-wave current limiting circuit according to claim 5, characterized in that: The secondary overcurrent protection circuit further includes: an eighth resistor, a ninth resistor, a fourth capacitor, a tenth resistor, an eleventh resistor and a fifth capacitor, wherein: The non-inverting input terminal of the third comparator is respectively connected to one end of the eighth resistor, one end of the ninth resistor and one end of the fourth capacitor, the other end of the ninth resistor and the other end of the fourth capacitor are both connected to an external DC power supply, and the other end of the eighth resistor is grounded; The inverting input terminal of the fourth comparator is respectively connected to one end of the tenth resistor, one end of the eleventh resistor and one end of the fifth capacitor, the other end of the eleventh resistor and the other end of the fifth capacitor are both grounded, and the other end of the tenth resistor is connected to an external DC power supply.

7. The Heric circuit-based wave-by-wave current limiting circuit according to claim 1, characterized in that: The peak inductor current overcurrent threshold is greater than the peak inductor current of the average inductor current, and the peak inductor current is the peak inductor current calculated when the bus voltage is the highest.

8. A wave-by-wave current limiting control method based on Heric circuit, characterized in that: Based on the Heric circuit-based wave-by-wave current limiting circuit according to any one of claims 1 to 7, the control method comprises: Obtain the inductor current sampling signal in the Heric circuit; Converting the inductor current sampling signal into an average inductor current signal, and comparing the average inductor current signal with an average inductor current overcurrent threshold to generate a primary overcurrent signal; Compare the inductor current sampling signal with the peak inductor current overcurrent threshold to generate a secondary software overcurrent signal, and generate a secondary hardware overcurrent signal after a preset delay time, wherein the peak inductor current overcurrent threshold is greater than the average inductor current overcurrent threshold, and the peak inductor current overcurrent threshold is the peak inductor current calculated when the bus voltage is the highest; The main switch tube is current limited wave by wave according to the secondary software overcurrent signal, and the freewheeling switch tube is blocked according to the secondary hardware overcurrent signal after a preset delay time, or the main switch tube is current limited wave by wave according to the primary overcurrent signal.

9. The wave-by-wave current limiting control method based on Heric circuit according to claim 8, characterized in that: According to the resistance values ​​of the second resistor and the third resistor, a positive half-wave average inductor current overcurrent threshold is set; The negative half-wave average inductor current overcurrent threshold is set according to the resistance values ​​of the fourth resistor and the fifth resistor.

10. The wave-by-wave current limiting control method based on Heric circuit according to claim 8, characterized in that: The delay time is set according to the resistance value of the seventh resistor and the capacitance value of the third capacitor.

11. An inverter, characterized in that: It comprises a Heric circuit and a wave-by-wave current limiting circuit based on the Heric circuit as described in any one of claims 1-7.

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