Filter and method for adaptively filtering various frequency signal impurities
By introducing clock prescaler control signals, system clock signals, sampling window control signals and filter threshold control signals into the filter, combined with sampling window enable module and frequency division clock module, the existing filters are solved for specific frequencies The problem of insufficient clutter filtering ability realizes flexible filtering of multiple frequency signals and supports multiple filtering functions.
Patent Information
- Application Number
- CN202411357912.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-27
AI Technical Summary
Existing analog filters can only filter out clutter at specific frequencies, lack universality, and cannot effectively deal with impurities of multiple frequency signals.
Design an adaptive filter, by introducing a clock prescaler control signal, system clock signal, sampling window control signal and filter threshold control signal, a collaborative sampling window enable module, a frequency division clock module, and a sampling signal and threshold subtraction counting module. It realizes filtering operations for impurities of signal different frequencies, and supports filtering functions such as high-pass, low-pass, band-pass, and band-resistance.
It realizes flexible configuration of filtering effects, meets the filtering needs of signals of different frequency, has a simple combination logic and reliable effect, which is better than traditional filters.
Smart Images
Figure CN119210401A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of signal processing, and in particular to a filter for adaptively filtering impurities of signals with multiple frequencies. Background Art
[0002] In integrated circuit systems, filters are important circuit function modules. Filters are mainly used to eliminate high-frequency false jump glitches, and are widely used at the input end of high-speed amplifiers and the input and output ends of comparators. Common filter implementation methods mainly use a series-parallel network of capacitors and resistors to achieve high-pass, low-pass, band-pass, band-stop and other filter functions. However, this type of analog filter solution can only filter out clutter of a specific frequency. The filtering solution is relatively specific and single, and is not universal. Summary of the invention
[0003] Purpose of the invention: In order to overcome the deficiencies in the prior art, the present invention provides a filter and method for adaptively filtering impurities of multiple frequency signals, which introduces a clock pre-division control signal, a system clock signal, a sampling window control signal and a filtering threshold control signal to coordinate a sampling window enable module, a frequency division clock module and a sampling signal and threshold subtraction counting module to perform filtering operations on impurities of different frequency signals, thereby realizing flexible configuration of the filtering effect.
[0004] Technical solution: To achieve the above-mentioned purpose, the present invention provides a filter for adaptively filtering impurities of multiple frequency signals, including a sampling window enabling module, a frequency division clock module and a sampling signal and threshold subtraction counting module; the output end of the sampling window enabling module is electrically connected to the input end of the sampling signal and threshold subtraction counting module, and the output end of the sampling signal and threshold subtraction counting module serves as the output end of the filter; the frequency division clock module provides a frequency division clock signal for the sampling window enabling module; the input end of the sampling window enabling module is electrically connected to the input end and the output end of the filter to collect the input signal and the output signal of the filter; the filter introduces a clock pre-division control signal, a system clock signal, a sampling window control signal and a filtering threshold control signal to coordinate the sampling window enabling module, the frequency division clock module and the sampling signal and threshold subtraction counting module to filter signal impurities of different frequencies in the input signal.
[0005] Further, the sampling window enable module includes an X1 XOR gate circuit, a D1 trigger, a C2 counter, a B1 buffer and an X2 XOR gate circuit; the two input ends of the X1 XOR gate circuit are respectively connected to the input end and the output end of the filter, and the output end of the X1 XOR gate circuit is electrically connected to the CK end of the D1 trigger; the Q end of the D1 trigger is electrically connected to the input end of the C2 counter, the output end of the C2 counter is electrically connected to one input end of the X2 XOR gate circuit, and the other input end of the X2 XOR gate circuit inputs the sampling window control signal; the output end of the X2 XOR gate circuit is respectively electrically connected to the RN end of the D1 trigger and the input end of the B1 buffer, and the output end of the B1 buffer outputs the EN_CNT signal.
[0006] Furthermore, the frequency-dividing clock module includes a full adder circuit, a D2 trigger, an X3 XOR gate circuit, a D3 trigger and a B2 buffer; the output end of the full adder circuit is electrically connected to the D end of the D2 trigger; the CK end of the D2 trigger inputs a system clock signal, the Q end of the D2 trigger is electrically connected to the clock control end of the full adder circuit and an input end of the X3 XOR gate circuit, the other input end of the X3 XOR gate circuit inputs a clock pre-dividing control signal, and the output end of the X3 XOR gate circuit is electrically connected to the D end of the D3 trigger; the CK end of the D3 trigger inputs a system clock signal, the output end of the D3 trigger is electrically connected to the input end of the B2 buffer and the reset end of the D2 trigger 32, and the output end of the B2 buffer outputs a frequency-dividing clock signal SYSCLK_DIV.
[0007] Furthermore, it also includes a first AND gate circuit and a second AND gate circuit; the output end of the B2 buffer is electrically connected to the clock input end of the C2 counter, an input end of the first AND gate circuit and an input end of the second AND gate circuit; the output end of the B1 buffer is electrically connected to the other input end of the first AND gate circuit, and the output end of the B1 buffer is electrically connected to the other end of the second AND gate circuit through the first signal flipping circuit.
[0008] Furthermore, the output end of the first AND gate circuit is electrically connected to the sampling signal and the input end of the C1 counter in the threshold subtraction counting module, and the output end of the second AND gate circuit is electrically connected to the sampling signal and the input end of the C0 counter in the threshold subtraction counting module.
[0009] Furthermore, the sampling signal and threshold subtraction counting module also includes an S1 subtractor, an S0 subtractor and an RS latch; the output end of the C1 counter is electrically connected to an input end of the S1 subtractor, and the other input end of the S1 subtractor inputs a filter threshold control signal; the output end of the C0 counter is electrically connected to an input end of the S0 subtractor, and the other input end of the S1 subtractor inputs a filter threshold control signal; the output ends of the S0 subtractor and the S1 subtractor are electrically connected to two input ends of the RS latch through a second signal flipping circuit and a third signal flipping circuit, respectively; the output end of the RS latch outputs a FIL-OUT signal, which is a signal after the input signal is filtered by a filter.
[0010] Furthermore, a working method of a filter for adaptively filtering impurities of multiple frequency signals comprises the following steps:
[0011] Step 1, setting a clock pre-scaling control signal, a sampling window control signal and a filter threshold control signal;
[0012] Step 2: The input signal and output signal of the filter are collected through the sampling window enabling module to determine whether the phases of the input signal and the output signal are the same. If they are the same, they are directly output; if they are not the same, the next step is executed;
[0013] Step 3: The sampling window enable module is enabled, and the sampling signal and the threshold subtraction counting module start counting to determine whether the number of either number 0 or number 1 reaches or exceeds the filter threshold control signal. When the filter threshold control signal is reached or exceeded, the FIL-OUT signal output by the filter is flipped. When the filter threshold control signal is not reached or exceeded, the FIL-OUT signal output by the filter is not flipped.
[0014] Step 4: The sampling window enable module is disabled, the counting ends, and the filter outputs the filtered FIL-OUT signal.
[0015] Furthermore, the sampling signal and threshold subtraction counting module determines whether the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal, and subtracts the number of number 0 or number 1 from the filtering threshold control signal by setting S0 subtractor and S1 subtractor respectively; when the subtraction can produce 1, the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal.
[0016] Beneficial effect: The filter and method for adaptively filtering impurities of multiple frequency signals of the present invention mainly integrate digital control signals, and independently configure the frequency division value, sampling window, and counting threshold. The clock pre-division control signal, system clock signal, sampling window control signal, and filtering threshold control signal are introduced to coordinate the sampling window enable module, the frequency division clock module, and the sampling signal and threshold subtraction counting module, so as to realize flexible configuration of the filtering effect, meet different filtering performance requirements, and realize high-pass, low-pass, band-pass, band-stop and other filtering functions; and the combination logic is concise and the effect is reliable, which is better than the traditional filter. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A filter block diagram for adaptively filtering impurities in signals of multiple frequencies;
[0018] Figure 2 It is the circuit diagram of sampling window enabling module;
[0019] Figure 3 This is the circuit diagram of the frequency division clock module;
[0020] Figure 4 It is the circuit diagram of sampling signal and threshold value subtraction counting module;
[0021] Figure 5 A flow chart of a filter working method for adaptively filtering impurities of multiple frequency signals;
[0022] Figure 6 The overall working timing diagram of the filter for adaptively filtering impurities of multiple frequency signals;
[0023] Figure 7 The overall circuit diagram of the filter for adaptively filtering impurities of multiple frequency signals;
[0024] Figure 8 Truth diagram of the filter output state for adaptive filtering of impurities in signals with multiple frequencies. DETAILED DESCRIPTION
[0025] The present invention will be further described below in conjunction with the accompanying drawings.
[0026] like Figure 1As shown, in view of the problem that the traditional analog filter solution can only filter the fixed frequency band noise, has a single application scenario and is not universal, a filter for adaptively filtering the impurities of multiple frequency signals is proposed to coordinate the digital port; a filter for adaptively filtering the impurities of multiple frequency signals, including a sampling window enabling module 2, a frequency division clock module 3 and a sampling signal and threshold subtraction counting module 4; the output end of the sampling window enabling module 2 is electrically connected to the input end of the sampling signal and threshold subtraction counting module 4, and the output end of the sampling signal and threshold subtraction counting module 4 is used as the output end of the filter 1; the frequency division clock module 3 provides a frequency division clock signal for the sampling window enabling module 2; The input end of the sampling window enabling module 2 is electrically connected to the input end and the output end of the filter 1, and the input signal FIL_INPUT and the output signal FIL_OUTPUT of the filter 1 are collected; the filter 1 introduces the clock pre-division control signal CLKPRESCALE, the system clock signal SYSCLK, the sampling window control signal SAMPWIN and the filtering threshold control signal THRESHOLD to coordinate the sampling window enabling module 2, the frequency division clock module 3 and the sampling signal and threshold subtraction counting module 4 to filter the signal impurities of different frequencies in the input signal, thereby realizing the filtering functions of high-pass, low-pass, band-pass or band-stop on the input signal.
[0027] The frequency division clock module 3 divides the system clock into any frequency division configuration, and can adjust the sensitivity to the input signal according to user needs. When the filter input signal phase and output phase are different, a counting enable window is generated before filtering is performed. If the filter input signal phase and output are the same, the filter output remains unchanged. At this time, there is no false jump signal in the input and no filtering is required.
[0028] The sampling window enable module 2 uses the frequency-divided clock to sample the input signal level, and sends it to the counter in the sampling signal and threshold subtraction counting module 4, and subtracts it from the filter threshold control signal. When the number of counted values "0" or "1" exceeds the threshold, the subtractor carry signal is activated, and the filter outputs 0 or 1. This filtering implementation method effectively coordinates the digital port and can realize flexible configuration of the filtering effect.
[0029] like Figure 2As shown, the sampling window enabling module 2 includes an X1 XOR gate circuit 21, a D1 trigger 22, a C2 counter 23, a B1 buffer 25 and an X2 XOR gate circuit 24; the two input ends of the X1 XOR gate circuit 21 are respectively connected to the input end and the output end of the filter 1, and the output end of the X1 XOR gate circuit 21 is electrically connected to the CK end of the D1 trigger 22; the Q end of the D1 trigger 22 is electrically connected to the input end of the C2 counter 23, the output end of the C2 counter 23 is electrically connected to one input end of the X2 XOR gate circuit 24, and the other input end of the X2 XOR gate circuit 24 inputs the sampling window control signal; the output end of the X2 XOR gate circuit 24 is respectively electrically connected to the RN end of the D1 trigger 22 and the input end of the B1 buffer 25, and the output end of the B1 buffer 25 outputs the EN_CNT signal. The D end of the D1 trigger 22 inputs the TIEH level, which usually refers to being connected to a high potential VCC, VDD or a positive power supply voltage.
[0030] The two input ends of the X1 XOR gate circuit 21 respectively collect the filter input signal FIL_INPUT and the filter output signal FIL_OUTPUT of the filter 1, and perform XOR logic on the two signals; when the input signal and the output signal of the filter 1 are in phase, the X1 XOR gate circuit 21 outputs a high level, at which time the sampling window is enabled and the counting starts; otherwise, the X1 XOR gate circuit 21 outputs a low level, at which time the sampling window is disabled and the counting ends; wherein the rising edge serves as the rising edge of the working clock signal of the D1 trigger 22, the D1 trigger 22 transmits the TIEH level to the output Q end, the C2 counter 23 starts to be enabled, the C2 counter 23 internally uses the divided clock signal output by the divided clock module 3 as the working clock, and the C2 counter 23 outputs the NUM_SAMPWIN signal.
[0031] The X2 XOR gate circuit 24 performs XOR logic on the NUM_SAMPWIN signal and the sampling window control signal SAMPWIN; taking the 3-bit control signal as an example, NUM_SAMPWIN<2:0> and the sampling window control signal SAMPWIN perform XOR logic, and when the 3-bit control signals are exactly the same, the EN signal output from the XOR logic output terminal presents a low level; at the same time, the EN signal output by the X2 XOR gate circuit 24 is used to reset the D1 trigger 22. Such a timing logic arrangement ensures that when it is detected that the filter input and output are different, the sampling window enable is immediately turned on, and the enable time lasts for the period of the divided clock SYSCLK_DIV * the number of sampling windows SAMPWIN. The EN signal output by the X2 XOR gate circuit 24 increases the driving capability through the B1 buffer 25BUFFER and then outputs the EN_CNT signal as the sampling window enable signal of the actual filter, supporting the subsequent logic to continue working.
[0032] like Figure 3 As shown, the frequency division clock module 3 includes a full adder circuit 31, a D2 trigger 32, an X3 XOR gate circuit 33, a D3 trigger 34 and a B2 buffer 35; the output end of the full adder circuit 31 is electrically connected to the D end of the D2 trigger 32; the CK end of the D2 trigger 32 inputs the system clock signal, the Q end of the D2 trigger 32 is electrically connected to the clock control end of the full adder circuit 31 and one input end of the X3 XOR gate circuit 33, the other input end of the X3 XOR gate circuit 33 inputs the clock pre-division control signal, and the output end of the X3 XOR gate circuit 33 is electrically connected to the D end of the D3 trigger 34; the CK end of the D3 trigger 34 inputs the system clock signal, the output end of the D3 trigger 34 is electrically connected to the input end of the B2 buffer 35 and the reset end of the D2 trigger 32, and the output end of the B2 buffer 35 outputs the frequency division clock signal SYSCLK_DIV. <0> Input TIEH level, X<10:1> of full adder circuit 31 inputs VSS. The output end of D3 flip-flop 34 is electrically connected to the reset end RN_SYNC of D2 flip-flop 32, and the signal pulse outputted from the output end of D3 flip-flop 34 resets SUM10D-SUM0D in D2 flip-flop 32; the reset end RN of D3 flip-flop 34 receives the reset signal to reset D3 flip-flop.
[0033] Taking the clock pre-scaling control signal CLKPRESCALE<10:0> as an example, an 11-bit full adder circuit is constructed, and the SUM0-SUM10 at the output end of the full adder circuit 31 is synchronized with the system clock signal SYSCLK in the D2 trigger 32; the SUM10D-SUM0D output by the D2 trigger 32 is used to update the full adder circuit 31, and the SUM10D-SUM0D output by the output end of the D2 trigger 32 is XORed with the clock pre-scaling control signal CLKPRESCALE in the X3 XOR gate circuit XOR. When the 11-bit clock pre-division control signal CLKPRESCALE and the current 11-bit carry-end signal level of the full adder circuit 31 are all consistent, the XOR result of the X3 XOR gate circuit 33 is 0; then a D3 flip-flop 34 is added, which is also synchronized with the system clock signal SYSCLK to widen the pulse of the XOR output. This pulse is used to reset SUM10D-SUM0D, and the full adder circuit 31 is reset to zero and starts counting again; at the same time, the XOR output synchronized with the system clock signal SYSCLK in the D3 flip-flop 34 is used as the divided clock signal SYSCLK_DIV after the driving capability is improved by the B2 buffer 35BUFFER, and is supplied to the inside of the filter, that is, supplied to the inside of the sampling window enable module 2.
[0034] like Figure 7As shown, it also includes a first AND gate circuit 27 and a second AND gate circuit 28; the output end of the B2 buffer 35 is electrically connected to the clock input end of the C2 counter 23, one input end of the first AND gate circuit 27 and one input end of the second AND gate circuit 28; the output end of the B1 buffer 25 is electrically connected to the other input end of the first AND gate circuit 27, and the output end of the B1 buffer 25 is electrically connected to the other end of the second AND gate circuit 28 through the first signal flip circuit 26.
[0035] like Figure 7 As shown, the output end of the first AND gate circuit 27 is electrically connected to the input end of the C1 counter 41 in the sampling signal and threshold subtraction counting module 4, and the output end of the second AND gate circuit 28 is electrically connected to the input end of the C0 counter 43 in the sampling signal and threshold subtraction counting module 4.
[0036] like Figure 4-7 As shown, the sampling signal and threshold subtraction counting module 4 also includes an S1 subtractor 42, an S0 subtractor 44 and an RS latch 45; the output end of the C1 counter 41 is electrically connected to an input end of the S1 subtractor 42, and the other input end of the S1 subtractor 42 inputs a filtering threshold control signal; the output end of the C0 counter 43 is electrically connected to an input end of the S0 subtractor 44, and the other input end of the S1 subtractor 42 inputs a filtering threshold control signal; the output ends of the S0 subtractor 44 and the S1 subtractor 42 are electrically connected to two input ends of the RS latch 45 through a second signal flip circuit 46 and a third signal flip circuit 47 respectively; the output end of the RS latch 45 outputs a FIL-OUT signal, which is a signal after the input signal is filtered by the filter 1.
[0037] The C1 counter 41 and the C0 counter 43 input RST to reset the C1 counter 41 and the C0 counter 43, and the C1 counter 41 and the C0 counter 43 input TIEH level. The EN_CNT signal is inverted to the EN_CNTB signal, and the EN_CNT signal and the EN_CNTB signal are respectively ANDed with the SYSCLK_DIV at one input end of the first AND gate circuit 27 and the second AND gate circuit 28, and then the EN_CNT1 signal and the EN_CNT0 signal are output; the EN_CNT1 signal and the EN_CNT0 signal are respectively inputted into the input end of the C0 counter 43 and the C1 counter 41 of number 1; that is, during the sampling window enabling period, the C0 counter 43 of number 0 and the C1 counter 41 of number 1 work simultaneously.
[0038] Taking the sampling window with 5 effective bits as an example, the number of 0s and 1s in the enabling time are NUM1<4:0> and NUM0<4:0> respectively; NUM1<4:0> and NUM0<4:0> are subtracted from the filter threshold control signal THRESHOLD<4:0> respectively. When the subtraction can produce a number of 1 or more, whether the number of 0s or 1s reaches or exceeds the filter threshold control signal, the subtractor carry signal is activated, and the filter outputs 0 or 1. The S1 subtractor 42 and the S0 subtractor 44 respectively output the signal OUT1 of the number 1 and the signal OUT0 of the number 0; when any one of the number of 0s or the number of 1s reaches or exceeds the filter threshold control signal, the signal output by the filter 1 is flipped, but when the number of 0s or the number of 1s both reaches or exceeds the filter threshold control signal, it is determined that the output result of the filter 1 is invalid and filtering is performed again.
[0039] There are several cases where the OUT1 signal output from the output end of the S0 subtractor 44 and the OUT0 signal output from the output end of the S1 subtractor 42 are as follows: Figure 8 The output state truth diagram of the filter for adaptive filtering of multi-frequency signals is shown. Combined with the output truth diagram, the OUT1 signal and the OUT0B signal are used as the final output signal FIL_OUT of the filter after passing through the RS latch 45; when the OUT1 signal and the OUT0 signal are both 1, the number of 1s is greater than the filter threshold control signal, and the output signal FIL_OUT is 1; when the OUT1 signal and the OUT0 signal are both 0, the number of 0s is greater than the filter threshold control signal, and the output signal FIL_OUT is 0; Latch indicates that the state of the previous output is maintained; when the number of 1s and the number of 0s are both greater than the filter threshold control signal, it is determined to be invalid and filtering is performed again.
[0040] like Figure 6 As shown, it is an overall working timing diagram of a filter for adaptively filtering multi-frequency signals when an input signal is used.
[0041] like Figure 5 As shown, a working method of a filter for adaptively filtering impurities of multiple frequency signals includes the following steps
[0042] Step 1, setting a clock pre-scaling control signal, a sampling window control signal and a filter threshold control signal;
[0043] Step 2: The input signal and output signal of the filter 1 are collected by the sampling window enabling module 2 to determine whether the phases of the input signal and the output signal are the same. If they are the same, they are directly output; if they are not the same, the next step is executed;
[0044] Step 3, the sampling window enabling module 2 is enabled, and the sampling signal and the threshold subtraction counting module 4 start counting to determine whether the number of any one of the numbers 0 or 1 reaches or exceeds the filtering threshold control signal. When the filtering threshold control signal is reached or exceeded, the filtered FIL-OUT signal output by the filter 1 is flipped. When the filtering threshold control signal is not reached or exceeded, the filtered FIL-OUT signal output by the filter 1 is not flipped.
[0045] Step 4: the sampling window enable module 2 is disabled, the counting ends, and the filter 1 outputs the filtered FIL-OUT signal.
[0046] By changing the set clock pre-division control signal CLKPRESCALE, the sampling window control signal SAMPWIN and the filtering threshold control signal THRESHOLD, high-pass, low-pass, band-pass and band-stop filtering operations are implemented on the input signal, and signal impurities of different frequencies in the input signal are perfectly filtered; there is no need to change the circuit structure again, and flexible configuration of the filtering effect is achieved.
[0047] The sampling signal and threshold subtraction counting module 4 determines whether the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal, and subtracts the number of number 0 or number 1 from the filtering threshold control signal by setting S0 subtractor 44 and S1 subtractor 42 respectively; when the subtraction can subtract 1, the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal.
[0048] The above is only a description of the preferred embodiments of the present invention. Ordinary technicians in this technical field can make several modifications and optimizations based on the above disclosure without departing from the above basic principles. These improvements and optimizations should be regarded as the understood protection scope of the present invention.
Claims
1. A filter for adaptively filtering impurities of signals of multiple frequencies, characterized in that: The invention comprises a sampling window enabling module (2), a frequency division clock module (3) and a sampling signal and threshold subtraction counting module (4); the output end of the sampling window enabling module (2) is electrically connected to the input end of the sampling signal and threshold subtraction counting module (4), and the output end of the sampling signal and threshold subtraction counting module (4) serves as the output end of the filter (1); the frequency division clock module (3) provides a frequency division clock signal for the sampling window enabling module (2); the input end of the sampling window enabling module (2) is electrically connected to the input end and the output end of the filter (1), and the input signal and the output signal of the filter (1) are collected; the filter (1) introduces a clock pre-division control signal, a system clock signal, a sampling window control signal and a filtering threshold control signal to coordinate the sampling window enabling module (2), the frequency division clock module (3) and the sampling signal and threshold subtraction counting module (4), so as to filter signal impurities of different frequencies in the input signal.
2. The filter for adaptively filtering impurities of multiple frequency signals according to claim 1, characterized in that: The sampling window enabling module (2) comprises an X1 XOR gate circuit (21), a D1 trigger (22), a C2 counter (23), a B1 buffer (25) and an X2 XOR gate circuit (24); two input ends of the X1 XOR gate circuit (21) are respectively connected to the input end and the output end of the filter (1), and the output end of the X1 XOR gate circuit (21) is electrically connected to the CK end of the D1 trigger (22); the Q end of the D1 trigger (22) is electrically connected to the input end of the C2 counter (23), the output end of the C2 counter (23) is electrically connected to one input end of the X2 XOR gate circuit (24), and the other input end of the X2 XOR gate circuit (24) inputs a sampling window control signal; the output end of the X2 XOR gate circuit (24) is respectively electrically connected to the RN end of the D1 trigger (22) and the input end of the B1 buffer (25), and the output end of the B1 buffer (25) outputs an EN_CNT signal.
3. The filter for adaptively filtering impurities of signals with multiple frequencies according to claim 2, characterized in that: The frequency-dividing clock module (3) comprises a full adder circuit (31), a D2 trigger (32), an X3 XOR gate circuit (33), a D3 trigger (34) and a B2 buffer (35); the output end of the full adder circuit (31) is electrically connected to the D end of the D2 trigger (32); the CK end of the D2 trigger (32) inputs a system clock signal, and the Q end of the D2 trigger (32) is electrically connected to the clock control end of the full adder circuit (31) and the Q end of the X3 XOR gate circuit (33). An input terminal of the X3 XOR gate circuit (33) is input with a clock pre-division control signal at the other input terminal, and an output terminal of the X3 XOR gate circuit (33) is electrically connected to a D terminal of a D3 trigger (34); a system clock signal is input to a CK terminal of the D3 trigger (34), an output terminal of the D3 trigger (34) is electrically connected to an input terminal of a B2 buffer (35) and a reset terminal of a D2 trigger 32, and an output terminal of the B2 buffer (35) outputs a divided clock signal SYSCLK_DIV.
4. The filter for adaptively filtering impurities of signals with multiple frequencies according to claim 3, characterized in that: It also includes a first AND gate circuit (27) and a second AND gate circuit (28); the output end of the B2 buffer (35) is electrically connected to the clock input end of the C2 counter (23), one input end of the first AND gate circuit (27) and one input end of the second AND gate circuit (28); the output end of the B1 buffer (25) is electrically connected to the other input end of the first AND gate circuit (27), and the output end of the B1 buffer (25) is electrically connected to the other end of the second AND gate circuit (28) through a first signal flip circuit (26).
5. The filter for adaptively filtering impurities of signals with multiple frequencies according to claim 4, characterized in that: The output end of the first AND gate circuit (27) is electrically connected to the sampling signal and the input end of the C1 counter (41) in the threshold subtraction counting module (4), and the output end of the second AND gate circuit (28) is electrically connected to the sampling signal and the input end of the C0 counter (43) in the threshold subtraction counting module (4).
6. The filter for adaptively filtering impurities of signals with multiple frequencies according to claim 5, characterized in that: The sampling signal and threshold subtraction counting module (4) further comprises an S1 subtractor (42), an S0 subtractor (44) and an RS latch (45); the output end of the C1 counter (41) is electrically connected to an input end of the S1 subtractor (42), and the other input end of the S1 subtractor (42) inputs a filtering threshold control signal; the output end of the C0 counter (43) is electrically connected to an input end of the S0 subtractor (44), and the other input end of the S1 subtractor (42) inputs a filtering threshold control signal; the output ends of the S0 subtractor (44) and the S1 subtractor (42) are electrically connected to two input ends of the RS latch (45) through a second signal flipping circuit (46) and a third signal flipping circuit (47) respectively; the output end of the RS latch (45) outputs a FIL-OUT signal, which is a signal after the input signal is filtered by the filter (1).
7. The working method of a filter for adaptively filtering impurities of signals with multiple frequencies according to claim 6, characterized in that: The following steps are included Step 1, setting a clock pre-scaling control signal, a sampling window control signal and a filter threshold control signal; Step 2, collecting the input signal and output signal of the filter (1) through the sampling window enabling module (2), judging whether the phases of the input signal and the output signal are the same, directly outputting them if they are the same, and executing the next step if they are not the same; Step 3, the sampling window enabling module (2) is enabled, and the sampling signal and the threshold subtraction counting module (4) start counting to determine whether the number of either number 0 or number 1 reaches or exceeds the filter threshold control signal. When the filter threshold control signal is reached or exceeded, the FIL-OUT signal output by the filter (1) is flipped. When the filter threshold control signal is not reached or exceeded, the FIL-OUT signal output by the filter (1) is not flipped. Step 4: the sampling window enabling module (2) is disabled, the counting ends, and the filter (1) outputs the filtered FIL-OUT signal.
8. The working method of a filter for adaptively filtering impurities of multiple frequency signals according to claim 7, characterized in that: The sampling signal and threshold subtraction counting module (4) determines whether the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal, and respectively subtracts the number of number 0 or number 1 from the filtering threshold control signal by setting an S0 subtractor (44) and an S1 subtractor (42); when the subtraction can produce 1, the number of number 0 or number 1 reaches or exceeds the filtering threshold control signal.