Cache system, cache processing method, electronic equipment and storage medium

Abstract

The invention provides a cache system, a cache processing method, electronic equipment and a storage medium, the cache system comprises a plurality of processing cores and a configuration module, each processing core comprises a target storage area, the configuration module is used for determining multi-level cache configuration information of a first processing core, and according to the multi-level cache configuration information, the first processing core is configured to process a cache; first cache regions are divided from target storage regions of a plurality of processing cores, the first cache regions correspondingly divided by the plurality of processing cores form a multi-level cache system of the first processing cores, and the processing cores where the first cache regions of different levels are located are related to position information of the first processing cores. The first processing core is any one of the plurality of processing cores; and the first processing core is used for searching and acquiring data indicated in a data access request from the multi-level cache system of the first processing core when the data access request is received. In this way, the multi-level cache system of different processing cores can be flexibly configured, and the performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a cache system, a cache processing method, an electronic device, and a storage medium. Background Art

[0002] Many-core systems can process large-scale data and complex tasks in parallel, providing efficient computing capabilities for application fields such as scientific computing, artificial intelligence, and big data analysis. However, the computing speed of the processor and the memory access speed may not match, affecting the computing performance. In related technologies, cache technology can be used, but the execution tasks of different processing cores in the many-core system may be different, and the requirements of different tasks for the cache system may also be different. A fixed multi-level cache system may limit the performance of the many-core system. Summary of the invention

[0003] The present disclosure provides a cache system, a cache processing method, an electronic device and a storage medium.

[0004] In a first aspect, the present disclosure provides a cache system, including multiple processing cores and a configuration module, wherein the processing core includes a target storage area:

[0005] The configuration module is used to determine multi-level cache configuration information of the first processing core, and divide the first cache area from the target storage area of ​​the multiple processing cores according to the multi-level cache configuration information, the first cache areas corresponding to the multiple processing cores constitute the multi-level cache system of the first processing core, and the processing cores where the first cache areas of different levels are located are related to the position information of the first processing core, and the first processing core is any one of the multiple processing cores;

[0006] The first processing core is used to search and obtain the data indicated in the data access request from the multi-level cache system of the first processing core when receiving the data access request.

[0007] In a second aspect, the present disclosure provides a cache processing method, which is applied to the above-mentioned cache system, and the method includes:

[0008] Determining multi-level cache configuration information of the first processing core;

[0009] According to the multi-level cache configuration information, a first cache area is divided from the target storage area of ​​multiple processing cores, and the first cache areas corresponding to the multiple processing cores constitute a multi-level cache system of the first processing core, and the processing cores at different levels where the first cache areas are located are related to the location information of the first processing core.

[0010] In a third aspect, the present disclosure provides an electronic device comprising: a plurality of processing cores; and an on-chip network configured to exchange data between the plurality of processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the above-mentioned cache processing method.

[0011] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned cache processing method when executed by a processor.

[0012] The embodiments provided by the present disclosure divide the first cache area from the target storage areas of multiple processing cores according to the multi-level cache configuration information of the first processing core, so that the first cache areas of multiple different levels are divided to form a multi-level cache system of the first processing core. In this way, the multi-level cache system of the first processing core can be flexibly configured according to the multi-level cache configuration information of the first processing core. Different processing cores can configure the multi-level cache system more specifically and flexibly to better meet the needs of different processing cores, thereby improving the overall computing and cache performance. In addition, the multi-level cache system is configured based on the target storage area of ​​the processing core itself, and there is no need to design other hardware resources additionally, thereby saving hardware resource consumption. When the first processing core receives a data access request, it can search and obtain from the multi-level cache system of the first processing core, thereby improving data access speed and efficiency.

[0013] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0015] Figure 1 A schematic diagram of the hardware architecture of a many-core system provided in an embodiment of the present disclosure;

[0016] Figure 2 A schematic diagram of the hardware architecture of another many-core system in an embodiment of the present disclosure;

[0017] Figure 3 A schematic diagram of a cache system in an embodiment of the present disclosure;

[0018] Figure 4 A schematic diagram of dividing a target storage area in an embodiment of the present disclosure;

[0019] Figure 5 A multi-level cache system with a tree-like or anti-tree-like structure in the embodiment of the present disclosure;

[0020] Figure 6 A schematic diagram of multiple cache areas and cache page tables in an embodiment of the present disclosure;

[0021] Figure 7 A schematic diagram of a multi-level cache system divided into grids in an embodiment of the present disclosure;

[0022] Figure 8 A schematic diagram of another multi-level cache system divided into grids according to an embodiment of the present disclosure;

[0023] Fig. 9 A schematic diagram of another multi-level cache system divided into grids according to an embodiment of the present disclosure;

[0024] Fig.10 A flowchart of a cache processing method provided by an embodiment of the present disclosure;

[0025] Fig.11 A block diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0027] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0028] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0031] To facilitate understanding, the concepts involved in the embodiments of the present disclosure are briefly described first.

[0032] Many-core system: Many-core system is a high-performance computing architecture that integrates multiple processor cores on a single chip and uses parallel computing to improve performance and energy efficiency. A processing core is an independent computing unit inside a processor. Each processing core can execute its own instruction stream and has its own register set and other hardware resources. With the development of multi-core technology, a processor can include multiple processing cores, so a processor can execute multiple tasks or threads at the same time.

[0033] Multi-level cache system: can alleviate the speed difference between the processor and the main memory by providing different levels of storage, thereby improving the overall system performance. In a multi-level cache system, the cache area can be divided into multiple levels according to the access speed, memory size, etc. For example, in one possible embodiment, the multi-level cache system includes: Level 1 cache (L1 cache): usually the cache closest to the processor, with the fastest access speed, can be used to store data and instructions to be executed, etc., and due to the limitations of cost and physical space, the size of L1 cache is usually relatively small; Level 2 cache (L2 cache): L2 cache is usually larger than L1 cache, but the access speed is slower than L1 cache; Level 3 cache (L3 cache): L3 cache has a larger capacity than L2 cache and L1 cache, but the access speed is relatively slow, and L3 cache can also be used to store shared data between multiple processing cores.

[0034] Many-core systems can process large-scale data and complex tasks in parallel, but the computing speed of the processor and the memory access speed may not match, which affects the computing performance and system power consumption. In related technologies, multi-level cache technology can be used. During hardware design, the location, size, and link relationship of each level of cache are fixed in the processor, that is, the designed multi-level cache system is provided to all processing cores as part of the chip hardware logic circuit, which requires additional hardware resources to be divided from the processor. Moreover, different processing cores in the many-core system may have different execution tasks, and different tasks may have different requirements for the multi-level cache system. The fixed multi-level cache system may also limit the performance of the many-core system.

[0035] According to the cache system and cache processing method of the embodiments of the present disclosure, the first cache area can be divided from the target storage areas of multiple processing cores according to the multi-level cache configuration information of the first processing core, so that the first cache areas of multiple different levels are divided, i.e., the multi-level cache system of the first processing core is constituted. In this way, the multi-level cache system of the processing core can be flexibly configured according to the multi-level cache configuration information, and a multi-level cache system that is more suitable for the tasks performed by the processing core can be obtained, which is more targeted and flexible, thereby improving the overall performance. Moreover, the multi-level cache system is configured based on the resources of the target storage area of ​​the processing core itself, and there is no need to occupy other hardware resources in the processor, thereby saving hardware resource consumption. When the first processing core receives a data access request, it can search and obtain from the multi-level cache system of the first processing core, thereby improving data access speed and efficiency.

[0036] The cache system and cache processing method according to the embodiments of the present disclosure can be applied to a many-core system, which includes multiple processing cores. Based on the hardware architecture of the processing cores of the many-core system, a multi-level cache system for each processing core can be flexibly configured, and the cache processing method can be executed by the many-core system.

[0037] Figure 1 A schematic diagram of the hardware architecture of a many-core system provided in an embodiment of the present disclosure.

[0038] like Figure 1 As shown, the many-core system includes multiple processing cores, each processing core has a private target storage area, for example, the target storage area is a static random access memory (SRAM), and each processing core can communicate with each other through an on-chip network.

[0039] based on Figure 1In the many-core system shown in the embodiment of the present disclosure, a corresponding multi-level cache system can be configured according to the needs of each processing core, and different processing cores execute different computing tasks in parallel. Specifically, in the embodiment of the present disclosure, a cache system is provided, which includes: multiple processing cores and a configuration module, the processing core includes a target storage area, and the multiple processing cores are processing cores on the many-core chip, wherein:

[0040] 1) A configuration module, used to determine the multi-level cache configuration information of the first processing core, and divide the first cache area from the target storage area of ​​the multiple processing cores according to the multi-level cache configuration information, the first cache areas corresponding to the multiple processing cores constitute the multi-level cache system of the first processing core, and the processing cores where the first cache areas of different levels are located are related to the position information of the first processing core, and the first processing core is any one of the multiple processing cores.

[0041] In the embodiment of the present disclosure, the target storage area is located in the private memory of the processing core, for example, Figure 1 As shown, the target storage area may be a private SRAM of the processing core.

[0042] Or the target memory area is located in the local shared memory area or global shared memory area of ​​multiple processing cores, for example Figure 2 FIG. 1 is a schematic diagram of the hardware architecture of another multi-core system in an embodiment of the present disclosure. Figure 2 As shown, multiple processing cores may also have local shared memory areas and global shared memory areas. Furthermore, when dividing, the first cache area may be divided from the local shared memory area or the global shared memory area according to the multi-level cache configuration information. For example, the first-level cache in the multi-level cache system of processing core 0 may be divided from the local shared memory area corresponding to the processing core 0.

[0043] Among them, for determining the multi-level cache configuration information of the first processing core, the present disclosure provides several possible embodiments:

[0044] In a possible embodiment, the configuration module is used to determine the multi-level cache configuration information of the first processing core based on task information of the task executed by the first processing core, storage resource information of the target storage area in multiple processing cores, and location information between the first processing core and multiple processing cores.

[0045] In the disclosed embodiment, the task information may include information such as the amount of data associated with the task and the computing speed. The position information between the first processing core and the other multiple processing cores represents the hardware position relationship, position distance and other information between the processing cores in the many-core system.

[0046] In this way, in the embodiment of the present disclosure, the multi-level cache system of the processing core can be dynamically configured according to the requirements of the processing core's execution tasks, which is more flexible and can better meet the task requirements of each processing core, thereby improving system performance.

[0047] In a possible embodiment, the configuration module is used to: obtain an input configuration instruction, and determine the multi-level cache configuration information of the first processing core indicated in the configuration instruction.

[0048] That is, in the embodiments of the present disclosure, the user can also pre-configure the multi-level cache configuration information of each processing core. Specifically, during the configuration, the user can also make configuration based on comprehensive considerations such as the execution task requirements of the processing core, the hardware location layout of the processing core in the many-core system, the storage resource information of the target storage area in the processing core, etc. Furthermore, for example, during the compilation stage, a configuration instruction containing the multi-level cache configuration information for the first processing core can be input, that is, the multi-level cache system of the first processing core can be configured according to the multi-level cache configuration information.

[0049] Furthermore, in the embodiments of the present disclosure, the multi-level cache configuration information of the first processing core can also be determined in combination with the above-mentioned two embodiments. For example, during the compilation phase, the compiler can statically determine and configure the multi-level cache system of the first processing core according to the configuration instructions. This can be used as the initial design state of the multi-level cache system of the first processing core. Then, during the operation phase, the multi-level cache system of the first processing core can be dynamically determined and adjusted in real time based on the task information of the first processing core, the current storage resource information of the target storage area of ​​the processing core, etc. In this way, the flexibility and performance of the design of the multi-level cache system for different processing cores can be further improved.

[0050] In the embodiment of the present disclosure, the multi-level cache configuration information includes the number of levels of the multi-level cache system, the location of each level cache area and the size of each level cache area. Then, when dividing the first cache area from the target storage area of ​​multiple processing cores according to the multi-level cache configuration information, the configuration module is used to: divide the first cache area from the target storage area of ​​the processing core corresponding to the location of each level cache area according to the number of levels and the processing cores corresponding to the location of each level cache area, and according to the size of each level cache area, and determine the link information between each first cache area.

[0051] Among them, multiple first cache areas are cache areas of different levels in a multi-level cache system. First cache areas belonging to the same level can be located in the target storage area of ​​one or more processing cores, and first cache areas belonging to different levels can also be located in the same processing core or in the target storage area of ​​different processing cores.

[0052] For example, see Figure 3 As shown, it is a schematic diagram of a cache system in an embodiment of the present disclosure. Figure 3 As shown, the first processing core is processing core 0, the number of levels of the multi-level cache system of processing core 0 is four, and the first-level cache area is located in the target storage area of ​​processing core 0, the second-level cache area is divided into two, respectively located in the target storage areas of processing cores 3 and 4, the third-level cache area is divided into three, respectively located in the target storage areas of processing cores 5, 6 and 7, the fourth-level cache area is located in the target storage area of ​​processing core 8, and the link information between cache areas of different levels is as shown in FIG. Figure 3 The arrows in the figure indicate the link relationship.

[0053] 2) The first processing core is used to search and obtain the data indicated in the data access request from the multi-level cache system of the first processing core when receiving the data access request.

[0054] Specifically, the present disclosure provides a possible embodiment, which queries the first-level cache area included in the multi-level cache system of the first processing core according to the data address in the data access request. If the data is found, the data indicated in the data access request is obtained from the first-level cache area. If the data is not found, the next-level cache area linked to the first-level cache area is queried according to the link information corresponding to the first-level cache area to determine the queried target cache area, and the data indicated in the data access request is obtained from the target cache area.

[0055] For example, Figure 3 As shown, in response to a data access request of processing core 0, processing core 0 first accesses the first-level cache area in the multi-level cache system of processing core 0, that is, the L1cache deployed in processing core 0. If the data is not found in L1cache, the link information in L1cache is queried to determine that the next-level L2 cache with a link relationship is located in processing core 3 and processing core 4. Processing core 0 simultaneously sends the data address of the data to be queried to processing core 3 and processing core 4. If one of processing core 3 and processing core 4 finds the data, the found data and query hit information are returned to processing core 0, and then processing core 0 sends a termination search information to processing core 3 and processing core 4. If the data is not found in both processing core 3 and processing core 4, the next-level cache area can be accessed according to the above steps.

[0056] In the disclosed embodiment, a flexible multi-level cache system configuration is provided for a many-core system. According to the multi-level cache configuration information of the first processing core, a first cache area can be divided from the target storage area of ​​the multiple processing cores. The first cache areas corresponding to the multiple processing cores constitute the multi-level cache system of the first processing core. In this way, the required multi-level cache system can be flexibly configured according to the needs of different processing cores, which not only improves the performance and flexibility of the many-core system, but also improves the performance of the multi-level cache system. Furthermore, when the first processing core receives a data access request, it can search and obtain the corresponding data from the multi-level cache system of the first processing core, which can improve data acquisition efficiency.

[0057] The cache system in the embodiment of the present disclosure is further described below.

[0058] In the embodiment of the present disclosure, the first cache area divided from the target storage area of ​​the processing core can be further divided to be able to store different information in a more subdivided manner, thereby improving data storage and reading efficiency. In a possible embodiment, the first cache area includes a link area and a cache data area, wherein the cache data area is used to store target data of the task executed by the first processing core; the link area is used to store link information of the next-level cache area corresponding to the current-level cache area, and the link information includes the location of the next-level cache area and the data address range of the target data stored in the next-level cache area.

[0059] In addition, in order to identify the data address of the target data stored in each cache area, a tag area is also configured in the cache system in the embodiment of the present disclosure. In a possible embodiment, the tag area is located in the first cache area of ​​the first processing core, and the tag area is used to store the data address of the target data stored in the corresponding first cache area.

[0060] In a possible embodiment, the tag area is located in a shared area of ​​multiple processing cores, and the tag area is used to store data addresses of target data stored in the first cache areas of the multiple processing cores associated with the shared area.

[0061] In the disclosed embodiment, the tag area and the cache data area can be configured in the same processing core, which can improve the query efficiency, and the tag area and the cache data area can also be configured in different processing cores, so that the cache data areas of different processing cores can share a tag area, thereby saving the storage caused by the tag. However, it should be noted that when multiple processing cores share the tag area, it is also necessary to add a link area in the cache area of ​​the processing core to record the location of the tag area corresponding to the cache data area, so as to be able to accurately find the data address of the target data stored in the cache data area.

[0062] Furthermore, in addition to being divided into a first cache area, the target storage area in the embodiment of the present disclosure may also be divided into a random access memory area, where the random access memory area is used to store data statically allocated during compilation.

[0063] For example, see Figure 4 FIG. 1 is a schematic diagram of a target storage area division in an embodiment of the present disclosure, taking the tag area being located in the first cache area of ​​each processing core as an example. Figure 4 As shown, the target storage area can be divided into a first cache area and a random access memory area. The first cache area can be further divided into a link area, a tag area and a cache data area. The tag area is used to store data addresses, the cache data area is used to store target data, and the link area is used to store link information of the next level cache area corresponding to the cache area.

[0064] In this way, in the embodiment of the present disclosure, the target storage area of ​​the processing core is divided into a cache area and a random access memory area. For the data stored in the random access memory area, the processing core can use a method similar to using the main memory to directly access the data therein through the address, while the cache area can be accessed through the cache mechanism. There may be data missing in the cache area. At this time, if the data is not queried from the multi-level cache system of the processing core, the random access memory area or the main memory outside the processing core can be queried to ensure that the required data can be obtained.

[0065] It should be noted that the embodiments of the present disclosure do not limit the configuration of the multi-level cache system, and specifically provide several possible embodiments.

[0066] In a possible embodiment, a cache area at the same level includes multiple sub-caches, and the multiple sub-caches are respectively located in target storage areas of different processing cores. Then, the link information between the first cache areas at different levels in the multi-level cache system is in a tree structure or an anti-tree structure, and the link information of the next-level cache area stored in the link information is the link information of the sub-caches in the next-level cache area that have connecting edges in the tree structure or the anti-tree structure.

[0067] In the embodiments of the present disclosure, for example, the remaining storage resources in the target storage area of ​​a processing core may be insufficient, and the access speeds of cache areas based on different levels are different, and the location distribution has distance requirements. Therefore, the cache area of ​​the same level can also be split into multiple sub-caches, and deployed to the target storage areas of different processing cores respectively, which can improve the configuration flexibility of the multi-level cache system. However, there may be many link relationships between two adjacent levels, which may cause data query to be too complicated. Therefore, in the case where the cache area of ​​the same level includes multiple sub-caches, in the embodiments of the present disclosure, a multi-level cache system with a tree structure or an anti-tree structure can be adopted. In this way, the link area in the processing core only needs to store the link information of some sub-caches in the next level, rather than the link information of all sub-caches in the next level, which can improve data query and access efficiency.

[0068] For example, see Figure 5 As shown, a multi-level cache system with a tree-like or anti-tree-like structure in an embodiment of the present disclosure is shown. Figure 5 As shown in the figure, if the L2 cache is distributed on 2 processing cores, the L3 cache is distributed on 4 processing cores, and the L4 cache is distributed on 2 processing cores, there are 8 cache connection edges between L2 and L3, which is likely to cause cache search signal explosion. Therefore, a multi-level cache system with a tree or anti-tree structure is adopted. The link area of ​​each processing core only needs to record the link information of the sub-cache area connected to the next-level cache area, rather than all the sub-cache areas corresponding to the next-level cache area, such as Figure 7 In the tree structure, in the link area of ​​the second-level sub-cache area 1 corresponding to L2cache, only the link information of the third-level sub-cache area 1 and the third-level sub-cache area 2 corresponding to L3cache needs to be stored, and as Figure 7 As shown, it can also be an inverse tree structure, that is, many-to-one. In this case, the link area of ​​a sub-cache area only needs to record the link information of the sub-cache areas with connection relationship in the next-level cache area.

[0069] In one possible embodiment, the target storage area of ​​the processing core includes one or more first cache areas, and the multiple first cache areas represent cache areas of different levels in the multi-level cache system of the first processing core; or the target storage area of ​​the processing core also includes second cache areas in the multi-level cache systems of other processing cores; then the link area is also used to store a cache page table, and the cache page table is used to record the core identifier of the processing core to which each cache area included in the target storage area of ​​the processing core belongs, as well as the level identifier to which it belongs.

[0070] For example, see Figure 6 As shown, it is a schematic diagram of multiple cache areas and cache page tables in an embodiment of the present disclosure, such as Figure 6As shown, the target storage area of ​​a processing core can be divided into multiple cache areas and random access memory areas. The multiple cache areas include, for example, cache area 1, cache area 2, and cache area 3. The multiple cache areas can be in a multi-level cache system centered on different processing cores, or can also be different levels of a multi-level cache system of a processing core. For example, cache area 1 is the second-level cache area in the multi-level cache system of processing core 0, cache area 2 is the third-level cache area in the multi-level cache system of processing core 0, and cache area 3 is the second-level cache area in the multi-level cache system of processing core 1.

[0071] Furthermore, in the embodiments of the present disclosure, a cache page table can be used in the processing core to record which level in the multi-level cache area of ​​which processing core each cache area corresponds to. In this way, recording in the form of a cache page table is clearer and simpler. When performing data access queries, it is possible to quickly indicate that the query is to be performed in the correct cache area, thereby improving efficiency.

[0072] In a possible embodiment, in the embodiment of the present disclosure, a multi-level cache system can also be configured based on the hardware architecture of multiple processing cores in the many-core system. Specifically, multiple processing cores are divided into m*n grids according to location information, each grid includes at least one processing core, and the processing cores in the same grid share the same level of cache area; the configuration module is used to:

[0073] 1) Based on the divided m*n grids, with the first grid where the first processing core is located as the center, a first cache area is divided from the target storage area of ​​the processing core included in the first grid to serve as a first-level cache area. 2) According to a preset adjacent routing rule, it is determined that the first grid corresponds to a second grid that meets the adjacent routing rule, and the first cache area is divided from the target storage area of ​​the processing core included in the second grid to serve as a second-level cache area, and the first grid is continued to be the center until the number of levels is met, and a multi-level cache system for the first processing core is obtained, wherein the multi-level cache system includes at least a first-level cache area and a second-level cache area.

[0074] Among them, the target storage area of ​​the processing core where the first-level cache area and the second-level cache area are located meets the storage resource conditions. For example, if a processing core is determined for dividing the second-level cache area according to the adjacent routing rules, and the storage resources in the target storage area of ​​the processing core are relatively small, or the data to be stored in the random access memory area of ​​the processing core itself exceeds a certain threshold, it may not be enough to divide a cache area of ​​a suitable size. Therefore, the processing core can be used without using the cache area, so that the random access memory area in the processing core can be used normally.

[0075] The adjacent routing rules can be adjacent grids in the upper, lower, left, right, or diagonal directions, etc., which are not limited in the embodiments of the present disclosure. It can be understood that in the multi-level cache system of the first processing core, the smaller the number of levels of the cache area, the grid of the processing core where it is located is usually closer to the position of the first grid.

[0076] For example, see Figure 7 FIG. 1 is a schematic diagram of a multi-level cache system divided into a grid in an embodiment of the present disclosure, where multiple processing cores in a multi-core system are divided into m*n grids, such as Figure 7 As shown, each box represents a processing core. For example, each grid includes two processing cores. i,j represents all processing cores contained in the i-th row and j-th column of the grid, G i,j All processing cores in a processor can share the same level of cache, for example, Figure 7 China-Israel 3,2 The grid is centered, G 3,2 The two processing cores in the processor share the L1 cache.

[0077] And, with G i,j Centered on G i,j The target storage area of ​​the processing core is divided into a first-level cache area and a G i,j A grid with a one-hop distance can be used as a second grid that complies with the adjacent routing rule. For example, the second grid includes G i-1,j , G i+1,j , G i,j-1 , G i,j+1 ,like Figure 7 As shown, Figure 7 In order to more clearly describe the cache areas at different levels, different grayscale colors of the boxes are used to distinguish the cache areas at different levels, such as Figure 7 In, G 3,2 The second grid corresponding to the grid is the adjacent grids above, below, left and right. The secondary cache area is divided from the target storage area of ​​the processing core included in the second grid. Similarly, i,j The next adjacent third grid, for example, Figure 7 As shown, it can be determined that G 3,2 The third grid corresponding to the grid, such as the third grid includes G i-1,j-1 , G i+1,j-1 , G i-1,j+1 , G i-1,j+1 and divide the third-level cache area from the target storage area of ​​the processing core included in the third grid,

[0078] Then we can get G i,j A multi-level cache system centered on G i,j The processing cores in the system can correspond to the same multi-level cache system.

[0079] For example, see Figure 8 FIG. 1 is a schematic diagram of another multi-level cache system divided into grids in an embodiment of the present disclosure. For example, i,j Centered on G i,j The target storage area of ​​the processing core is divided into a first-level cache area. If the second network that meets the adjacent routing rule includes grids at upper, lower, left, right, and diagonal positions, then Figure 8 As shown, the determined second grid includes: G i-1,j , G i+1,j , G i,j-1 , G i,j+1 , G i-1,j-1 , G i+1,j-1 , G i-1,j+1 , G i-1,j+1 , and the determined third grid includes G i-2,j-1 , G i-1,j , G i-2,j+1 , G i+2,j-1 , G i+2,j , G i+2,j+1 .

[0080] In addition, in the embodiment of the present disclosure, when determining other grids that conform to the adjacent routing rule corresponding to the first grid, if it is determined that the storage resources of the target storage area of ​​the processing core in the other grids that conform to the adjacent routing rule do not meet the requirements, or the data to be stored in the random access storage area of ​​the other grids themselves exceeds a certain threshold, then the other grids that conform to the adjacent routing rule may not be used for cache partitioning. For example, refer to Fig. 9 FIG. 1 is a schematic diagram of another multi-level cache system divided into grids in an embodiment of the present disclosure, with G 3,2 The grid is centered. If G 3,1 and G 4,3 If the storage resource condition is not met, it can be not used, and the second-level cache area or the third-level cache area can be divided from other grids that meet the adjacent routing rules.

[0081] In this way, in the embodiments of the present disclosure, a multi-level cache system can be configured based on the hardware deployment architecture of multiple processing cores in the many-core system without occupying additional hardware resources, and the performance of the multi-level cache system is improved by comprehensively considering factors such as location and storage resources.

[0082] Based on the cache system in the embodiment of the present disclosure, Fig.10 A flowchart of a cache processing method provided by an embodiment of the present disclosure. Fig.10 , the method comprising:

[0083] S1010: Determine multi-level cache configuration information of a first processing core.

[0084] S1020: Divide the first cache area from the target storage area of ​​the multiple processing cores according to the multi-level cache configuration information, the first cache areas divided corresponding to the multiple processing cores constitute a multi-level cache system of the first processing core, and the processing cores where the first cache areas of different levels are located are related to the location information of the first processing core.

[0085] Furthermore, when the first processing core accesses data during the execution of a task, it can preferentially query from the multi-level cache system of the first processing core to improve data access efficiency. Specifically, the present disclosure also provides a possible implementation method, including: receiving a data access request, the data access request includes at least a data address, and the data access request is received by the first processing core; according to the data address, searching and obtaining the data indicated in the data access request from the multi-level cache system of the first processing core.

[0086] It should be noted that the cache processing method in the embodiment of the present disclosure involves configuration and a multi-level cache system, which is the same as the description of the cache system in the above embodiment, and will not be repeated here.

[0087] In this way, in the embodiments of the present disclosure, the flexibility of the many-core system can be fully utilized to dynamically and flexibly configure the corresponding multi-level cache system for the processing core, so as to better meet the computing and data access requirements of the processing core itself and improve the system performance. Furthermore, when accessing data, it can be queried and obtained from the corresponding multi-level cache system, which improves the data access efficiency and also improves the performance of the processing core in executing tasks.

[0088] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not repeat them. It can be understood by those skilled in the art that in the above-mentioned method of the specific implementation method, the specific execution order of each step should be determined according to its function and possible internal logic.

[0089] In addition, the present disclosure also provides electronic devices, computer-readable storage media, and computer program products, all of which can be used to implement any cache processing method provided by the present disclosure. The corresponding technical solutions and descriptions are referred to the corresponding records in the method part and will not be repeated here.

[0090] Fig.11 A block diagram of an electronic device provided in an embodiment of the present disclosure.

[0091] Reference Fig.11 An embodiment of the present disclosure provides an electronic device, which includes multiple processing cores 1101 and an on-chip network 1102, wherein the multiple processing cores 1101 are connected to the on-chip network 1102, and the on-chip network 1102 is used to exchange data between the multiple processing cores and external data.

[0092] One or more instructions are stored in one or more processing cores 1101 , and the one or more instructions are executed by one or more processing cores 1101 , so that the one or more processing cores 1101 can execute the above-mentioned cache processing method.

[0093] In some embodiments, the electronic device may be a brain-like chip, which can use vectorized computing and needs to load the weight information and other parameters of the neural network model through an external memory such as a double data rate (DDR) synchronous dynamic random access memory. Therefore, the batch processing used in the embodiments of the present disclosure has a higher computing efficiency.

[0094] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the cache processing method described above when executed by a processor. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0095] The embodiment of the present disclosure also provides a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above-mentioned cache processing method.

[0096] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0097] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0098] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0099] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0100] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0101] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0102] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0103] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0104] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0105] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A cache system, characterized in that: The system comprises a plurality of processing cores and a configuration module, wherein the processing core comprises a target storage area: The configuration module is used to determine multi-level cache configuration information of the first processing core, and divide the first cache area from the target storage area of ​​the multiple processing cores according to the multi-level cache configuration information, the first cache areas corresponding to the multiple processing cores constitute the multi-level cache system of the first processing core, and the processing cores where the first cache areas of different levels are located are related to the position information of the first processing core, and the first processing core is any one of the multiple processing cores; The first processing core is used to search and obtain the data indicated in the data access request from the multi-level cache system of the first processing core when receiving the data access request.

2. The system according to claim 1, characterized in that The multiple processing cores are processing cores on a many-core chip; wherein different processing cores execute different computing tasks in parallel.

3. The system according to claim 1, characterized in that The configuration module is used to determine the multi-level cache configuration information of the first processing core according to the task information of the task executed by the first processing core, the storage resource information of the target storage area in the multiple processing cores, and the position information between the first processing core and the multiple processing cores; Alternatively, the configuration module is used to: obtain an input configuration instruction, and determine the multi-level cache configuration information of the first processing core indicated in the configuration instruction.

4. The system according to any one of claims 1 to 3, characterized in that: The multi-level cache configuration information includes the number of levels of the multi-level cache system, the location of each level cache area, and the size of each level cache area; The configuration module is used to: divide the first cache area from the target storage area of ​​the processing core corresponding to the location of each level cache area according to the number of levels, the processing core corresponding to the location of each level cache area, and the size of each level cache area, and determine the link information between each of the first cache areas.

5. The system according to claim 4, characterized in that The first cache area includes a link area and a cache data area, wherein: The cache data area is used to store target data of the task executed by the first processing core; The link area is used to store link information of a next-level cache area corresponding to a current-level cache area, and the link information includes a location of the next-level cache area and a data address range of target data stored in the next-level cache area.

6. The system according to claim 5, characterized in that If the cache area of ​​the same level includes multiple sub-cache areas, and the multiple sub-cache areas are respectively located in the target storage areas of different processing cores, then the link information between the first cache areas of different levels in the multi-level cache system is in a tree structure or an anti-tree structure, and the link information of the next-level cache area stored in the link information is the link information of the sub-cache areas in the next-level cache area that have connecting edges in the tree structure or anti-tree structure.

7. The system according to claim 5, characterized in that The target storage area of ​​the processing core includes one or more first cache areas, and the plurality of first cache areas represent cache areas at different levels in a multi-level cache system of the first processing core; Or the target storage area of ​​the processing core also includes the second cache area in the multi-level cache system of other processing cores; The link area is further used to store a cache page table, and the cache page table is used to record the core identifier of the processing core to which each cache area included in the target storage area of ​​the processing core belongs, and the level identifier to which it belongs.

8. The system according to claim 5, characterized in that The system also includes a label area; Wherein, the tag area is located in the first cache area of ​​the first processing core, and the tag area is used to store the data address of the target data stored in the corresponding first cache area; Alternatively, the tag area is located in a shared area of ​​multiple processing cores, and the tag area is used to store data addresses of target data stored in the first cache areas of the multiple processing cores associated with the shared area.

9. The system according to claim 4, characterized in that The multiple processing cores are divided into m*n grids according to the location information, each grid includes at least one processing core, and the processing cores in the same grid share the cache area of ​​the same level; the configuration module is used to: According to the divided m*n grids, with the first grid where the first processing core is located as the center, a first cache area is divided from the target storage area of ​​the processing core included in the first grid to serve as a first-level cache area; According to a preset adjacent routing rule, it is determined that the first grid corresponds to a second grid that complies with the adjacent routing rule, and a first cache area is divided from a target storage area of ​​a processing core included in the second grid to serve as a secondary cache area. The first grid is continued to be taken as the center until the number of levels is met, thereby obtaining a multi-level cache system for the first processing core, wherein the multi-level cache system includes at least the first-level cache area and the second-level cache area.

10. The system according to claim 1, characterized in that The target storage area is located in a private memory of a processing core, or the target storage area is located in a local shared storage area or a global shared storage area of ​​a plurality of processing cores.

11. A cache processing method, characterized in that: Applied to the cache system according to any one of claims 1 to 10, the method comprises: Determining multi-level cache configuration information of the first processing core; According to the multi-level cache configuration information, a first cache area is divided from the target storage area of ​​multiple processing cores, and the first cache areas corresponding to the multiple processing cores constitute a multi-level cache system of the first processing core, and the processing cores at different levels where the first cache areas are located are related to the location information of the first processing core.

12. The method according to claim 11, characterized in that The method further comprises: receiving a data access request, wherein the data access request includes at least a data address, and the data access request is received by the first processing core; According to the data address, the data indicated in the data access request is searched and obtained from the multi-level cache system of the first processing core.

13. An electronic device, characterized in that: include: Multiple processing cores; as well as An on-chip network is configured to exchange data between the multiple processing cores and external data; wherein one or more instructions are stored in one or more of the processing cores, and one or more of the instructions are executed by one or more of the processing cores, so that one or more of the processing cores can execute the cache processing method described in any one of claims 11-12.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the computer program implements the cache processing method according to any one of claims 11 to 12.

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