Keyboard circuit with multiple keys and key value reading method

Abstract

The invention discloses a keyboard circuit with multiple keys. The keyboard circuit comprises an I / O port expansion circuit, a key circuit and an external interface circuit, the I / O port expansion circuit is respectively connected with the key circuit and the external interface circuit; the I / O port expansion circuit is also connected with the I / O port of the CPU; the I / O port expansion circuit is used for expanding an I / O port of the CPU, acquiring a key signal of the key circuit and transmitting the key signal to the CPU through the I / O port; the I / O port expansion circuit at least expands two groups or more than two groups of parallel input and output I / O ports; the key circuit is used for collecting key signals and transmitting the key signals to the I / O port expansion circuit. The invention further provides a key value reading method of the keyboard circuit with the multiple keys. The keyboard circuit solves the technical problems of high I / O port resource occupation and slow key value reading response of an existing keyboard circuit CPU.

Description

Technical Field

[0001] The present invention relates to the field of key technology, and in particular to a keyboard circuit of multiple keys and a key value reading method. Background Art

[0002] Simple buttons are generally designed directly using the I / O port. When the button is pressed, the level of the I / O port changes. For example, all I / O ports are pulled up, and one end of the button is grounded. When the button is pressed, the level of the I / O port can be pulled from a high level to a low level. The CPU can read the corresponding I / O port level by scanning the I / O port and confirm which button is pressed.

[0003] At present, since the number of buttons on power products is relatively small, there are generally two ways to achieve it. The first way is to use AD sampling to read the button value. The keyboard uses the principle of AD sampling. Every time a button is pressed, the voltage of AD sampling will be different, so as to distinguish which button is pressed. The characteristic of this method is that the number of buttons is determined by the accuracy of AD sampling, that is, the number of AD bits carried by the CPU; the second way is to use the I / O port to directly press the button. Pressing the button changes the level of the I / O port, and the CPU reads the value of the I / O port. This method is simple and direct, but it occupies more I / O port resources. One button occupies one I / O port. For example, the patent document with application number 201721685645.9 discloses a capacitive sensing button circuit. The keys currently used in large quantities are all in the second mode, which reads the key value through the I / O port. If several keys are used, the same number of I / O ports need to be designed. The CPU regularly scans each I / O port to read the key value. When there are many keys in use, such as 20-bit keys, a large number of I / O ports will be occupied, that is, 20 I / O port resources will be used, which greatly wastes the I / O port resources of the CPU. At the same time, the scanning method is adopted, and the scanning time is long and the key response time is long, which also greatly wastes the CPU resources. Therefore, it is urgent to propose a keyboard circuit with multiple keys and a key value reading method to solve the technical problems of high I / O port resource occupation of the CPU of the existing keyboard circuit and slow key value reading response. Summary of the invention

[0004] The main purpose of the present invention is to provide a keyboard circuit with multiple keys and a key value reading method, aiming to solve the technical problems of high I / O port resource occupancy of the CPU of the existing keyboard circuit and slow key value reading response.

[0005] To achieve the above object, the present invention provides a keyboard circuit with multiple keys, wherein the keyboard circuit with multiple keys comprises:

[0006] I / O port expansion circuit, key circuit and external interface circuit;

[0007] The I / O port expansion circuit is connected to the key circuit and the external interface circuit respectively; the I / O port expansion circuit is also connected to the I / O port of the CPU;

[0008] The I / O port expansion circuit is used to expand the I / O port of the CPU, and to obtain the key signal of the key circuit, and transmit the key signal to the CPU through the I / O port; the I / O port expansion circuit at least expands two or more groups of parallel input and output I / O ports;

[0009] The key circuit is used to collect key signals and transmit the key signals to the I / O port expansion circuit.

[0010] In one of the preferred solutions, the I / O port expansion circuit includes an expansion chip D2;

[0011] Pin 1 of the expansion chip D2 is connected to the interrupt interface of the CPU;

[0012] Pins 2, 3, 12, and 21 of the expansion chip D2 are grounded;

[0013] Pins 4, 5, 6, and 7 of the expansion chip D2 are connected to the output end of the keyboard circuit;

[0014] Pins 16, 17, 18, 19, and 20 of the expansion chip D2 are connected to the input end of the keyboard circuit;

[0015] Pins 22 and 23 of the expansion chip D2 are respectively connected to the second pull-up circuit and the external interface circuit;

[0016] Pin 24 of the expansion chip D2 is connected to the first protection circuit.

[0017] In one of the preferred solutions, the first protection circuit includes a capacitor C1, a TVS tube V1, and a bidirectional anti-static tube D1;

[0018] One end of the capacitor C1 is connected to the 24-pin of the expansion chip D2 and the power supply end respectively, and the other end of the capacitor C1 is connected to the bidirectional antistatic tube D1, the TVS tube V1 and the ground end respectively, and the other ends of the bidirectional antistatic tube D1 and the TVS tube V1 are connected to the power supply end.

[0019] In one of the preferred embodiments, the second pull-up circuit includes a resistor R6 and a resistor R7; one end of the resistor R6 is connected to the resistor R7 and the power supply end respectively, the other end of the resistor R6 is connected to the pin 23 of the extension chip D2, and the other end of the resistor R7 is connected to the pin 22 of the extension chip D2.

[0020] One of the preferred schemes, the key circuit includes a first pull-up circuit, a multi-bit key circuit and a third protection circuit; one end of the first pull-up circuit is connected to the power supply end, the other end of the first pull-up circuit is connected to the multi-bit key circuit, the multi-bit key circuit is respectively connected to the I / O port expansion circuit and the third protection circuit, and the other end of the third protection circuit is grounded.

[0021] In one of the preferred solutions, the multi-bit key circuit adopts an M×N matrix multi-bit key circuit; wherein M is the number of rows of keys in the key circuit, 1<M≤8, and N is the number of columns of keys in the key circuit, 1<N≤8.

[0022] In one preferred solution, the multi-bit key circuit adopts a 5×4 matrix multi-bit key circuit;

[0023] The 5×4 matrix multi-bit key circuit includes a key K1, a key K2, ..., a key K20;

[0024] Pins 1 and 3 of the button K1, button K2, ..., button K20 are respectively connected to the first pull-up circuit, the third protection circuit and the I / O port expansion circuit, and pins 2 and 4 of the button K1, button K2, ..., button K20 are connected to the I / O port expansion circuit.

[0025] In one of the preferred solutions, the third protection circuit includes a capacitor C2; one end of the capacitor C2 is connected to the I / O port expansion circuit and the multi-bit key circuit respectively, and the other end of the capacitor C2 is grounded.

[0026] In one of the preferred solutions, the external interface circuit includes a plug XS29;

[0027] Pin 1 of the plug XS29 is connected to a second protection circuit; the second protection circuit includes a capacitor C6, a TVS tube V2 and a bidirectional anti-static tube D3;

[0028] One end of the capacitor C6 is connected to pin 1 of the plug XS29, the power supply end, the bidirectional antistatic tube D3 and the TVS tube V2 respectively, and the other ends of the bidirectional antistatic tube D3, the capacitor C6 and the TVS tube V2 are grounded;

[0029] Pins 2, 3, and 4 of the plug XS29 are connected to the I / O port expansion circuit;

[0030] Pin 5 of the XS29 plug is grounded.

[0031] A method for reading key values ​​of a keyboard circuit including the multi-bit key, comprising the following steps:

[0032] S1, initialize the expansion chip D2 of the I / O port expansion circuit;

[0033] S2, configure the input port and output port of the expansion chip D2, write the row signals ROW_0, ROW_1, ..., ROW_M-1 of the key circuit to 0, read the column signals COL_0, COL_1, ..., COL_N-1 of the key circuit at regular intervals, if a key is pressed, COL_y=0, then the I / O port expansion circuit outputs an interrupt signal and records the value of y in the column signal;

[0034] Among them, ROW_M-1 is the row signal of the M-th row key, M is the number of rows of keys in the key circuit, 1<M≤8, COL_N-1 is the column signal of the N-th column key, N is the number of columns of keys in the key circuit, 1<N≤8, COL_y is the column signal of the y-th column key, 1<y≤8;

[0035] S3. The CPU enters the interrupt service program and operates the expansion chip D2. Specifically, the row signals of the key circuit are assigned 1 one by one. At the same time, the value of the column signal COL_y is read. If the value of the column signal COL_y is 1, the row number and column number of the key at this time are recorded as the coordinates of the pressed key.

[0036] In the above technical solution of the present invention, the keyboard circuit of the multi-key includes: an I / O port expansion circuit, a key circuit and an external interface circuit; the I / O port expansion circuit is respectively connected to the key circuit and the external interface circuit; the I / O port expansion circuit is also connected to the I / O port of the CPU; the I / O port expansion circuit is used to expand the I / O port of the CPU, and to obtain the key signal of the key circuit, and transmit the key signal to the CPU through the I / O port; the I / O port expansion circuit at least expands two or more groups of parallel input and output I / O ports; the key circuit is used to collect key signals and transmit the key signals to the I / O port expansion circuit. The present invention solves the technical problems of high I / O port resource occupation and slow key value reading response of the existing keyboard circuit CPU.

[0037] In the present invention, the I / O port on the CPU is directly expanded through the I / O port expansion circuit, two groups of I / O ports can be expanded, and a key circuit is constructed through the two groups of I / O ports, which only occupies one I / O port and one interrupt interface of the CPU, greatly reducing the number of I / O ports occupied by the CPU, reducing the resource consumption of the CPU, and shortening the response time of the key; at the same time, by reading the key value of the key circuit according to the interrupt signal of the I / O port expansion circuit, it is possible to obtain in real time which key is pressed, thereby reducing the CPU overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0039] Figure 1 A schematic diagram of a keyboard circuit with multiple keys according to an embodiment of the present invention;

[0040] Figure 2 Schematic diagram of an I / O port expansion circuit according to an embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of a key circuit according to an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of an external interface circuit according to an embodiment of the present invention;

[0043] Figure 5 The present invention is a schematic diagram of a method for reading key values ​​of a keyboard circuit with multiple keys according to an embodiment of the present invention.

[0044] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with the implementation methods and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] In addition, in the present invention, the descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0047] Furthermore, the technical solutions between the various embodiments of the present invention may be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in the field. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0048] See also Figure 1-Figure 4According to one aspect of the present invention, the present invention provides a keyboard circuit with multiple keys, wherein the keyboard circuit with multiple keys comprises:

[0049] I / O port expansion circuit, key circuit and external interface circuit;

[0050] The I / O port expansion circuit is connected to the key circuit and the external interface circuit respectively; the I / O port expansion circuit is also connected to the I / O port of the CPU;

[0051] The I / O port expansion circuit is used to expand the I / O port of the CPU, and to obtain the key signal of the key circuit, and transmit the key signal to the CPU through the I / O port; the I / O port expansion circuit at least expands two or more groups of parallel input and output I / O ports;

[0052] The key circuit is used to collect key signals and transmit the key signals to the I / O port expansion circuit.

[0053] Specifically, in this embodiment, the I / O port expansion circuit includes an expansion chip D2;

[0054] Pin 1 of the expansion chip D2 is connected to the interrupt interface of the CPU and the resistor R5 respectively, and the other end of the resistor R5 is connected to the power supply end;

[0055] Pins 2, 3, 12, and 21 of the expansion chip D2 are grounded; the I / O port expansion circuit can determine the address of the IIC bus through pins 2, 3, and 21 of the expansion chip D2. When multiple IIC devices are mounted on the IIC bus of the CPU, the address of the device can be determined through pins 2, 3, and 21 of the expansion chip D2, which is convenient for the CPU to access. When multiple identical I / O expansion circuits are mounted on the IIC bus, the address of the device is determined by different pull-ups and pull-downs of pins 2, 3, and 21 of the expansion chip D2. Different addresses are set for identical devices mounted on the same bus. In the present invention, only one expansion chip is used, so the address is set to 000, that is, pins 2, 3, 12, and 21 of the expansion chip D2 are grounded;

[0056] Pins 4, 5, 6, and 7 of the expansion chip D2 are connected to the output end of the keyboard circuit;

[0057] Pins 16, 17, 18, 19, and 20 of the expansion chip D2 are connected to the input end of the keyboard circuit;

[0058] The 22nd and 23rd pins of the expansion chip D2 are respectively connected to the second pull-up circuit and the external interface circuit; the 22nd and 23rd pins of the expansion chip D2 are also respectively connected to the clock TCK pin and the data TWD pin of the IIC port of the CPU;

[0059] Pin 24 of the expansion chip D2 is connected to the first protection circuit, and pin 24 of the expansion chip D2 is connected to the power supply terminal through the first protection circuit, so as to provide power for the expansion chip D2 to work normally;

[0060] Specifically, in this embodiment, the expansion chip D2 adopts a nanocore microelectronic chip of model NCA9555, and the present invention does not make any specific limitation. Specifically, it only needs to have an IIC interface that can expand two or more I / O ports and have an interrupt signal.

[0061] Specifically, in this embodiment, the first protection circuit includes a capacitor C1, a TVS tube V1, and a bidirectional anti-static tube D1; one end of the capacitor C1 is respectively connected to the 24 pins of the expansion chip D2 and the power supply terminal, and the other end of the capacitor C1 is respectively connected to the bidirectional anti-static tube D1, the TVS tube V1 and the ground terminal, and the other ends of the bidirectional anti-static tube D1 and the TVS tube V1 are connected to the power supply terminal. The first protection circuit can suppress instantaneous overvoltage and protect circuit components from damage by instantaneous surge pulse voltage. At the same time, the bidirectional anti-static tube D1 can realize overvoltage protection of the circuit, and absorb the large current generated by electrostatic discharge to prevent damage to sensitive electronic components caused by static electricity.

[0062] Specifically, in the present embodiment, the second pull-up circuit includes a resistor R6 and a resistor R7; one end of the resistor R6 is respectively connected to the resistor R7 and the power supply end, the other end of the resistor R6 is connected to the 23rd pin of the extension chip D2, and the other end of the resistor R7 is connected to the 22nd pin of the extension chip D2; the pull-up processing is performed by the second pull-up circuit to ensure the stability and reliability of the input signal and improve the anti-interference ability of the circuit.

[0063] Specifically, in this embodiment, the key circuit includes a first pull-up circuit, a multi-bit key circuit and a third protection circuit; one end of the first pull-up circuit is connected to the power supply end, the other end of the first pull-up circuit is connected to the multi-bit key circuit, the multi-bit key circuit is respectively connected to the I / O port expansion circuit and the third protection circuit, and the other end of the third protection circuit is grounded.

[0064] Specifically, in this embodiment, the multi-bit key circuit adopts an M×N matrix multi-bit key circuit; wherein, M is the number of rows of keys in the key circuit, 1<M≤8, and N is the number of columns of keys in the key circuit, 1<N≤8; in the present invention, the number of keys of the multi-bit key circuit is designed to be a matrix multi-bit key circuit of 8×8 at most, and the present invention does not make a specific limitation, and it can be set according to needs.

[0065] Specifically, in this embodiment, the multi-bit key circuit adopts a 5×4 matrix multi-bit key circuit; the 5×4 matrix multi-bit key circuit includes a key K1, a key K2, ..., a key K20;

[0066] Pins 1 and 3 of the button K1 are connected to the resistor R1, the capacitor C5 and the pin 4 of the expansion chip D2 respectively, and pins 2 and 4 of the button K1 are connected to the pin 20 of the expansion chip D2;

[0067] Pins 1 and 3 of the button K2 are connected to the resistor R2, the capacitor C4 and the pin 5 of the expansion chip D2 respectively, and pins 2 and 4 of the button K2 are connected to the pin 20 of the expansion chip D2;

[0068] Pins 1 and 3 of the button K3 are connected to the resistor R3, the capacitor C2 and the pin 6 of the expansion chip D2 respectively, and pins 2 and 4 of the button K3 are connected to the pin 20 of the expansion chip D2;

[0069] Pins 1 and 3 of the button K4 are connected to the resistor R4, the capacitor C3 and the pin 7 of the expansion chip D2 respectively, and pins 2 and 4 of the button K4 are connected to the pin 20 of the expansion chip D2;

[0070] Pins 1 and 3 of the button K5 are connected to the resistor R1, the capacitor C5 and the pin 4 of the expansion chip D2 respectively, and pins 2 and 4 of the button K5 are connected to the pin 19 of the expansion chip D2;

[0071] Pins 1 and 3 of the button K6 are connected to the resistor R2, the capacitor C4 and the pin 5 of the expansion chip D2 respectively, and pins 2 and 4 of the button K6 are connected to the pin 19 of the expansion chip D2;

[0072] Pins 1 and 3 of the button K7 are connected to the resistor R3, the capacitor C2 and the pin 6 of the expansion chip D2 respectively, and pins 2 and 4 of the button K7 are connected to the pin 19 of the expansion chip D2;

[0073] Pins 1 and 3 of the button K8 are connected to the resistor R4, the capacitor C3 and the pin 7 of the expansion chip D2 respectively, and pins 2 and 4 of the button K8 are connected to the pin 19 of the expansion chip D2;

[0074] Pins 1 and 3 of the button K9 are connected to the resistor R1, the capacitor C5 and the pin 4 of the expansion chip D2 respectively, and pins 2 and 4 of the button K9 are connected to the pin 18 of the expansion chip D2;

[0075] Pins 1 and 3 of the button K10 are connected to the resistor R2, the capacitor C4 and the pin 5 of the expansion chip D2 respectively, and pins 2 and 4 of the button K10 are connected to the pin 18 of the expansion chip D2;

[0076] Pins 1 and 3 of the button K11 are connected to the resistor R3, the capacitor C2 and the pin 6 of the expansion chip D2 respectively, and pins 2 and 4 of the button K11 are connected to the pin 18 of the expansion chip D2;

[0077] Pins 1 and 3 of the button K12 are connected to the resistor R4, the capacitor C3 and the pin 7 of the expansion chip D2 respectively, and pins 2 and 4 of the button K12 are connected to the pin 18 of the expansion chip D2;

[0078] Pins 1 and 3 of the button K13 are connected to the resistor R1, the capacitor C5 and the pin 4 of the expansion chip D2 respectively, and pins 2 and 4 of the button K13 are connected to the pin 17 of the expansion chip D2;

[0079] Pins 1 and 3 of the button K14 are connected to the resistor R2, the capacitor C4 and the pin 5 of the expansion chip D2 respectively, and pins 2 and 4 of the button K14 are connected to the pin 17 of the expansion chip D2;

[0080] Pins 1 and 3 of the button K15 are connected to the resistor R3, the capacitor C2 and the pin 6 of the expansion chip D2 respectively, and pins 2 and 4 of the button K15 are connected to the pin 17 of the expansion chip D2;

[0081] Pins 1 and 3 of the button K16 are connected to the resistor R4, the capacitor C3 and the pin 7 of the expansion chip D2 respectively, and pins 2 and 4 of the button K16 are connected to the pin 17 of the expansion chip D2;

[0082] Pins 1 and 3 of the button K17 are connected to the resistor R1, the capacitor C5 and the pin 4 of the expansion chip D2 respectively, and pins 2 and 4 of the button K17 are connected to the pin 16 of the expansion chip D2;

[0083] Pins 1 and 3 of the button K18 are connected to the resistor R2, the capacitor C4 and the pin 5 of the expansion chip D2 respectively, and pins 2 and 4 of the button K18 are connected to the pin 16 of the expansion chip D2;

[0084] Pins 1 and 3 of the button K19 are connected to the resistor R3, the capacitor C2 and the pin 6 of the expansion chip D2 respectively, and pins 2 and 4 of the button K19 are connected to the pin 16 of the expansion chip D2;

[0085] Pins 1 and 3 of the button K20 are connected to the resistor R4, the capacitor C3 and the pin 7 of the expansion chip D2 respectively, and pins 2 and 4 of the button K20 are connected to the pin 16 of the expansion chip D2;

[0086] The keys K1, K2, K3 and K4 are arranged in the same row, the keys K5, K6, K7 and K8 are arranged in the same row, the keys K9, K10, K11 and K12 are arranged in the same row, the keys K13, K14, K15 and K16 are arranged in the same row, the keys K17, K18, K19 and K20 are arranged in the same row; the keys K1, K5, K9, K13 and K17 are arranged in the same column, the keys K2, K6, K10, K14 and K18 are arranged in the same column, the keys K3, K7, K8 and K9 are arranged in the same row, the keys K10, K11 and K12 are arranged in the same row, the keys K13, K14, K15 and K16 are arranged in the same row, the keys K17, K18, K19 and K20 are arranged in the same row; 11. Key K15 and key K19 are arranged in the same column, and key K4, key K8, key K12, key K16 and key K20 are arranged in the same column; pins 4, 5, 6 and 7 of the extension chip D2 correspond to network labels COL_0, COL_1, COL_2 and COL_3 as column coordinates of the keys, respectively, and pins 20, 19, 18, 17 and 16 of the extension chip D2 correspond to network labels ROW_0, ROW_1, ROW_2, ROW_3 and ROW_4 as row coordinates of the keys, respectively. Through this dot matrix form of rows and columns, multiple keys can be accurately controlled and are easy to expand; the present invention forms a matrix multi-bit key circuit with 5 rows and 4 columns through 20 keys.

[0087] Specifically, in this embodiment, the third protection circuit includes a capacitor C2; one end of the capacitor C2 is respectively connected to the I / O port expansion circuit and the multi-bit key circuit, and the other end of the capacitor C2 is grounded; in the present invention, the third protection circuit includes a capacitor C3, a capacitor C2, a capacitor C4 and a capacitor C5; one end of the capacitor C3, a capacitor C2, a capacitor C4 and a capacitor C5 is connected to the multi-bit key circuit, and the other end of the capacitor C3, a capacitor C2, a capacitor C4 and a capacitor C5 is grounded; the third protection circuit improves the stability of the circuit and reduces electromagnetic interference.

[0088] Specifically, in the present embodiment, the first pull-up circuit includes a resistor R1, a resistor R2, a resistor R3 and a resistor R4; one end of the resistor R1, the resistor R2, the resistor R3 and the resistor R4 is connected to the power supply end, and the other end of the resistor R1, the resistor R2, the resistor R3 and the resistor R4 is connected to the multi-bit key circuit; the stability and reliability of the input signal are ensured by the first pull-up circuit, thereby improving the anti-interference ability of the circuit.

[0089] Specifically, in this embodiment, the external interface circuit includes a plug XS29;

[0090] Pin 1 of the plug XS29 is connected to the second protection circuit; the second protection circuit includes a capacitor C6, a TVS tube V2 and a bidirectional anti-static tube D3; one end of the capacitor C6 is respectively connected to pin 1 of the plug XS29, the power supply end, the bidirectional anti-static tube D3 and the TVS tube V2, and the other ends of the bidirectional anti-static tube D3, the capacitor C6 and the TVS tube V2 are grounded; the capacitor C6 is used to improve the stability of the circuit and reduce electromagnetic interference, and the second protection circuit can suppress instantaneous overvoltage and protect circuit components from damage by instantaneous surge pulse voltage. At the same time, the bidirectional anti-static tube D3 is set to realize overvoltage protection of the circuit, and to prevent damage to sensitive electronic components caused by static electricity by absorbing the large current generated by electrostatic discharge.

[0091] Pins 2, 3, and 4 of the plug XS29 are connected to the I / O port expansion circuit;

[0092] Pin 5 of the XS29 plug is grounded.

[0093] See also Figure 5 According to one aspect of the present invention, the present invention provides a key value reading method of a keyboard circuit including the multi-bit key, comprising the following steps:

[0094] S1, initialize the expansion chip D2 of the I / O port expansion circuit;

[0095] S2, configure the input port and output port of the expansion chip D2, write the row signals ROW_0, ROW_1, ..., ROW_M-1 of the key circuit to 0, read the column signals COL_0, COL_1, ..., COL_N-1 of the key circuit at regular intervals, if a key is pressed, COL_y=0, at this time the I / O port expansion circuit outputs the interrupt signal INT_K=0, and records the value of y in the column signal;

[0096] The input port and output port of the expansion chip D2 are configured as follows:

[0097] Configure pins 4, 5, 6, and 7 of the expansion chip D2 as input ports, and configure pins 20, 19, 18, 17, and 16 of the expansion chip D2 as output ports;

[0098] Among them, ROW_M-1 is the row signal of the M-th row key, M is the number of rows of keys in the key circuit, 1<M≤8, COL_N-1 is the column signal of the N-th column key, N is the number of columns of keys in the key circuit, 1<N≤8, COL_y is the column signal of the y-th column key, 1<y≤8;

[0099] S3. The CPU enters the interrupt service program and operates the expansion chip D2. Specifically, the row signals of the key circuit are assigned 1 one by one. At the same time, the value of the column signal COL_y is read. If the value of the column signal COL_y is 1, the row number and column number of the key at this time are recorded as the coordinates of the pressed key.

[0100] Specifically, in this embodiment, the present invention directly expands the I / O port on the CPU through the I / O port expansion circuit, which can expand two groups of I / O ports, and construct a key circuit through the two groups of I / O ports, which only occupies one I / O port and one interrupt interface of the CPU, greatly reducing the number of I / O ports occupied by the CPU, reducing the resource consumption of the CPU, and shortening the response time of the key; at the same time, by reading the key value of the key circuit according to the interrupt signal of the I / O port expansion circuit, it is possible to obtain in real time which key is pressed, reducing the CPU overhead and accurately reading the key value of the key.

[0101] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A keyboard circuit with multiple keys, characterized in that: include: I / O port expansion circuit, key circuit and external interface circuit; The I / O port expansion circuit is connected to the key circuit and the external interface circuit respectively; the I / O port expansion circuit is also connected to the I / O port of the CPU; The I / O port expansion circuit is used to expand the I / O port of the CPU, and to obtain the key signal of the key circuit, and transmit the key signal to the CPU through the I / O port; the I / O port expansion circuit at least expands two or more groups of parallel input and output I / O ports; The key circuit is used to collect key signals and transmit the key signals to the I / O port expansion circuit.

2. A keyboard circuit with multiple keys according to claim 1, characterized in that: The I / O port expansion circuit includes an expansion chip D2; Pin 1 of the expansion chip D2 is connected to the interrupt interface of the CPU; Pins 2, 3, 12, and 21 of the expansion chip D2 are grounded; Pins 4, 5, 6, and 7 of the expansion chip D2 are connected to the output end of the keyboard circuit; Pins 16, 17, 18, 19, and 20 of the expansion chip D2 are connected to the input end of the keyboard circuit; Pins 22 and 23 of the expansion chip D2 are respectively connected to the second pull-up circuit and the external interface circuit; Pin 24 of the expansion chip D2 is connected to the first protection circuit.

3. A keyboard circuit with multiple keys according to claim 2, characterized in that: The first protection circuit includes a capacitor C1, a TVS tube V1, and a bidirectional anti-static tube D1; One end of the capacitor C1 is connected to the 24-pin of the expansion chip D2 and the power supply end respectively, and the other end of the capacitor C1 is connected to the bidirectional antistatic tube D1, the TVS tube V1 and the ground end respectively, and the other ends of the bidirectional antistatic tube D1 and the TVS tube V1 are connected to the power supply end.

4. A keyboard circuit with multiple keys according to claim 2, characterized in that: The second pull-up circuit includes a resistor R6 and a resistor R7; one end of the resistor R6 is connected to the resistor R7 and the power supply end respectively, the other end of the resistor R6 is connected to the pin 23 of the extension chip D2, and the other end of the resistor R7 is connected to the pin 22 of the extension chip D2.

5. A keyboard circuit with multiple keys according to any one of claims 1 to 4, characterized in that: The key circuit includes a first pull-up circuit, a multi-bit key circuit and a third protection circuit; one end of the first pull-up circuit is connected to the power supply end, the other end of the first pull-up circuit is connected to the multi-bit key circuit, the multi-bit key circuit is respectively connected to the I / O port expansion circuit and the third protection circuit, and the other end of the third protection circuit is grounded.

6. A keyboard circuit with multiple keys according to claim 5, characterized in that: The multi-bit key circuit adopts an M×N matrix multi-bit key circuit; wherein M is the number of rows of keys in the key circuit, 1<M≤8, and N is the number of columns of keys in the key circuit, 1<N≤8.

7. A keyboard circuit with multiple keys according to claim 6, characterized in that: The multi-bit key circuit adopts a 5×4 matrix multi-bit key circuit; The 5×4 matrix multi-bit key circuit includes a key K1, a key K2, ..., a key K20; Pins 1 and 3 of the button K1, button K2, ..., button K20 are respectively connected to the first pull-up circuit, the third protection circuit and the I / O port expansion circuit, and pins 2 and 4 of the button K1, button K2, ..., button K20 are connected to the I / O port expansion circuit.

8. A keyboard circuit with multiple keys according to claim 5, characterized in that: The third protection circuit includes a capacitor C2; one end of the capacitor C2 is connected to the I / O port expansion circuit and the multi-bit key circuit respectively, and the other end of the capacitor C2 is grounded.

9. A keyboard circuit with multiple keys according to any one of claims 1 to 4, characterized in that: The external interface circuit includes a plug XS29; Pin 1 of the plug XS29 is connected to a second protection circuit; the second protection circuit includes a capacitor C6, a TVS tube V2 and a bidirectional anti-static tube D3; One end of the capacitor C6 is connected to pin 1 of the plug XS29, the power supply end, the bidirectional antistatic tube D3 and the TVS tube V2 respectively, and the other ends of the bidirectional antistatic tube D3, the capacitor C6 and the TVS tube V2 are grounded; Pins 2, 3, and 4 of the plug XS29 are connected to the I / O port expansion circuit; Pin 5 of the XS29 plug is grounded.

10. A method for reading key values ​​of a keyboard circuit having multiple keys according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1, initialize the expansion chip D2 of the I / O port expansion circuit; S2, configure the input port and output port of the expansion chip D2, write the row signals ROW_0, ROW_1, ..., ROW_M-1 of the key circuit to 0, read the column signals COL_0, COL_1, ..., COL_N-1 of the key circuit at regular intervals, if a key is pressed, COL_y=0, then the I / O port expansion circuit outputs an interrupt signal and records the value of y in the column signal; Among them, ROW_M-1 is the row signal of the M-th row key, M is the number of rows of keys in the key circuit, 1<M≤8, COL_N-1 is the column signal of the N-th column key, N is the number of columns of keys in the key circuit, 1<N≤8, COL_y is the column signal of the y-th column key, 1<y≤8; S3. The CPU enters the interrupt service program and operates the expansion chip D2. Specifically, the row signals of the key circuit are assigned 1 one by one. At the same time, the value of the column signal COL_y is read. If the value of the column signal COL_y is 1, the row number and column number of the key at this time are recorded as the coordinates of the pressed key.

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