Timing violation soft PUF based on carry lookahead adder

Abstract

The invention discloses a time sequence violation soft PUF (Physical Unclonable Function) based on a carry lookahead adder, which is characterized in that an arithmetic operation unit is used as a combinational logic pipeline structure of the carry lookahead adder as a hardware platform, and PUF response output is generated by making a time sequence violation appear in the combinational logic pipeline structure; the method has the advantages that any other hardware circuit does not need to be additionally designed and added, the PUF response capable of representing hardware characteristics can be extracted by improving the clock frequency of the existing combinational logic pipeline structure to enable time sequence violation to occur in the combinational logic pipeline structure, higher safety is achieved, meanwhile, lower hardware overhead is achieved, hardware resource waste is avoided, and the method is suitable for large-scale popularization and application. And the working efficiency is higher, and the reliability and the uniqueness are better.

Description

Technical Field

[0001] The present invention relates to a soft PUF, and in particular to a timing violation soft PUF based on a carry-lookahead adder. Background Art

[0002] In today's era of booming Internet of Things, information security issues have become increasingly prominent. Some hackers and malicious actors use advanced technologies to try to steal, copy or tamper with these key information, resulting in increasingly serious threats to traditional digital keys and identifiers. Physically Unclonable Function (PUF) is a chip fingerprint extraction technology that uses process deviations in the integrated circuit manufacturing process to achieve data security storage and information exchange authentication. Its unpredictability and non-replicability make PUF widely used in encryption, device authentication, key generation and other fields.

[0003] PUF can be divided into two types: hardware PUF (HPUF) and software PUF (SPUF), depending on whether a dedicated hardware circuit is needed as an entropy source. Hard PUF is usually integrated into a chip and then embedded into the target circuit, or implemented by configuring a special circuit structure in a programmable device such as a field programmable gate array (FPGA). However, with the increasing size of the Internet of Things system, more and more security protection issues for resource-constrained systems have emerged. Traditional hard PUFs that rely on dedicated hardware circuits as entropy sources are no longer applicable, and the demand for soft PUFs is becoming increasingly apparent.

[0004] In recent years, a soft PUF has emerged that uses the path delay information inside the traditional digital multiplier as an entropy source. In digital system design, the multiplier is one of the typical combinatorial logic structural units that perform arithmetic operations, and has a complex data transmission path that is affected by the input signal. The soft PUF uses the input signal of the 32-bit multiplier as the PUF excitation signal, and uses the delay of the internal transmission path of the 32-bit multiplier as the entropy source. The delay of the internal transmission path of the 32-bit multiplier is quantified through a 12-bit time-to-digital converter (TDC), and Bit-5 and Bit-6 of the TDC output bits are selected as the PUF response output of the soft PUF. At the same time, a lightweight dynamic obfuscation algorithm (DOA) and a secure mutual authentication protocol are used to offset modeling attacks.

[0005] Although the soft PUF has high security and obtains PUF response by quantifying the delay of the internal transmission path of the 32-bit multiplier, there is no need to design a hardware circuit to generate an entropy source. However, the 12-bit TDC used to quantify the delay of the internal transmission path of the 32-bit multiplier and the dynamic obfuscation algorithm implemented in hardware occupy a large amount of hardware overhead, and only two bits of the 12-bit TDC output meet the index requirements of the PUF response, resulting in a large waste of hardware resources. In addition, since the internal transmission path and structure of the 32-bit multiplier are relatively complex, and the validity of the transmission path needs to be verified before the TDC outputs the quantized value, the quantization process is complex and time-consuming, which directly affects the efficiency of generating PUF responses. In addition, because there is inevitable random noise in the actual quantization path delay process, the reliability of the soft PUF is low. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a timing violation soft PUF based on a carry lookahead adder which has high security, low hardware overhead, no waste of hardware resources, high efficiency in generating PUF responses, and high reliability.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: a timing violation soft PUF based on a carry-lookahead adder, which uses a combinatorial logic pipeline structure whose arithmetic operation unit is a carry-lookahead adder as a hardware platform, and generates a PUF response output by causing a timing violation inside the combinatorial logic pipeline structure.

[0008] The combinational logic pipeline structure includes an input register unit, an arithmetic operation unit and a sampling register unit; the arithmetic operation unit is a carry-lookahead adder for performing addition operations, and the number of bits of addends that can be calculated by the carry-lookahead adder is recorded as m, that is, the carry-lookahead adder is an m-bit carry-lookahead adder, and the m-bit carry-lookahead adder has two m-bit addend input ports and an m+1-bit addend and output port; the input register unit is composed of 2m D flip-flops, each of which has 1 signal input port, 1 signal output port and 1 clock control port, the signal input ports of the 2m D flip-flops serve as the 2m-bit excitation input ports of the input register unit, the signal output ports of the 2m D flip-flops serve as the 2m-bit output ports of the input register unit, the clock control ports of the 2m D flip-flops are connected, and the The connection end is the clock control port of the input register unit; the sampling register unit is composed of m+1 D flip-flops, each of which has 1 signal input port, 1 signal output port and 1 clock control port, the signal input ports of the m+1 D flip-flops serve as the m+1-bit input ports of the sampling register unit, the signal output ports of the m+1 D flip-flops serve as the m+1-bit output ports of the sampling register unit, the clock control ports of the m+1 D flip-flops are connected, and the connection end is the clock control port of the sampling register unit; the 2m-bit output port of the input register unit is correspondingly connected to the two m-bit addend input ports of the m-bit carry lookahead adder, and the m+1-bit addend sum output port of the m-bit carry lookahead adder is connected to the m+1-bit input port of the sampling register unit;

[0009] When the timing violation soft PUF based on the carry-lookahead adder needs to generate a PUF response, a 2m-bit excitation signal is input to the 2m-bit excitation input port of the input register unit, and a two-cycle clock signal is simultaneously input to the clock control port of the input register unit and the clock control port of the sampling register unit, and the period of the clock signal is 0.5T max , T maxis the maximum path delay time from the 2m-bit excitation input port of the input register unit to the m+1-bit output port of the sampling register unit. When the first rising edge of the clock signal arrives, the input register unit, under the control of the clock signal, outputs the 2m-bit excitation signal input thereto through its 2m-bit output port to the two m-bit addend input ports of the m-bit carry-lookahead adder. The m-bit carry-lookahead adder adds the two m-bit excitation signals input to its two m-bit addend input ports to obtain an m+1-bit operation result, which is output to the m+1-bit input port of the sampling register unit through its m+1-bit addend sum output port. Afterwards, when the second rising edge of the clock signal arrives, the sampling register unit, under the control of the clock signal, samples the m+1-bit operation result connected to its m+1-bit input port. At this time, due to the timing The period of the clock signal is too small, resulting in timing violations in some triggers in the sampling register unit. The triggers with timing violations randomly output 0 or 1 at their signal output ports, thereby causing the m+1-bit output port of the sampling register unit to output an abnormal m+1-bit operation result. The abnormal m+1-bit operation result is used as the initial PUF response of the soft PUF. The highest bit of the theoretical operation result obtained by adding two m-bit excitation signals input from the two m-bit addend input ports of the m-bit carry lookahead adder is discarded as the m-bit reference value. The highest bit of the initial PUF response is discarded to obtain m-bit data. The number of different bits between the m-bit data and the m-bit reference value is counted. If the statistical result is an odd number, the final PUF response of the timing violation soft PUF based on the carry lookahead adder is 1, otherwise it is 0.

[0010] Compared with the prior art, the advantage of the present invention is that it uses a combinatorial logic pipeline structure in which the arithmetic operation unit is a carry-lookahead adder as a hardware platform, and generates a PUF response output by causing a timing violation inside the combinatorial logic pipeline structure. There is no need to additionally design and add any other hardware circuits. By increasing the clock frequency of the existing combinatorial logic pipeline structure to cause a timing violation inside the structure, a PUF response that can characterize the hardware characteristics can be extracted. While having higher security, it has lower hardware overhead, does not cause waste of hardware resources, and has higher work efficiency, better reliability and uniqueness. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A two-dimensional grayscale image of 10,000 responses of a single carry-lookahead adder-based timing violation soft PUF of the present invention under normal temperature and pressure conditions;

[0012] Figure 2This is an average grayscale mapping result diagram of 30 timing violation soft PUF output responses based on carry look-ahead adders of the present invention under normal temperature and pressure conditions;

[0013] Figure 3 This is a graph showing the ACF test result of a 10,000-bit response of a single carry-lookahead adder-based timing violation soft PUF of the present invention under normal temperature and pressure conditions;

[0014] Figure 4 The inter-chip Hamming distance (Inter-HD) diagram is a graph of the same set of stimuli applied to 30 timing violation soft PUFs based on carry-lookahead adders of the present invention under normal temperature and pressure conditions;

[0015] Figure 5 Figure 2 is the intra-chip Hamming distance (Intra-HD) diagram and the graph of the timing violation soft PUF based on carry-lookahead adder of the present invention after the same set of stimuli are repeatedly applied 50 times under normal temperature and pressure conditions. Figure 4 Normalized result diagram of the inter-slice Hamming distance (Inter-HD);

[0016] Figure 6 This is the prediction accuracy diagram of 5 different PUFs under different training sets when the machine learning attack algorithm is LR;

[0017] Figure 7 This is the prediction accuracy graph of 5 different PUFs under different training sets when the machine learning attack algorithm is ANN;

[0018] Figure 8 This is the prediction accuracy chart of 5 different PUFs under different training sets when the machine learning attack algorithm is SVM;

[0019] Fig. 9 This is the prediction accuracy chart for 5 different PUFs under different training sets when the machine learning attack algorithm is Light GBM. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below with reference to the accompanying drawings.

[0021] Embodiment 1: A timing violation soft PUF based on a carry-lookahead adder uses a combinatorial logic pipeline structure whose arithmetic operation unit is a carry-lookahead adder as a hardware platform, and generates a PUF response output by causing a timing violation inside the combinatorial logic pipeline structure.

[0022] In this embodiment, the existing combinational logic pipeline structure using the arithmetic operation unit as a carry-lookahead adder is used as the hardware platform, and no additional design or addition of any other hardware circuit is required. The PUF response that can characterize the hardware characteristics can be extracted by increasing the clock frequency of the existing combinational logic pipeline structure. Compared with the existing soft PUF products, it has higher security and lower hardware overhead, does not cause waste of hardware resources, and has higher work efficiency, better reliability and uniqueness.

[0023] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the combinational logic pipeline structure includes an input register unit, an arithmetic operation unit and a sampling register unit; the arithmetic operation unit is a carry-lookahead adder that performs addition operations, and the number of bits of addends that can be calculated by the carry-lookahead adder is recorded as m, that is, the carry-lookahead adder is an m-bit carry-lookahead adder, and the m-bit carry-lookahead adder has two m-bit addend input ports and an m+1-bit addend and output port; the input register unit is composed of 2m D flip-flops, each of which has 1 signal input port, 1 signal output port and 1 clock control port, the signal input ports of the 2m D flip-flops serve as the 2m-bit excitation input ports of the input register unit, the signal output ports of the 2m D flip-flops serve as the 2m-bit output ports of the input register unit, the clock control ports of the 2m D flip-flops are connected, and their connection ends are the clock control ports of the input register unit; the sampling register unit is composed of m+1 D flip-flops, Each D flip-flop has 1 signal input port, 1 signal output port and 1 clock control port. The signal input ports of m+1 D flip-flops serve as the m+1-bit input ports of the sampling register unit, and the signal output ports of the m+1 D flip-flops serve as the m+1-bit output ports of the sampling register unit. The clock control ports of the m+1 D flip-flops are connected, and their connection ends are the clock control ports of the sampling register unit. The 2m-bit output port of the input register unit is correspondingly connected to the two m-bit addend input ports of the m-bit carry lookahead adder, and the m+1-bit addend sum output port of the m-bit carry lookahead adder is connected to the m+1-bit input port of the sampling register unit. When the timing violation soft PUF based on the carry lookahead adder needs to generate a PUF response, a 2m-bit excitation signal is input to the 2m-bit excitation input port of the input register unit, and two-cycle clock signals are simultaneously input to the clock control port of the input register unit and the clock control port of the sampling register unit, and the period of the clock signal is 0.5T. max , T maxis the maximum path delay time from the 2m-bit excitation input port of the input register unit to the m+1-bit output port of the sampling register unit (obtained in advance through experimental testing). When the first rising edge of the clock signal arrives, the input register unit outputs the 2m-bit excitation signal input thereto through its 2m-bit output port to the two m-bit addend input ports of the m-bit carry lookahead adder under the control of the clock signal. The m-bit carry lookahead adder adds the two m-bit excitation signals, i.e., the two m-bit addends, inputted to its two m-bit addend input ports to obtain an m+1-bit operation result, which is outputted to the m+1-bit input port of the sampling register unit through its m+1-bit addend sum output port. Afterwards, when the second rising edge of the clock signal arrives, the sampling register unit samples the m+1-bit operation result connected to its m+1-bit input port under the control of the clock signal. At this time, since the period of the clock signal is too small, some triggers in the sampling register unit have timing violations. These triggers with timing violations randomly output 0 or 1 at their signal output ports, which causes the m+1-bit output port of the sampling register unit to output an abnormal m+1-bit operation result. This abnormal m+1-bit operation result is used as the initial PUF response of the soft PUF. The highest bit of the theoretical operation result obtained by adding the two m-bit excitation signals input from the two m-bit addend input ports of the m-bit carry lookahead adder is discarded as the m-bit reference value. The highest bit of the initial PUF response is discarded to obtain m-bit data. The number of different bits between the m-bit data and the m-bit reference value is counted. If the statistical result is an odd number, the final PUF response of the soft PUF based on the timing violation of the carry lookahead adder is 1, otherwise it is 0.

[0024] In this embodiment, m=32, that is, the arithmetic operation unit is a 32-bit carry-lookahead adder, the input register unit is composed of 64 D flip-flops, and the sampling register unit is composed of 33 D flip-flops. Through post-simulation testing, the maximum path delay time from the 64-bit stimulus input port of the input register unit to the 33-bit output port of the sampling register unit is 4.062ns. The specific experimental steps of the timing violation soft PUF based on the carry-lookahead adder of the present invention to generate a 1-bit PUF response are as follows:

[0025] (1) Using the FPGA internal clock IP core MMCM, two clock signals with a period of 2.031 ns are simultaneously input into the clock control ports of the input register unit and the sampling register unit. Through Matlab, a 64-bit excitation signal 64'h1234ABCDABCD1234 is input into the 64-bit excitation input port of the input register unit. When the rising edge of the clock signal of the first cycle arrives, the 64-bit excitation signal 64'h1234ABCDABCD1234 is divided into two 32-bit excitation signals, that is, two 32-bit addends 32'h1234ABCD and 32'hABCD1234 are output to the two 32-bit addend input ports of the 32-bit carry lookahead adder in a one-to-one correspondence. The two 32-bit addend input ports of the 32-bit carry lookahead adder input two 32-bit addends 3 2'h1234ABCD and 32'hABCD1234 are operated, and the 33-bit operation result is output to the 33-bit input port of the sampling register unit through its 33-bit output port. When the rising edge of the clock signal of the second cycle arrives, the sampling register unit samples the 33-bit operation result input at its 33-bit input port. Because some D flip-flops in the sampling register unit have timing violations at this time, the sampling register unit samples the 33-bit operation result input at its 33-bit input port abnormally. At this time, its 33-bit output port outputs an abnormal 33-bit operation result 33'h0BE11BD11, and the abnormal 33-bit operation result 33'h0BE11BD11 is fed back to the PC end as the initial PUF response of the timing violation soft PUF based on the carry lookahead adder of the present invention;

[0026] (2) Matlab on the PC performs the addition operation of two 32-bit addends 32'h1234ABCD and 32'hABCD1234 to obtain the 33-bit theoretical operation value 33'h0BE01BE01;

[0027] (3) Discard the highest bit of the 33-bit theoretical operation value 33'h0BE01BE01 to obtain the 32-bit reference value 32'hBE01BE01. Similarly, discard the highest bit of the initial PUF response to obtain the 32-bit data 32'hBE11BD11. XOR the 32-bit reference value 32'hBE01BE01 with the 32-bit data 32'hBE11BD11 to obtain the 32-bit XOR value 32'h00100310. Counting that 4 bits of the 32-bit XOR value 32'h00100310 are 1, it means that the number of bits that are different between the 32-bit reference value 32'hBE01BE01 and the 32-bit data 32'hBE11BD11 is 4. Because 4 is an even number, the timing violation soft PUF based on the carry lookahead adder of the present invention, under the stimulation of the 64-bit stimulation signal 64'h1234ABCDABCD1234, finally generates a PUF response of 0.

[0028] When the 64-bit excitation signal input to the 64-bit excitation input port of the input register unit is changed, the 32-bit addends connected to the two 32-bit addend input ports of the 32-bit carry-lookahead adder can be changed, thereby changing the final PUF response generated by the timing violation soft PUF based on the carry-lookahead adder of the present invention.

[0029] In this embodiment, a combinational logic pipeline structure with a 32-bit carry-lookahead adder as the arithmetic operation unit is used as the hardware platform, and no additional hardware structure is required. Compared with the existing soft PUF based on quantized 32-bit multiplier path delay, it not only greatly reduces the hardware overhead, but also can generate the same number of stimulus response pairs under the input of the same number of stimulus signals, and only needs to perform one addition operation when obtaining the PUF response, and only needs two clock cycles to extract the initial PUF response of the soft PUF, making the process of obtaining the PUF response simple and efficient. The actual sampling value of the sampling register unit (the abnormal 33-bit operation result output by the 33-bit output port of the sampling register unit) is used as the initial PUF response of the soft PUF. This method does not cause waste of PUF response bits and avoids the unstable response phenomenon caused by random noise in the quantization delay time, thereby improving the reliability of the soft PUF. In addition, the final PUF response of the soft PUF undergoes data processing processes including preprocessing of the sampled value (removing the highest bit), statistics of the number of bits that are different between the sampled value after preprocessing and the reference value, and parity check, which makes it more difficult for attackers to model the soft PUF, thereby improving the security of the soft PUF. It can be seen that the present invention has lower hardware overhead, higher work efficiency and better reliability, as well as better security, and is suitable for protection issues in the field of information security.

[0030] The development board NEXYS4 DDR is used to layout the timing violation soft PUF based on the carry look-ahead adder of the present invention on the Xilinx XC7A100T FPGA through the Vivado tool. The communication with the FPGA is established through the Matlab tool on the PC. The FPGA internal clock IP core MMCM is called to generate a clock control signal. The stimulus is generated by Matlab and transmitted to the FPGA. The FPGA is responsible for feeding back the generated initial PUF response to the PC. After that, the initial PUF response is post-processed by Matlab to generate the final soft PUF response. The performance analysis of the generated soft PUF response is as follows:

[0031] (1) Randomness

[0032] Randomness can be measured intuitively by observing the distribution of PUF responses to logical 0 and logical 1. In a completely random situation, the probability of "0" and "1" should be 0.5. Figure 1 A two-dimensional grayscale image of 10,000 responses of a single carry-lookahead adder-based timing violation soft PUF of the present invention is shown in FIG. Figure 2 The average grayscale mapping results of the responses of 30 carry-lookahead adder-based timing violation soft PUFs of the present invention are reflected, and the overall value is maintained at about 0.5. The PUF response distribution is random and has no obvious logical deviation, indicating that the carry-lookahead adder-based timing violation soft PUF of the present invention has good randomness.

[0033] In order to evaluate the response randomness of the timing violation soft PUF based on the carry lookahead adder in a more rigorous and systematic manner, the 10 6 The 10-bit PUF response sequence is tested using the NIST 800-22 randomness test suite. 6 The bit PUF response sequence is divided into 20 groups of bit streams with a length of 50,000 each as the input of the NIST test. When the P value of the test result is greater than 0.01, the bit stream is considered to be random with a confidence level of 99%. The NIST test results are shown in Table 1:

[0034] Table 1 NIST test results of PUF

[0035]

[0036] From the analysis of Table 1, it can be seen that the timing violation soft PUF based on carry lookahead adder of the present invention has passed the listed NIST test items, which indicates that the PUF response generated by the timing violation soft PUF based on carry lookahead adder of the present invention has good randomness.

[0037] (2) Unpredictability

[0038] The autocorrelation function (ACF) describes the correlation between the current value and the past value of the random response sequence. An ACF value of 0 means that the generated response sequence has no spatial correlation. The ACF test is performed on the 10,000-bit response of the timing violation soft PUF based on the carry lookahead adder of the present invention. The results are as follows: Figure 3 shown. Figure 3 The test results show that within a 95% confidence interval, the ACF value of the timing violation soft PUF based on the carry look-ahead adder of the present invention is 0.0237, which is close to the ideal value of 0.

[0039] (3) Uniqueness and reliability

[0040] The uniqueness of PUF is measured by the inter-Hamming distance (Inter-HD), which is measured by the average Hamming distance between the responses generated by applying the same stimulus to different PUFs. Ideally, the proportion is 50%. The average Hamming distance is calculated as follows:

[0041]

[0042] When calculating the average inter-chip Hamming distance, k represents the number of PUFs, R p and R q represents the output response of the pth and qth PUFs under the same stimulus, r represents the number of response bits, HD(R p ,R q ) is the Hamming distance of the output response. By changing the layout and replacing different development boards, the same set of input excitation signals are applied to 30 different timing violation soft PUFs based on carry-lookahead adders of the present invention, and the Inter-HD of their PUF response data is counted and analyzed, as shown in Figure 4 Analysis Figure 4 It can be seen that the average inter-chip Hamming distance of the timing violation soft PUF based on the carry lookahead adder of the present invention is 49.93%, and the variance is 0.53%, indicating that the timing violation soft PUF based on the carry lookahead adder of the present invention has good uniqueness.

[0043] The reliability of PUF is used to reflect the ability to maintain consistent responses under the same stimulus. The reliability of PUF is measured by counting the average intra-Hamming distance (Intra-Hamming Distance, Intra-HD) of the responses of the same PUF under the same stimulus for k repetitions, and the ideal case is 0%. When calculating the average intra-Hamming distance, k at this time represents the number of repetitions. The same set of excitation signals is repeatedly applied 50 times to the same timing violation soft PUF based on carry lookahead adder of the present invention, and the Intra-HD of its PUF response data is counted and analyzed. The average intra-Hamming distance of the timing violation soft PUF based on carry lookahead adder of the present invention is 2.61%, and the variance is 0.45%, indicating that the timing violation soft PUF based on carry lookahead adder of the present invention has good reliability. After normalizing Inter-HD and Intra-HD, as shown in Figure 5 As shown, Figure 5 This intuitively reflects that the timing violation soft PUF based on the carry-lookahead adder of the present invention has higher reliability and uniqueness.

[0044] (4) Security

[0045] In order to evaluate the security of the timing violation soft PUF based on carry lookahead adder of the present invention, APUF and its three variants 2XOR PUF, 4XOR PUF and 8XOR PUF are used as reference objects. Each PUF generates 10 6 The authors used four machine learning algorithms to conduct Python modeling attack experiments on each PUF instance. The attack algorithms used were logistic regression LR, support vector machine SVM, artificial neural network ANN, and lightweight gradient boosting machine LightGBM. During training, the test set was fixed at 200,000, and the number of training sets was gradually increased to 800,000. The prediction accuracy of different algorithms for the five PUFs under different data sets was counted. Figure 6 It reflects the prediction accuracy when the attack algorithm is LR. Figure 7 It reflects the prediction accuracy when the attack algorithm is ANN. Figure 8 It reflects the prediction accuracy when the attack algorithm is SVM. Fig. 9 It reflects the prediction accuracy when the attack algorithm is Light GBM. Figures 6 to 9 The results show that the timing violation soft PUF based on carry-lookahead adder of the present invention has good anti-attack capability against four machine learning algorithms, which further illustrates that the present invention has strong security.

[0046] (5) Performance comparison

[0047] The performance comparison of the timing violation soft PUF based on carry look-ahead adder of the present invention and four other different types of soft PUFs is shown in Table 2.

[0048] Table 2 Performance comparison of different types of soft PUF

[0049]

[0050] In Table 2, document 1 is “J.Chen, P.Wang, Y.Zhang, and H.Zhang, “SPUF design based onCamellia encryption algorithm,” Microelectronics Journal, vol 112, 2021.”, document 2 is “Wang Pengjun, Chen Jia, Zhang Yuejun, et al. Multi-entropy source soft PUF based on path sensitization [J]. Journal of Xidian University, 2022, 49(06): 58-66.”, document 3 is “A.Japa, J.Zhang, W.Liu and C.Gu, “Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?” ,”in2023Asian Hardware Oriented Security and Trust Symposium(Asian HOST),Tianjin,China,pp.1-6,2023.” Document 4 is “A.Maiti and P.Schaumont,“Anovel microprocessor-intrinsic Physical Unclonable Function,”in 22nd International Conference onField Programmable Logic and Applications(FPL),pp.380-387,2012.”. Analysis of the data in Table 2 shows that the timing violation soft PUF based on carry lookahead adder of the present invention has higher reliability and stronger security than the other four different types of existing soft PUFs.

[0051] In summary, the timing violation soft PUF based on carry-lookahead adder of the present invention completely adopts the existing combinatorial logic pipeline structure using arithmetic operation units as carry-lookahead adders as the hardware platform, and does not require additional design and addition of any other hardware circuits. By increasing the clock frequency of the existing combinatorial logic pipeline structure, the PUF response that can characterize the hardware characteristics can be extracted. Compared with the existing soft PUF products, the timing violation soft PUF based on carry-lookahead adder of the present invention has higher security and lower hardware overhead, does not cause hardware resource waste, has higher work efficiency, and has better reliability and uniqueness.

Claims

1. A timing violation soft PUF based on carry-lookahead adder, characterized in that A combinatorial logic pipeline structure whose arithmetic operation unit is a carry-lookahead adder is used as a hardware platform, and a PUF response output is generated by causing a timing violation inside the combinatorial logic pipeline structure.

2. The timing violation soft PUF based on carry-lookahead adder according to claim 1, characterized in that The combinational logic pipeline structure includes an input register unit, an arithmetic operation unit and a sampling register unit; The arithmetic operation unit is a carry-lookahead adder for performing addition operations, and the number of bits of addends that can be calculated by the carry-lookahead adder is recorded as m, that is, the carry-lookahead adder is an m-bit carry-lookahead adder, and the m-bit carry-lookahead adder has two m-bit addend input ports and an m+1-bit addend output port; The input register unit is composed of 2m D flip-flops, each of which has 1 signal input port, 1 signal output port and 1 clock control port. The signal input ports of the 2m D flip-flops serve as the 2m-bit excitation input ports of the input register unit, the signal output ports of the 2m D flip-flops serve as the 2m-bit output ports of the input register unit, and the clock control ports of the 2m D flip-flops are connected, and their connection ends are the clock control ports of the input register unit. The sampling register unit is composed of m+1 D flip-flops, each of which has 1 signal input port, 1 signal output port and 1 clock control port. The signal input ports of the m+1 D flip-flops serve as the m+1-bit input ports of the sampling register unit, the signal output ports of the m+1 D flip-flops serve as the m+1-bit output ports of the sampling register unit, and the clock control ports of the m+1 D flip-flops are connected, and their connection ends are the clock control ports of the sampling register unit. The 2m-bit output port of the input register unit is connected to the two m-bit addend input ports of the m-bit carry-lookahead adder, and the m+1-bit addend sum output port of the m-bit carry-lookahead adder is connected to the m+1-bit input port of the sampling register unit; When the timing violation soft PUF based on the carry-lookahead adder needs to generate a PUF response, a 2m-bit excitation signal is input to the 2m-bit excitation input port of the input register unit, and a two-cycle clock signal is simultaneously input to the clock control port of the input register unit and the clock control port of the sampling register unit, and the period of the clock signal is 0.5T max , T max is the maximum path delay time from the 2m-bit excitation input port of the input register unit to the m+1-bit output port of the sampling register unit. When the first rising edge of the clock signal arrives, the input register unit, under the control of the clock signal, outputs the 2m-bit excitation signal input thereto through its 2m-bit output port to the two m-bit addend input ports of the m-bit carry-lookahead adder. The m-bit carry-lookahead adder adds the two m-bit excitation signals input to its two m-bit addend input ports to obtain an m+1-bit operation result, which is output to the m+1-bit input port of the sampling register unit through its m+1-bit addend sum output port. Afterwards, when the second rising edge of the clock signal arrives, the sampling register unit, under the control of the clock signal, samples the m+1-bit operation result connected to its m+1-bit input port. At this time, due to the timing The period of the clock signal is too small, resulting in timing violations in some triggers in the sampling register unit. The triggers with timing violations randomly output 0 or 1 at their signal output ports, thereby causing the m+1-bit output port of the sampling register unit to output an abnormal m+1-bit operation result. The abnormal m+1-bit operation result is used as the initial PUF response of the soft PUF. The highest bit of the theoretical operation result obtained by adding two m-bit excitation signals input from the two m-bit addend input ports of the m-bit carry lookahead adder is discarded as the m-bit reference value. The highest bit of the initial PUF response is discarded to obtain m-bit data. The number of different bits between the m-bit data and the m-bit reference value is counted. If the statistical result is an odd number, the final PUF response of the timing violation soft PUF based on the carry lookahead adder is 1, otherwise it is 0.

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