Silicon epitaxial wafer capable of reducing edge microcrack defects and preparation method thereof

Abstract

The invention provides a silicon epitaxial wafer capable of reducing edge microcrack defects and a preparation method thereof. The preparation method comprises the following steps: etching a reaction cavity and a graphite base; coating the graphite base with silicon; a silicon substrate slice is placed in the slice pit; hydrogen and trichlorosilane are introduced into the reaction cavity, growth of a silicon epitaxial layer is carried out, the initial flow of trichlorosilane is 4-6 g / min, the initial growth rate is 0.9-1.1 [mu] m / min, and after growth is carried out for 1-2 min, the flow of trichlorosilane is adjusted to be 10-12 g / min, the growth rate of the silicon epitaxial layer is adjusted to be 1.8-2.0 [mu] m / min, and the target thickness is achieved. According to the preparation method, parameters such as silicon coating time, wafer placing temperature, growth temperature, growth rate and the like are regulated and controlled, the probability that microcrack defects appear on the edge of the thick-layer silicon epitaxial wafer is reduced, the process is simple, batch repetition can be achieved, and preparation and batch production of the silicon epitaxial wafer with the diameter being 125-200 mm and the target silicon epitaxial layer thickness being 50-120 microns are achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor silicon epitaxial wafer preparation, and in particular relates to a silicon epitaxial wafer capable of reducing edge microcrack defects and a preparation method thereof. Background Art

[0002] Silicon epitaxial wafers are an important product in the field of semiconductor materials. They specifically refer to semiconductor silicon wafers formed by epitaxial growth technology on the basis of silicon polished wafers. The doping type, resistivity, thickness, uniformity and other parameters of silicon epitaxial wafers need to meet the use requirements of the device. At present, the working withstand voltage requirement of high-voltage and high-power devices is 500~1200 V, and the corresponding requirement for the thickness of the target silicon epitaxial layer is 50~120 μm, which belongs to thick silicon epitaxial wafers. The epitaxial layer of thick silicon epitaxial wafers grows continuously at high temperature for a relatively long time, causing the silicon epitaxial wafers to face greater mechanical and thermal stress, especially the edge position is more significantly affected by mechanical and thermal stress, which significantly increases the probability of microcrack defects in thick silicon epitaxial wafers, because any microcrack at any position will be judged as a defective product, so the occurrence of microcrack defects seriously reduces the growth yield and production efficiency of thick silicon epitaxial wafers.

[0003] To grow silicon epitaxial wafers with a target silicon epitaxial layer thickness of 50~120μm, a flat-plate multi-wafer silicon epitaxial furnace is required. In each furnace, 10 125mm diameter silicon epitaxial wafers, 8 150mm diameter silicon epitaxial wafers, and 5 200mm diameter silicon epitaxial wafers can be grown simultaneously. Solving the problem of microcrack defects at the edge of thick silicon epitaxial wafers has become a key technical problem in the preparation and industrial mass production of thick silicon epitaxial wafers.

[0004] The Chinese patent document with publication number CN103354242B discloses an extremely thick epitaxial wafer for high-voltage power devices and a method for manufacturing the same. The method significantly prolongs the heating time to reduce the thermal deformation of the silicon epitaxial wafer and realizes the preparation of silicon epitaxial wafers with a silicon epitaxial layer thickness greater than 100 μm. The Chinese patent document with publication number CN118241309B discloses a method for preparing an extremely thick film silicon epitaxial wafer, wherein the silicon epitaxial layer growth rate is set to 1.5~1.6 μm / min, and the thermal stress of the silicon epitaxial wafer is reduced by significantly reducing the silicon epitaxial layer growth rate, thereby realizing the growth of silicon epitaxial wafers with a silicon epitaxial layer thickness greater than 200 μm. However, the preparation method and process parameters are suitable for growing extremely thick film silicon epitaxial wafers with a silicon epitaxial layer thickness of 200~230 μm, and are not suitable for preparing silicon epitaxial wafers with a silicon epitaxial layer thickness of 50~120 μm. Moreover, the process takes a long time, which affects the production capacity of industrial mass production of thick silicon epitaxial wafers. The Chinese patent document with publication number CN117626425B discloses a method for preparing 8-inch silicon epitaxial wafers for IGBT, which grows the epitaxial layer by means of variable temperature and variable flow rate, first using high temperature and large flow rate for rapid growth, then using low temperature and large flow rate for medium-speed growth, and then low temperature and small flow rate for slow growth to reduce the risk of cracking. In the above-mentioned preparation methods, the process time is relatively long and the process is relatively complicated, which affects the production capacity of industrial mass production of thick silicon epitaxial wafers. The industry urgently needs a preparation method for thick silicon epitaxial wafers with simple preparation process and stable reduction of edge microcrack defects. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a silicon epitaxial wafer capable of reducing edge microcrack defects and a preparation method thereof. By comprehensively designing parameters such as silicon coating time, wafer placement temperature, growth temperature, and growth rate required for a thick silicon epitaxial layer, the probability of microcrack defects occurring at the edge of the thick silicon epitaxial wafer is reduced. The preparation and mass production of silicon epitaxial wafers with a diameter of 125 to 200 mm and a target silicon epitaxial layer thickness of 50 to 120 μm are achieved under the condition of simple process and batch repetition.

[0006] In order to solve the above problems, one aspect of the present invention provides a method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects, wherein the thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 50-120 μm, and the preparation method comprises the following steps in sequence: S1. Etching the reaction chamber of the silicon epitaxial furnace and the graphite base in the reaction chamber; S2. The graphite base is subjected to silicon coating; S3. Place a silicon substrate sheet in the pit of the graphite base in the reaction chamber of the silicon epitaxial furnace; S4. Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The initial trichlorosilane flow rate is 4-6 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9-1.1 μm / min. After the growth time is maintained for 1-2 min, the trichlorosilane flow rate is adjusted to 10-12 g / min and the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min until the target silicon epitaxial layer thickness is reached to obtain a silicon epitaxial wafer.

[0007] Preferably, step S1 comprises: introducing hydrogen gas and hydrogen chloride gas into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and the graphite base of the silicon epitaxial furnace; The temperature of the reaction chamber of the silicon epitaxial furnace is 1080~1100℃.

[0008] Preferably, in step S1, the hydrogen flow rate is 20-50 L / min, the hydrogen chloride gas flow rate is 34-36 L / min, and the etching time is 7-15 min.

[0009] Preferably, step S2 comprises: introducing hydrogen and trichlorosilane into a reaction chamber of a silicon epitaxial furnace to grow a polycrystalline silicon coating layer on a graphite base; The hydrogen flow rate is 140~160 L / min, the trichlorosilane flow rate is 10~14 g / min, and the time for growing the polysilicon coating is 150~300 sec.

[0010] Preferably, in step S3, the temperature in the reaction chamber of the silicon epitaxial furnace is 280-300°C.

[0011] Preferably, in step S4, the temperature in the reaction chamber of the silicon epitaxial furnace is 1030-1050°C.

[0012] Preferably, in step S4, the hydrogen flow rate is 140-160 L / min.

[0013] Preferably, the silicon epitaxial furnace is a flat-plate multi-wafer silicon epitaxial furnace.

[0014] Preferably, the crystal orientation of the silicon substrate is <111> , diameter is 125~200 mm, resistivity is 0.001~0.005Ω·cm, and oxygen content is 8~12 ppma.

[0015] Another aspect of the present invention provides a silicon epitaxial wafer capable of reducing edge microcrack defects, which is prepared by the above-mentioned preparation method.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of the present invention comprises the following steps: firstly etching and silicon coating a reaction chamber and a graphite base of a silicon epitaxial furnace to optimize the growth surface of an epitaxial layer, improve the quality of the epitaxial layer, and enhance process efficiency; then placing a silicon substrate into the graphite base to grow a silicon epitaxial layer, and accurately controlling and obtaining a growth rate suitable for the growth of a silicon epitaxial layer with a thickness of 50 to 120 μm; the growth rate range can greatly shorten the process time while ensuring that no microcrack defects are generated, and improve the production capacity of industrial mass production of thick silicon epitaxial wafers; further, an initial growth stage is added, and a smaller trichlorosilane flow rate and a smaller growth rate are used in the initial growth stage to relieve stress and avoid stress accumulation due to direct high-speed growth, which leads to cracking.

[0017] The method for preparing silicon epitaxial wafers capable of reducing edge microcrack defects reduces the probability of microcrack defects occurring at the edge of thick silicon epitaxial wafers by comprehensively designing parameters such as silicon coating time, wafer placement temperature, growth temperature, and growth rate required for thick silicon epitaxial layers, and realizes the preparation and mass production of silicon epitaxial wafers with a diameter of 125-200 mm and a target silicon epitaxial layer thickness of 50-120 μm under the condition of simple process and batch repetition. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a silicon epitaxial wafer prepared in Examples 1-6 of the present invention; Figure 2 is a schematic diagram of the location of microcracks on the silicon epitaxial wafer prepared in Comparative Example 1; Figure 3 is a schematic diagram of the location of microcracks on the silicon epitaxial wafer prepared in Comparative Example 3; Figure 4 is a schematic diagram of the location of microcracks on the silicon epitaxial wafer prepared in Comparative Example 4; Figure 5 is a schematic diagram of the location of microcracks on the silicon epitaxial wafer prepared in Comparative Example 5; Figure 6 It is a schematic diagram of the location of microcracks on the silicon epitaxial wafer prepared in Comparative Example 7. DETAILED DESCRIPTION

[0019] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0020] One aspect of an embodiment of the present invention provides a method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects, wherein the thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 50 to 120 μm, and the preparation method comprises sequentially performing the following steps: S1. Etching the reaction chamber of the silicon epitaxial furnace and the graphite base in the reaction chamber; S2. The graphite base is subjected to silicon coating; S3. Place a silicon substrate sheet in the pit of the graphite base in the reaction chamber of the silicon epitaxial furnace; S4. Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The initial trichlorosilane flow rate is 4-6 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9-1.1 μm / min. After the growth time is maintained for 1-2 min, the trichlorosilane flow rate is adjusted to 10-12 g / min and the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min until the target silicon epitaxial layer thickness is reached to obtain a silicon epitaxial wafer.

[0021] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects in an embodiment of the present invention comprises the following steps: firstly etching and silicon coating a reaction chamber and a graphite base of a silicon epitaxial furnace to optimize the growth surface of an epitaxial layer, improve the quality of the epitaxial layer, and enhance process efficiency; then placing a silicon substrate into the graphite base to grow a silicon epitaxial layer, and accurately controlling the growth rate suitable for the growth of a silicon epitaxial layer with a thickness of 50 to 120 μm; the growth rate range can greatly shorten the process time while ensuring that no microcrack defects are generated, thereby improving the capacity of industrial mass production of thick silicon epitaxial wafers; further, an initial growth stage is added, in which a smaller trichlorosilane flow rate and a smaller growth rate are used to relieve stress and avoid stress accumulation due to direct high-speed growth, which leads to cracking.

[0022] The graphite base is the carrier and heating element of the silicon substrate. Its thermal stability, thermal uniformity and other performance parameters play a decisive role in the quality of epitaxial material growth, and directly determine the uniformity and purity of the material. Therefore, its quality directly affects the preparation of epitaxial wafers. Etching the reaction chamber and graphite base can remove surface impurities, optimize the growth surface, adjust the growth conditions, and improve process stability and repeatability; silicon coating can protect the base, effectively block the impurities released by the graphite base, reduce the pollution of the epitaxial silicon layer, and provide a stable growth surface to improve the heat conduction to the silicon substrate.

[0023] In some embodiments, step S1 etches the reaction chamber of the silicon epitaxial furnace and the graphite susceptor in the reaction chamber, which may specifically include: introducing hydrogen and hydrogen chloride gas into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber of the silicon epitaxial furnace and the graphite susceptor.

[0024] The etching temperature can significantly affect the etching effect of the reaction chamber and the graphite base, thereby affecting the product quality of the silicon epitaxial wafer. Preferably, the temperature of the reaction chamber of the silicon epitaxial furnace is 1080-1100°C.

[0025] The gas flow rate during etching can significantly affect the etching effect of the reaction chamber and the graphite base, thereby affecting the product quality of the silicon epitaxial wafer. Preferably, in step S1, the hydrogen flow rate is 20-50 L / min, the hydrogen chloride gas flow rate is 34-36 L / min, and the etching time is 7-15 min.

[0026] In some embodiments, step S2 performs silicon coating on the graphite susceptor, which may specifically include: introducing hydrogen and trichlorosilane into a reaction chamber of a silicon epitaxial furnace to grow a polysilicon coating layer on the graphite susceptor.

[0027] When growing a polysilicon coating on a graphite susceptor, the gas flow rate and time can significantly affect the growth rate, thickness, deposition amount and density of the silicon layer, thereby affecting the quality of the silicon coating of the graphite susceptor. Preferably, when the graphite susceptor is subjected to silicon coating treatment, the hydrogen flow rate is 140-160 L / min, the trichlorosilane flow rate is 10-14 g / min, and the time for growing the polysilicon coating is 150-300 sec.

[0028] Preferably, in step S3, the temperature in the reaction chamber of the silicon epitaxial furnace is 280-300°C.

[0029] When the silicon epitaxial layer grows, the temperature in the reaction chamber can directly affect the growth rate, crystal quality, thermal stress, surface morphology, etc. of the epitaxial layer, thereby affecting the quality of the silicon epitaxial wafer. Preferably, in step S4, the temperature in the reaction chamber of the silicon epitaxial furnace is 1030-1050°C.

[0030] Preferably, in step S4, the hydrogen flow rate is 140-160 L / min.

[0031] Preferably, the silicon epitaxial furnace is a flat-plate multi-wafer silicon epitaxial furnace.

[0032] Preferably, the crystal orientation of the silicon substrate is <111> , diameter is 125~200 mm, resistivity is 0.001~0.005Ω·cm, and oxygen content is 8~12 ppma.

[0033] The method for preparing silicon epitaxial wafers capable of reducing edge microcrack defects in an embodiment of the present invention reduces the probability of microcrack defects occurring at the edge of thick silicon epitaxial wafers by comprehensively designing parameters such as silicon coating time, wafer placement temperature, growth temperature, and growth rate required for a thick silicon epitaxial layer, and realizes the preparation and mass production of silicon epitaxial wafers with a diameter of 125-200 mm and a target silicon epitaxial layer thickness of 50-120 μm under the condition of simple process and batch repeatability.

[0034] Another aspect of an embodiment of the present invention provides a silicon epitaxial wafer capable of reducing edge microcrack defects, which is prepared by the above-mentioned preparation method.

[0035] In the following embodiments, the crystal orientation of the silicon substrate used is <111> , diameter is 125~200 mm, resistivity is 0.001~0.005 Ω·cm, oxygen content is 8~12 ppm. The silicon epitaxial furnace used is a flat-plate multi-wafer silicon epitaxial furnace. Example 1

[0036] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1080°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 34 L / min, and the etching time is 7 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 150 L / min, the trichlorosilane flow rate was 12 g / min, and the time for growing the polycrystalline silicon coating layer was 150 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 280° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1050°C, the hydrogen flow rate is 150 L / min, the initial trichlorosilane flow rate is 4 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9 μm / min. After the growth time is maintained for 1 minute, the trichlorosilane flow rate is adjusted to 12 g / min and the silicon epitaxial layer growth rate is 2.0 μm / min until the target silicon epitaxial layer thickness is achieved, thereby obtaining a silicon epitaxial wafer, such as Figure 1 Shown is a schematic diagram of a silicon epitaxial wafer. Example 2

[0037] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1080°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 34 L / min, and the etching time is 9 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 150 L / min, the trichlorosilane flow rate was 12 g / min, and the time for growing the polycrystalline silicon coating layer was 300 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 300° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1050°C, the hydrogen flow rate is 150 L / min, the initial trichlorosilane flow rate is 6 g / min, and the initial growth rate of the silicon epitaxial layer is 1.1 μm / min. After the growth time is maintained for 1 min, the trichlorosilane flow rate is adjusted to 12 g / min and the silicon epitaxial layer growth rate is 2.0 μm / min until the target silicon epitaxial layer thickness is achieved to obtain a silicon epitaxial wafer. Example 3

[0038] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1100°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 35 L / min, and the etching time is 10 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 150 L / min, the trichlorosilane flow rate was 14 g / min, and the time for growing the polycrystalline silicon coating layer was 300 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 300° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1040°C, the hydrogen flow rate is 150 L / min, the initial trichlorosilane flow rate is 4 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9 μm / min. After the growth time is maintained for 2 minutes, the trichlorosilane flow rate is adjusted to 10 g / min and the silicon epitaxial layer growth rate is 1.8 μm / min until the target silicon epitaxial layer thickness is achieved to obtain a silicon epitaxial wafer. Example 4

[0039] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1100°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 35 L / min, and the etching time is 12 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 150 L / min, the trichlorosilane flow rate was 10 g / min, and the time for growing the polycrystalline silicon coating layer was 300 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 300° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1050°C, the hydrogen flow rate is 150 L / min, the initial trichlorosilane flow rate is 4 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9 μm / min. After the growth time is maintained for 1 min, the trichlorosilane flow rate is adjusted to 10 g / min and the silicon epitaxial layer growth rate is 1.8 μm / min until the target silicon epitaxial layer thickness is achieved to obtain a silicon epitaxial wafer. Example 5

[0040] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1100°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 35 L / min, and the etching time is 15 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 150 L / min, the trichlorosilane flow rate was 10 g / min, and the time for growing the polycrystalline silicon coating layer was 200 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 300° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1050°C, the hydrogen flow rate is 150 L / min, the initial trichlorosilane flow rate is 4 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9 μm / min. After the growth time is maintained for 2 minutes, the trichlorosilane flow rate is adjusted to 12 g / min and the silicon epitaxial layer growth rate is 2.0 μm / min until the target silicon epitaxial layer thickness is achieved to obtain a silicon epitaxial wafer. Example 6

[0041] The method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects of this embodiment comprises the following steps in sequence: (1) Introducing hydrogen and hydrogen chloride into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and graphite susceptor of the silicon epitaxial furnace; the temperature of the reaction chamber of the silicon epitaxial furnace is 1090°C, the hydrogen flow rate is 20 L / min, the hydrogen chloride flow rate is 36 L / min, and the etching time is 10 min; (2) hydrogen and trichlorosilane were introduced into the reaction chamber of the silicon epitaxial furnace to grow a polycrystalline silicon coating layer on the graphite susceptor for silicon coating treatment. The hydrogen flow rate was 140 L / min, the trichlorosilane flow rate was 12 g / min, and the time for growing the polycrystalline silicon coating layer was 200 sec. (3) placing a silicon substrate into a sheet pit of a graphite base in a reaction chamber of a silicon epitaxial furnace, wherein the temperature in the reaction chamber of the silicon epitaxial furnace is 280° C.; (4) Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The temperature in the reaction chamber of the silicon epitaxial furnace is 1030°C, the hydrogen flow rate is 160 L / min, the initial trichlorosilane flow rate is 6 g / min, and the initial growth rate of the silicon epitaxial layer is 1.1 μm / min. After the growth time is maintained for 1 min, the trichlorosilane flow rate is adjusted to 12 g / min and the silicon epitaxial layer growth rate is 1.8 μm / min until the target silicon epitaxial layer thickness is achieved to obtain a silicon epitaxial wafer.

[0042] Comparative Example 1 The preparation method of the silicon epitaxial wafer of this comparative example, the remaining steps and parameters of the preparation method are the same as those of Example 3, except that in step (3), a silicon substrate is placed in the sheet pit of the graphite base in the reaction chamber of the silicon epitaxial furnace, and the temperature in the reaction chamber of the silicon epitaxial furnace is 310°C. Figure 2 As shown, there are a few micro cracks on the edge of the silicon epitaxial wafer prepared in this comparative example.

[0043] Comparative Example 2 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that in step (3), a silicon substrate is placed in the wafer pit of the graphite base in the reaction chamber of the silicon epitaxial furnace, and the temperature in the reaction chamber of the silicon epitaxial furnace is 270°C.

[0044] Comparative Example 3 The preparation method of the silicon epitaxial wafer of this comparative example, the remaining steps and parameters of the preparation method are the same as those of Example 3, except that step (2) is not performed, that is, the polycrystalline silicon coating layer is not grown on the graphite base. Figure 3 As shown, there are a few micro cracks on the edge of the silicon epitaxial wafer prepared in this comparative example.

[0045] Comparative Example 4 The preparation method of the silicon epitaxial wafer of this comparative example, the remaining steps and parameters of the preparation method are the same as those of Example 3, except that in step (4), the initial growth step with a lower growth rate is not performed, that is, the growth of the silicon epitaxial layer is performed as follows: the temperature in the reaction chamber of the silicon epitaxial furnace is 1040°C, the hydrogen flow rate is 150 L / min, the flow rate of trichlorosilane is 10 g / min, and the silicon epitaxial layer growth rate is 1.8 μm / min, until the target silicon epitaxial layer thickness is achieved. Figure 4 As shown, there are a few micro cracks on the edge of the silicon epitaxial wafer prepared in this comparative example.

[0046] Comparative Example 5 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that in step (4), the temperature in the reaction chamber of the silicon epitaxial furnace is 1060°C. Figure 5 As shown, there are a few micro cracks on the edge of the silicon epitaxial wafer prepared in this comparative example.

[0047] Comparative Example 6 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that in step (4), the temperature in the reaction chamber of the silicon epitaxial furnace is 1020° C., corresponding to a growth rate of the silicon epitaxial layer of 1.65 μm / min.

[0048] Comparative Example 7 The preparation method of the silicon epitaxial wafer of this comparative example, the remaining steps and parameters of the preparation method are the same as those of Example 3, except that in step (4), when the silicon epitaxial layer is grown, the initial trichlorosilane flow rate is 4 g / min, the initial growth rate of the silicon epitaxial layer is 0.9 μm / min, and after the growth time is maintained for 2 minutes, the trichlorosilane flow rate is adjusted to 13 g / min, and the growth rate of the silicon epitaxial layer is 2.1 μm / min. Figure 6 As shown, there are a few micro cracks on the edge of the silicon epitaxial wafer prepared in this comparative example.

[0049] Comparative Example 8 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that in step (4), when the silicon epitaxial layer is grown, the initial flow rate of trichlorosilane is 4 g / min, the initial growth rate of the silicon epitaxial layer is 0.9 μm / min, and after the growth time is maintained for 2 minutes, the flow rate of trichlorosilane is adjusted to 9 g / min, and the growth rate of the silicon epitaxial layer is 1.7 μm / min.

[0050] Comparative Example 9 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that the time for growing the polycrystalline silicon coating layer in step (2) is 140 seconds.

[0051] Comparative Example 10 The remaining steps and parameters of the preparation method of the silicon epitaxial wafer of this comparative example are the same as those of Example 3, except that the time for growing the polycrystalline silicon coating layer in step (2) is 320 seconds.

[0052] Silicon epitaxial wafers were prepared in batches by the methods of the above-mentioned embodiments and comparative examples, and the thickness of the silicon epitaxial wafers was measured. The five test positions of the thickness of the silicon epitaxial wafers were the center point with the main reference upward and four points 6 mm away from the edge just above, below, left and right of the center point. The average thickness of the silicon epitaxial wafer was calculated based on the five test positions. The probability of silicon epitaxial wafers with microcracks in the silicon epitaxial wafers prepared in batches in the embodiments and comparative examples was calculated, that is, the ratio of the number of silicon epitaxial wafers with microcracks to the total number of silicon epitaxial wafers. It can be seen from the comparison of the following embodiments and comparative examples that in the preparation method of the present invention, a small adjustment of parameters such as silicon coating time, wafer placement temperature, growth temperature, and growth rate will produce significant differences in the quality of thick silicon epitaxial wafers with a target silicon epitaxial layer thickness of 50 to 120 μm. The preparation process of the present invention is adjusted within the parameter range defined by the present invention, and the prepared thick silicon epitaxial wafers will not produce microcracks. The preparation and mass production of silicon epitaxial wafers with a diameter of 125-200 mm and a target silicon epitaxial layer thickness of 50-120 μm are achieved under the condition of simple process and batch repetition. The preparation methods of comparative examples 2, 6, 8, and 10, although no microcracks are produced, significantly increase the preparation time of silicon epitaxial wafers due to the increase in cooling time, the decrease in growth rate, the extension of silicon coating time, etc., greatly reduce the production capacity of silicon epitaxial wafers, and obviously cannot meet the current requirements for industrial mass production of silicon epitaxial wafers.

[0053] Table 1

[0054] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A method for preparing a silicon epitaxial wafer capable of reducing edge microcrack defects, characterized in that: The thickness of the silicon epitaxial layer of the silicon epitaxial wafer is 50-120 μm, and the preparation method comprises the following steps in sequence: S1. Etching the reaction chamber of the silicon epitaxial furnace and the graphite base in the reaction chamber; S2. The graphite base is subjected to silicon coating; S3. Place a silicon substrate sheet in the pit of the graphite base in the reaction chamber of the silicon epitaxial furnace; S4. Hydrogen and trichlorosilane are introduced into the reaction chamber of the silicon epitaxial furnace to grow a silicon epitaxial layer on the surface of the silicon substrate. The initial trichlorosilane flow rate is 4-6 g / min, and the initial growth rate of the silicon epitaxial layer is 0.9-1.1 μm / min. After the growth time is maintained for 1-2 min, the trichlorosilane flow rate is adjusted to 10-12 g / min and the growth rate of the silicon epitaxial layer is 1.8-2.0 μm / min until the target silicon epitaxial layer thickness is reached to obtain a silicon epitaxial wafer.

2. The preparation method according to claim 1, characterized in that: Step S1 includes: introducing hydrogen gas and hydrogen chloride gas into the reaction chamber of the silicon epitaxial furnace to etch the reaction chamber and the graphite base of the silicon epitaxial furnace; The temperature of the reaction chamber of the silicon epitaxial furnace is 1080~1100℃.

3. The preparation method according to claim 2, characterized in that: In step S1, the hydrogen flow rate is 20-50 L / min, the hydrogen chloride gas flow rate is 34-36 L / min, and the etching time is 7-15 min.

4. The preparation method according to claim 1, characterized in that: Step S2 includes: introducing hydrogen and trichlorosilane into a reaction chamber of a silicon epitaxial furnace to grow a polysilicon coating layer on a graphite base; The hydrogen flow rate is 140~160 L / min, the trichlorosilane flow rate is 10~14 g / min, and the time for growing the polysilicon coating is 150~300 sec.

5. The preparation method according to claim 1, characterized in that: In step S3, the temperature in the reaction chamber of the silicon epitaxial furnace is 280-300°C.

6. The preparation method according to claim 1, characterized in that: In step S4, the temperature in the reaction chamber of the silicon epitaxial furnace is 1030-1050°C.

7. The preparation method according to claim 1, characterized in that: In step S4, the hydrogen flow rate is 140-160 L / min.

8. The preparation method according to claim 1, characterized in that: The silicon epitaxial furnace is a flat-plate multi-wafer silicon epitaxial furnace.

9. The preparation method according to claim 1, characterized in that: The crystal orientation of the silicon substrate is <111> , diameter is 125~200 mm, resistivity is 0.001~0.005 Ω·cm, and oxygen content is 8~12 ppma.

10. A silicon epitaxial wafer capable of reducing edge microcrack defects, prepared by the preparation method according to any one of claims 1 to 9.

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