Chip and chip detection method

Abstract

The invention provides a chip, which comprises a to-be-tested signal source configured to generate a to-be-tested signal; the statistical module is connected with the to-be-detected signal source and is configured to generate a statistical result in a digital form according to the waveform of the to-be-detected signal; the statistical result comprises statistical data, the statistical data represents a waveform of the to-be-tested signal in a target clock period, and the waveform of the to-be-tested signal in the target clock period is different from the waveform of the to-be-tested signal in a previous clock period; and the statistical output end is configured to output the statistical result. The invention further provides a chip detection method.

Description

Technical Field

[0001] The present disclosure relates to the technical field of chip detection, and in particular to a chip and a chip detection method. Background Art

[0002] Chips in the form of field programmable gate arrays (FPGAs) may need to be tested in some cases.

[0003] However, existing chip detection methods are complicated and cannot be implemented in many cases. Summary of the invention

[0004] The present disclosure provides a chip and a chip detection method.

[0005] In a first aspect, an embodiment of the present disclosure provides a chip, comprising:

[0006] A signal source to be tested, configured to generate a signal to be tested;

[0007] A statistical module connected to the signal source to be tested, configured to generate a statistical result in digital form according to the waveform of the signal to be tested; the statistical result includes statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in the previous clock cycle;

[0008] A statistical output terminal is configured to output the statistical result.

[0009] In a second aspect, an embodiment of the present disclosure provides a chip detection method, which includes:

[0010] The statistical module of the chip generates a statistical result in digital form according to the waveform of the signal to be tested generated by the signal source to be tested in the chip; the statistical result includes statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in the previous clock cycle;

[0011] The statistical result is read from the statistical output terminal of the chip.

[0012] In the embodiment of the present disclosure, the statistical module in the chip can convert the signal to be detected (the signal to be tested) into a digital signal in the form of 0 or 1 (statistical result), and the statistical result only represents the waveform of the time period (target time period) in which the signal changes, so it is "compressed" and has a small amount of data. When the statistical result actually represents the complete waveform of the signal to be tested, the embodiment of the present disclosure is equivalent to obtaining the waveform of the signal to be tested through a digital signal, and completing chip detection without using special detection equipment. The method is simple and can be implemented under any circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In the accompanying drawings of the embodiments of the present disclosure:

[0014] Figure 1 A block diagram of a chip provided in an embodiment of the present disclosure;

[0015] Figure 2 A block diagram of another chip provided in an embodiment of the present disclosure;

[0016] Figure 3 A flowchart of a chip detection method provided by an embodiment of the present disclosure;

[0017] Figure 4 A flowchart of another chip detection method provided by an embodiment of the present disclosure;

[0018] Figure 5 A schematic diagram of a signal processing process in another chip detection method provided by an embodiment of the present disclosure;

[0019] Figure 6 A schematic diagram of a signal processing process in another chip detection method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the chip and the chip detection method provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0021] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0022] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0023] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0024] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0025] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0026] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0027] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0028] Chips in the form of field programmable gate array (FPGA) need to be tested during the debugging process, at the time of shipment, when a fault occurs, etc., that is, the waveform of some signals in the chip (the signal to be tested) is obtained, and the waveform is analyzed to see whether it is consistent with the preset value, so as to locate and eliminate the fault.

[0029] For example, in some related technologies, the waveform of the signal to be tested inside the chip can be read out and analyzed through a JTAG (Joint Test Action Group) probe or an ILA (Integrated Logic Analyzer) probe.

[0030] For example, in some other related technologies, the waveform of the signal to be tested inside the chip can also be pulled to the pin of the chip through a specific device, and then analyzed after being read out.

[0031] Therefore, chip detection in related technologies must be performed using specific detection equipment, which, on the one hand, complicates the chip detection process and, on the other hand, makes it impossible to perform chip detection in many cases (such as when the chip is in use).

[0032] First, refer to Figures 1 to 6 , an embodiment of the present disclosure provides a chip.

[0033] The chip of the embodiment of the present disclosure is a separately packaged device with data processing capability, which has multiple pins for externally receiving and outputting data.

[0034] In some embodiments, the chip includes an FPGA.

[0035] As a method of an embodiment of the present disclosure, the chip may specifically be in the form of an FPGA. Since the FPGA is programmable, it is more suitable for the embodiment of the present disclosure.

[0036] It should be understood that the chip of the embodiment of the present disclosure may also be in other forms such as an integrated circuit (IC).

[0037] Reference Figure 1 , the chip of the embodiment of the present disclosure includes:

[0038] A signal source to be tested, configured to generate a signal to be tested;

[0039] A statistical module connected to the signal source to be tested, configured to generate a statistical result in digital form according to the waveform of the signal to be tested; the statistical result includes statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in the previous clock cycle;

[0040] A statistics output terminal is configured to output statistical results.

[0041] Reference Figure 1 In the chip of the embodiment of the present disclosure, there are one or more signal sources (functional modules) that can generate signals, and some of the signal sources (signal sources to be tested) generate signals (signals to be tested) that need to be tested during the chip testing process.

[0042] A statistical module is added to the chip of the embodiment of the present disclosure, and all the signals to be tested are input into the statistical module (that is, the signal sources to be tested are all connected to the statistical module). The statistical module can convert the waveform of the input signal to be tested into a digital signal (statistical data) in the form of 0, 1 (such as using 0 to indicate that one bit of the waveform is a low level, and 1 to indicate that one bit of the waveform is a high level), and add it to the statistical result.

[0043] The chip works in units of a certain clock cycle (T). Therefore, if the waveform of the signal to be tested in a certain clock cycle is different from the waveform in the previous clock cycle, then the clock cycle (the waveform has a different clock cycle) is called the "target clock cycle".

[0044] The above statistical data represents and only represents the waveform of the signal to be tested in the target clock cycle. That is, in multiple consecutive clock cycles, if the waveform of the signal to be tested is the same, it is only necessary to record the data of the waveform in the first clock cycle, thereby saving computing power and storage resources.

[0045] It should be understood that for the "first" clock cycle after the detection starts, there is no other clock cycle in front of it, so its waveform can be regarded as different from the waveform of the previous clock cycle, and therefore it must be the target clock cycle.

[0046] Since the statistical results generated above are digital signals, they can be output through the statistical output terminal (such as a conventional pin) on the chip for further analysis of the statistical results, restoring the waveform of the signal to be tested, and realizing chip detection.

[0047] That is, the embodiment of the present disclosure first converts the waveform of the signal to be tested into a compressed digital signal inside the chip, and then reads out the digital signal. Through analysis, the complete waveform of the signal to be tested can be restored (because the waveform of the unchanged clock cycle is the same as the waveform of the previous target time period).

[0048] It should be understood that the specific form of the statistical results obtained from the statistical output terminal can be various, for example, it can be a text document.

[0049] In the embodiment of the present disclosure, the statistical module in the chip can convert the signal to be detected (the signal to be tested) into a digital signal in the form of 0 or 1 (statistical result), and the statistical result only represents the waveform of the time period (target time period) in which the signal changes, so it is "compressed" and has a small amount of data. When the statistical result actually represents the complete waveform of the signal to be tested, the embodiment of the present disclosure is equivalent to obtaining the waveform of the signal to be tested through a digital signal, and completing chip detection without using special detection equipment. The method is simple and can be implemented under any circumstances.

[0050] Reference Figure 2 In some embodiments, the statistics module includes:

[0051] The statistical unit is configured to: in response to at least one bit of the signal to be tested jumping relative to the corresponding bit in the previous clock cycle in any clock cycle, determine the clock cycle as a target clock cycle, and generate statistical data characterizing the waveform of the signal to be tested in the target clock cycle.

[0052] Reference Figure 2 As one embodiment of the present disclosure, the statistical module may include a statistical unit, and the statistical unit compares the waveform of the signal to be tested in each clock cycle with the waveform in the previous clock cycle. As long as any bit is found to be different, the current clock cycle is used as the target clock cycle, and statistical data corresponding to the target clock cycle is generated.

[0053] In some embodiments, generating statistical data characterizing the waveform of the signal under test in the target clock cycle includes: recording the value of each bit of the signal under test in the target clock cycle as statistical data.

[0054] As one method of an embodiment of the present disclosure, the statistical data of each target clock cycle may include the value of each bit of the signal under test in the target clock cycle (such as using 0 or 1 to represent the level of the waveform of each bit of the signal under test).

[0055] It should be understood that it is also feasible if the statistical data only includes information about the “bits” of the signal to be tested that are different from those in the previous target clock cycle.

[0056] In some embodiments, the statistics module includes:

[0057] a marking unit configured to generate a cycle mark corresponding to a clock cycle;

[0058] The statistical result of the clock cycle also includes a cycle mark corresponding to the clock cycle.

[0059] As mentioned above, the statistical data represents the waveform of the signal under test in the target clock cycle. The statistical results should further distinguish which clock cycle the statistical data corresponds to. Figure 2 The statistical module may also include a marking unit, which is used to generate a "cycle mark" corresponding to each clock cycle. Therefore, in the target clock cycle, the corresponding cycle mark and statistical data are used together as the final statistical result (such as the first line of a text document is the mark of the target clock cycle, followed by the statistical data of the corresponding target clock cycle).

[0060] For example, the marking unit may be a counter that counts once for each clock cycle, so that the cycle mark of each clock cycle may be the count value of the counter in the clock cycle.

[0061] It should be understood that the counter has a certain number of bits, and it will flip over and start counting again after reaching the maximum count value of the bit. For example, assuming that the counter is 32 bits, it will theoretically flip once every 43 seconds at a clock frequency of 100Mhz. Therefore, the number of bits of the selected counter cannot be too low, so as to avoid frequent flipping during a detection process and generating the same count value (cycle mark) in multiple clock cycles.

[0062] Reference Figure 2 In some embodiments, there are multiple signal sources to be tested; the statistical module further includes:

[0063] a bundling unit configured to bundle the test signals of the plurality of test signal sources in a predetermined order in each clock cycle to obtain a bundled signal;

[0064] Generating a statistical result in digital form according to the waveform of the signal to be tested includes: generating a statistical result in digital form according to the waveform of the bundled signal.

[0065] Reference Figure 2 As one method of an embodiment of the present disclosure, there may be multiple signal sources to be tested (signals to be tested), that is, there will be multiple signals to be tested in a clock cycle, so the embodiment of the present disclosure needs to generate statistical results corresponding to multiple signals to be tested in one clock cycle.

[0066] For this purpose, please refer to Figure 2 , Figure 5 A bundling unit is provided, which is used to receive different test signals in a clock cycle, and bundle (splice) these test signals in a predetermined order to generate a bundled signal.

[0067] Therefore, the duration of the above bundled signal is also a clock cycle, but its bit width is larger (equal to the sum of the bit widths of all the signals to be tested), wherein each bit represents a specific bit in a specific signal to be tested.

[0068] Furthermore, the statistical unit can generate "total" statistical data for each target clock cycle based on the bundled signal (such as using 0 or 1 to represent the levels of different bits of the bundled signal waveform in turn), and in the statistical data of each target clock cycle, each test signal corresponds to one or more bits at a predetermined position.

[0069] It should be understood that the above bundled signal only means that each test signal should be processed logically in the order of arrangement, so it is "equivalent to" the existence of a bundled signal spliced ​​in a predetermined order, but does not mean that a bundled signal must be actually generated physically.

[0070] In some embodiments, generating statistical results in digital form based on the waveform of the bundled signal includes: in response to at least one bit of the bundled signal jumping relative to the corresponding bit in the previous clock cycle in any clock cycle, determining the clock cycle as a target clock cycle, and recording the value of each bit of the bundled signal in the target clock cycle as statistical data.

[0071] For simplicity, the waveform of the bundled signal in each clock cycle may be directly compared with the waveform of the bundled signal in the previous clock cycle. If there is at least one bit different, all bits of the bundled signal in the target clock cycle are recorded as statistical data.

[0072] It should be understood that it is also feasible to determine target clock periods for different signals to be tested respectively and generate statistical results corresponding to the different signals to be tested respectively.

[0073] Reference Figure 2 In some embodiments, the statistics module further includes:

[0074] A mask unit configured to generate a mask signal corresponding to the bundled signal according to a mask setting; the mask signal includes a masking segment and / or a passing segment;

[0075] Generating a statistical result in digital form according to the waveform of the bundled signal includes: generating a statistical result in digital form according to the waveform of the corresponding pass segment of the bundled signal.

[0076] In order to realize the statistics of all possible test signals, all test signal sources in the chip must be connected to the statistical unit. However, in the specific chip detection process, it is not necessary to detect all test signals, but only some of them may be used; therefore, if the "unused" test signals are still counted at this time, it will cause a waste of computing power and storage space.

[0077] For this purpose, please refer to Figure 2 , Figure 6 , set a mask unit, which generates a corresponding mask signal according to which test signals are useful and which are useless in each detection. The position of the test signal that does not need to be detected in the corresponding bundled signal in the mask signal is a "masked segment (such as 0)", and the position of the test signal that needs to be detected in the corresponding bundled signal is a "pass segment (such as 1)".

[0078] Further, see Figure 6 The masking segment in the mask signal can "cover up" the corresponding part of the bundled signal, so the statistical module (such as the statistical unit) can only process the part of the bundled signal corresponding to the "passing segment", that is, only generate statistical data corresponding to this part of the bundled signal, which is equivalent to reducing the bit width of the bundled signal actually processed, which can save computing power and storage space.

[0079] Reference Figure 2 , as one embodiment of the present disclosure,

[0080] In some embodiments, the chip further includes a cache module:

[0081] The statistics module is also configured to write the statistics results into the cache module;

[0082] The statistics output terminal is configured to read the statistics results from the cache module.

[0083] Reference Figure 2 As one embodiment of the present disclosure, a cache module (such as a cache) is of course provided in the chip, so the statistical results generated by the above statistical module can be written into the cache module, and the statistical results can be read from the cache module when needed, thereby reducing changes to the chip structure.

[0084] It should be understood that it is also feasible to use a dedicated storage unit to store the statistical results.

[0085] Second, refer to Figures 1 to 6 , an embodiment of the present disclosure provides a chip detection method.

[0086] The chip detection method of the embodiment of the present disclosure is implemented based on the chip of the embodiment of the present disclosure.

[0087] Reference Figure 3 The chip detection method of the embodiment of the present disclosure includes:

[0088] S201. A statistical module of the chip generates a statistical result in digital form according to the waveform of a signal to be tested generated by a signal source to be tested in the chip.

[0089] The statistical results include statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in a previous clock cycle.

[0090] S202: Read the statistical result from the statistical output terminal of the chip.

[0091] Reference Figure 1 , Figure 3 According to the embodiment of the present disclosure, a signal to be tested may be generated inside the chip during detection, and the above statistical module obtains statistical results (including compressed statistical data) based on the signal to be tested, so that the above statistical results can be read out through the statistical output terminal as the result of chip detection.

[0092] Reference Figure 4 In some embodiments, after reading the statistical result from the statistical output terminal of the chip (S202), the method further includes:

[0093] S203: Analyze the waveform of the signal source to be tested according to the statistical results.

[0094] Reference Figure 5The statistical results in the form of digital signals obtained above can be further used to "restore" the actual waveform of each signal to be tested according to each digit (such as first restoring the actual waveform of the bundled signal, and then decomposing the actual waveform of each signal to be tested), and each waveform can be analyzed to achieve detection.

[0095] It should be understood that since the statistical results are the same as the actual content represented by the waveform, it is feasible to directly analyze the digital signal without restoring the waveform.

[0096] That is, the overall process of the chip detection method of the embodiment of the present disclosure includes:

[0097] (1) Send instructions to the chip to start chip detection.

[0098] (2) The chip continues to run and inputs the test signals of each test signal source into the bundling unit. The bundling unit bundles the test signals in a predetermined order in each clock cycle to obtain a bundled signal.

[0099] (3) The bundled signal is input to a statistical unit, which compares whether the bundled signal in each clock cycle is exactly the same as the bundled signal in the previous clock cycle.

[0100] (4) If the bundled signal in a certain clock cycle is different from the bundled signal in the previous clock cycle, it is determined to be the target clock cycle, and the statistical unit outputs the value of each bit of the bundled signal in the clock cycle as statistical data; if the bundled signal in a certain clock cycle is exactly the same as the bundled signal in the previous clock cycle, the statistical unit does not need to output the corresponding statistical data.

[0101] (5) The marking unit (such as a counter) counts in units of clock cycles. If a clock cycle statistics unit outputs statistical data (that is, there is a target clock cycle), the marking unit adds the current count value as a cycle mark before the statistical data.

[0102] (6) The statistical data with cycle marks are stored in the cache module as statistical results.

[0103] (7) When necessary, read the statistical results in the cache module from the statistical output terminal.

[0104] (8) Use external equipment to process the statistical results, restore the waveform of the bundled signal, and then further decompose the waveform of each signal to be tested.

[0105] (9) Chip detection is achieved by analyzing the waveform of the signal to be tested.

[0106] Example 1:

[0107] The following is an exemplary introduction to a chip and a detection method thereof according to an embodiment of the present disclosure.

[0108] During the RTL (Register Transfer Level) code design phase of the FPGA (chip), a separate RTL code is designed to send the test signals that require attention to a common module (statistical module). The common module obtains the compressed statistical results and writes them into the RAM (Random Access Memory, Register Transfer Level) cache (cache module) for subsequent reading from the CPU interface (statistical output end) and restoring the waveform.

[0109] Specifically, assume that the signals to be tested include: s_sop[0:0]..., s_num[7:0], s_rst[0:0], etc., where the content after s_ indicates the name of the signal, and [B:A] indicates that the bits occupied by the signal are from A to B, that is, the bit width of the signal to be tested.

[0110] Therefore, the chip detection method of the embodiment of the present disclosure includes:

[0111] (1) In each clock cycle, the 32-bit counter (mark unit) in the common module generates a mark value (cycle mark).

[0112] (2) In each clock cycle, the common module bundles the signals to be tested in sequence to obtain a signal A (bundled signal) with a bit width of 256 bits.

[0113] Among them, a list of internal signal names and bit widths is maintained in the order of bundling for later waveform recovery. For example, signal A can be represented as {s_sop[0:0]..., s_num[7:0], s_rst{0:0]}.

[0114] (3) In each clock cycle, the common module also generates a signal B (mask signal), whose bit width is the same as that of signal A, also 256 bits. The bit of 1 represents a passed segment, and the bit of 0 represents a masked segment.

[0115] (4) In each clock cycle, the common module counts the waveform of the portion of signal A that corresponds to the 0 bit of signal B, writes 0 to the bit corresponding to the low level of the waveform, and writes 1 to the bit corresponding to the high level of the waveform, thereby obtaining statistical data consisting of a series of 01 codes (in digital form).

[0116] (5) In each clock cycle, the common module analyzes whether signal A has changed (i.e., whether the statistical data is the same as that of the previous clock cycle); if not, the count value is obtained from the counter and the count value is added to the front of the statistical data of the clock cycle to obtain the statistical result of the clock cycle.

[0117] (6) If a statistical result is generated in a certain clock cycle, the common module writes the statistical result into RAM.

[0118] Therefore, referring to Table 1 below, the final statistical result may not be continuous, but only corresponds to the clock cycle in which part of the signal changes.

[0119] (7) When the detection time is reached, the statistical results in the RAM are read out from the CPU interface and stored as a text document (txt file), where the statistical results of each clock cycle correspond to one line of the text document.

[0120] Therefore, when the counter is 32 bits and the signal A is 256 bits (assuming no masking is performed), each line of the text document is 32+256=288 bits.

[0121] (7) Use software parsing tools such as GTKWave and ModelSim to process the text document and convert it into a waveform file in a universal format such as vcd (to restore the waveform of the signal to be tested).

[0122] For example, as shown in Table 1 below, assuming that the count value of the first line of the text document is 949, the values ​​of the s_sop[0:0], s_num[7:0], and s_rst{0:0] signals are 0, 0000101 (that is, 5), and 0, respectively; the count value of the second line of the text document is 955, where s_sop[0:0] becomes 1 (that is, the waveform of s_sop[0:0] is different, resulting in the statistics of the target clock cycle); the count value of the third line of the text document is 956, where s_sop[0:0] becomes 0 again; the count value of the third line of the text document is 999, where the value of s_rst{0:0] becomes 1 (that is, the waveform of s_rst{0:0] is different, resulting in the statistics of the clock cycle).

[0123] Table 1. Statistical results

[0124]

[0125] Furthermore, as shown in Table 2 below, the waveform of each signal to be tested in each clock cycle can be restored based on the above statistical results.

[0126] Table 2. Waveform of s_sop[0:0] in each clock cycle

[0127] Clock cycle number s_sop[0:0] 949 0 950 0 951 0 952 0 953 0 954 0 955 1 956 0 957 0 ... 0 999 0

[0128] It should be understood that the specific data of the waveform should correspond to the type of the waveform file. For example, in a waveform file in vcd format, s_sop is replaced by the character "a", and the clock cycle is represented by a number starting from 0 (#0, #1, #1), etc., which will not be described in detail here.

[0129] It should be understood that the specific format of the statistical results read out, the specific software analysis tool used, the specific format of the waveform file, etc. are not limited to the above examples.

[0130] Those skilled in the art will appreciate that all or some of the steps, systems, and functional modules / units in the apparatus disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0131] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0132] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0133] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A chip, wherein: include: A signal source to be tested, configured to generate a signal to be tested; A statistical module connected to the signal source to be tested, configured to generate a statistical result in digital form according to the waveform of the signal to be tested; the statistical result includes statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in the previous clock cycle; A statistical output terminal is configured to output the statistical result.

2. The chip according to claim 1, wherein: The statistics module includes: The statistical unit is configured to: in response to at least one bit of the signal to be tested jumping in any clock cycle relative to the corresponding bit in the previous clock cycle, determine that the clock cycle is a target clock cycle, and generate statistical data characterizing the waveform of the signal to be tested in the target clock cycle.

3. The chip according to claim 2, wherein: The generating of statistical data characterizing the waveform of the signal to be tested within the target clock cycle includes: The value of each bit of the signal to be tested in the target clock cycle is recorded as the statistical data.

4. The chip according to claim 1, wherein: The statistics module also includes: a marking unit configured to generate a cycle mark corresponding to the clock cycle; The statistical result of the clock cycle also includes a cycle mark corresponding to the clock cycle.

5. The chip according to claim 1, wherein: The number of the signal sources to be tested is multiple; the statistical module also includes: a bundling unit configured to bundle the test signals of the plurality of test signal sources in a predetermined order in each clock cycle to obtain a bundled signal; The generating of the statistical result in digital form according to the waveform of the signal to be tested includes: generating the statistical result in digital form according to the waveform of the bundled signal.

6. The chip according to claim 5, wherein: The method of generating statistical results in digital form based on the waveform of the bundled signal includes: in response to at least one bit of the bundled signal jumping relative to the corresponding bit in the previous clock cycle in any clock cycle, determining that the clock cycle is a target clock cycle, and recording the value of each bit of the bundled signal in the target clock cycle as the statistical data.

7. The chip according to claim 5, wherein: The statistics module also includes: A mask unit configured to generate a mask signal corresponding to the bundled signal according to a mask setting; the mask signal includes a mask segment and / or a pass segment; Generating a statistical result in digital form according to the waveform of the bundled signal includes: generating a statistical result in digital form according to the waveform of the corresponding pass segment of the bundled signal.

8. The chip according to claim 1, wherein: The chip also includes a cache module: The statistical module is further configured to write the statistical results into the cache module; The statistical output terminal is configured to read the statistical result from the cache module.

9. A chip detection method, wherein: include: The statistical module of the chip generates a statistical result in digital form according to the waveform of the signal to be tested generated by the signal source to be tested in the chip; The statistical result includes statistical data, the statistical data characterizes the waveform of the signal to be tested in a target clock cycle, and the waveform of the signal to be tested in the target clock cycle is different from the waveform in a previous clock cycle; The statistical result is read from the statistical output terminal of the chip.

10. The method according to claim 9, wherein: After reading the statistical result from the statistical output terminal of the chip, the method further includes: The waveform of the signal source to be tested is analyzed according to the statistical result.

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