Method for generating mask pattern, semiconductor packaging device and manufacturing method

Abstract

The embodiment of the present application provides a method for generating a mask pattern, a semiconductor packaging device and a manufacturing method. The method for generating a mask pattern is used to manufacture a semiconductor packaging device, and the semiconductor packaging device includes a redistribution layer formed on a semiconductor substrate according to the mask pattern. The method for generating the mask pattern includes: receiving an initial mask pattern; when there is a target inner angle that satisfies a first inner angle condition in the initial mask pattern, performing arc passivation treatment on the target inner angle in the initial mask pattern so that an arc transition is formed between the two sides constituting the target inner angle; wherein the initial mask pattern is subjected to arc passivation treatment to form an arc passivation mask pattern; the first inner angle condition is that the inner angle is not greater than 90°; performing logical operation processing on the arc passivation mask pattern to obtain a target mask pattern. Through the embodiment of the present application, the possibility of the insulating layer film of the redistribution layer breaking or falling off is reduced, and the performance of the semiconductor packaging device is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing technology, and specifically to a method for generating a mask pattern, a semiconductor packaging device, and a manufacturing method. Background Art

[0002] With the advancement of semiconductor manufacturing technology and the improvement of semiconductor device integration, redistribution layer (RDL) technology is widely used in high-density semiconductor packaging devices. Specifically, the redistribution layer is usually a stacked structure of a metal signal line layer and an insulating layer formed on a semiconductor substrate, wherein the shape and position of the metal signal line layer are defined by a specific mask pattern to connect the internal circuit of the chip with the external pins, and realize electrical connection and signal transmission between chips or between chips and other components. Therefore, the design and manufacture of the redistribution layer directly affects the electrical performance, signal integrity and reliability of semiconductor packaging devices.

[0003] The design of the mask pattern is crucial to improving the electrical characteristics and mechanical stability of the redistribution layer. However, as the semiconductor process nodes continue to shrink, especially for process nodes below 28nm, in the process of manufacturing the redistribution layer using the mask pattern designed according to the mask pattern design method in the prior art, the insulating layer film covering the metal signal line layer of the redistribution layer is prone to partial detachment, which in turn causes electrical leakage and reduces the performance of the semiconductor packaging device. Summary of the invention

[0004] In view of this, multiple embodiments of the present application provide a method for generating a mask pattern, a semiconductor packaging device, and a manufacturing method to improve the performance of the semiconductor packaging device.

[0005] In one aspect, an embodiment of the present application provides a method for generating a mask pattern, the method being used to manufacture a semiconductor packaging device, the semiconductor packaging device comprising a redistribution layer formed on a semiconductor substrate according to the mask pattern; the method comprising: receiving an initial mask pattern; when there is a target inner angle satisfying a first inner angle condition in the initial mask pattern, performing arc passivation processing on the target inner angle in the initial mask pattern so as to form an arc transition between two sides constituting the target inner angle; wherein, the initial mask pattern forms an arc passivation mask pattern after the arc passivation processing; the first inner angle condition is that the inner angle is not greater than 90°; performing logical operation processing on the arc passivation mask pattern to obtain a target mask pattern.

[0006] Optionally, when there is a target inner angle satisfying a first inner angle condition in the initial mask pattern, the target inner angle in the initial mask pattern is subjected to arc passivation processing so that an arc transition is formed between two sides constituting the target inner angle, the step comprising: screening the inner angle of the initial mask pattern based on the first inner angle condition to obtain a target inner angle satisfying the first inner angle condition; screening the target inner angle based on a second inner angle condition to obtain a first target inner angle satisfying the second inner angle condition and a second target inner angle not satisfying the second inner angle condition; wherein the second inner angle condition is that there exists a specified window figure in the angle area formed by the vertex of the target inner angle and the two sides, and there is a specified positional relationship between the angle area and the specified window figure; and different arc passivation processing methods are used to perform arc passivation processing on the first target inner angle and the second target inner angle respectively, so that the arc transition figure between the two sides constituting the first target inner angle is different from the arc transition figure between the two sides constituting the second target inner angle.

[0007] Optionally, the specified position relationship includes: the distance between the specified window graphic and two sides constituting the target inner angle is not greater than 1 m.

[0008] Optionally, the semiconductor packaging device further includes a passivation layer and a via; the passivation layer is formed on a side of the redistribution layer close to the semiconductor substrate, and the via is formed on a side of the redistribution layer away from the semiconductor substrate; the designated window pattern includes a passivation layer window pattern and a via window pattern; the passivation layer window pattern is located at a projection position of a passivation layer window in the passivation layer on the redistribution layer, and the via window pattern is located at a projection position of the via on the redistribution layer.

[0009] Optionally, different arc passivation processing methods are used to perform arc passivation processing on the first target inner angle and the second target inner angle respectively, so that the arc transition figure between the two sides constituting the first target inner angle is different from the arc transition figure between the two sides constituting the second target inner angle. The steps include: using an outward-expanding arc passivation processing method to perform arc passivation processing on the first target inner angle to form an outward-expanding arc transition figure; using an inward-expanding arc passivation processing method to perform arc passivation processing on the second target inner angle to form an inward-expanding arc transition figure.

[0010] Optionally, the angle area formed by the vertex and two sides of the first target inner angle is the first target inner angle figure; the first target inner angle is subjected to arc passivation processing by using an outward-expanding arc passivation processing method to form an outward-expanding arc transition figure, comprising: determining any point in the first target inner angle figure as the first center point; forming an outward-expanding correction arc based on the first center point on the basis of the first target inner angle figure; wherein the outward-expanding correction arc intersects with the two sides of the first target inner angle; the figure enclosed by the vertex of the first target inner angle, the two sides of the first target inner angle and the outward-expanding correction arc is the outward-expanding figure; the vertex of the first target inner angle is located on the outward-expanding correction arc or in the outward-expanding figure; and the outward-expanding figure is superimposed on the first target inner angle figure to form the outward-expanding arc transition figure.

[0011] Optionally, the angle area formed by the vertex and two sides of the second target inner angle is the second target inner angle figure; the step of performing arc passivation treatment on the second target inner angle using the inward arc passivation treatment method to form an inward arc transition figure includes: determining any point in the second target inner angle figure as the second center point; forming an inward correction arc based on the second target inner angle figure based on the second center point; wherein the inward correction arc intersects with the two sides of the second target inner angle, and the inward correction arc is located in the second target inner angle figure; the figure enclosed by the vertex of the second target inner angle, the two sides of the second target inner angle and the inward correction arc is the inward figure; the inward figure is removed on the basis of the second target inner angle figure to form the inward arc transition figure.

[0012] Optionally, the inner corner of the initial mask pattern has a pattern length parameter and an inner corner line width parameter; based on the pattern length parameter and the inner corner line width parameter, the target inner corner in the initial mask pattern is subjected to arc passivation processing so that an arc transition is formed between two sides constituting the target inner corner.

[0013] In another aspect, an embodiment of the present application provides a semiconductor packaging device, comprising a redistribution layer formed on a semiconductor substrate according to a target mask pattern; wherein the target mask pattern is generated according to the mask pattern generation method described in the above embodiment.

[0014] In another aspect, an embodiment of the present application provides a method for manufacturing a semiconductor packaging device, the method comprising: providing a semiconductor substrate; forming a redistribution layer on the semiconductor substrate according to a target mask pattern; wherein the target mask pattern is generated according to the mask pattern generation method described in the above embodiment.

[0015] In multiple embodiments provided in the present application, when a target inner angle not greater than 90° is screened out in an initial mask pattern for manufacturing a redistribution layer, an arc passivation treatment is performed on the target inner angle so that an arc transition is formed between the two sides constituting the target inner angle to obtain an arc passivation mask pattern, and then the arc passivation mask pattern is subjected to logical operation processing to obtain a target mask pattern. The unexpected effects achieved include: by performing an arc passivation treatment on the target inner angle not greater than 90° in the mask pattern, in the process of manufacturing the redistribution layer according to the target mask pattern, the concentration of stress on the insulating layer film deposited near the target inner angle is reduced, thereby reducing the possibility of breakage or falling off of the insulating layer film, and improving the performance of the semiconductor packaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 A schematic structural diagram of a semiconductor substrate provided for related technology.

[0018] Figure 2 A schematic diagram of the structure of a semiconductor packaging device provided for related technology.

[0019] Figure 3 The image of the redistribution layer insulation layer film peeling off in the semiconductor packaging device provided by the related technology from a cross-sectional perspective.

[0020] Figure 4 A schematic flow chart of a method for generating a mask pattern provided for one embodiment of the present application.

[0021] Figure 5 A schematic diagram of pattern length parameters and inner corner line width parameters of an inner corner in an initial mask pattern provided for one embodiment of the present application.

[0022] Figure 6 A schematic diagram of a process for performing arc passivation processing on a target inner corner in an initial mask pattern is provided for one embodiment of the present application.

[0023] Figure 7 A schematic diagram of forming an outward-expanding arc transition pattern provided for one embodiment of the present application.

[0024] Figure 8 A schematic diagram of an outward-expanding arc transition graphic provided for one embodiment of the present application.

[0025] Fig. 9 (a) is a schematic diagram of the stress concentration degree before the outward arc passivation treatment provided in an embodiment of the present application.

[0026] Fig. 9 (b) is a schematic diagram of the stress concentration degree after the outward arc passivation treatment provided in an embodiment of the present application.

[0027] Fig.10 A schematic diagram of a process for forming an inwardly contracted arc transition pattern is provided for one embodiment of the present application.

[0028] Fig.11 A schematic diagram of an inward-contracted arc transition pattern provided for one embodiment of the present application.

[0029] Structure number description

[0030] 100, semiconductor substrate; 110, top metal layer; 111, chip signal line; 112, isolation layer; 113, filling layer; 114, through hole; 120, bottom device layer; 200, redistribution layer; 210, redistribution layer signal line; 220, insulation layer; 300, dielectric layer; 400, passivation layer window; 500, outward expansion arc transition pattern; 501, first target inner corner pattern; 502, specified window pattern; 503, outward expansion pattern; 600, inward contraction arc transition pattern; 601, second target inner corner pattern; 602, inward contraction pattern. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0032] The drawings provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complicated.

[0033] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc., indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features.

[0034] The redistribution layer plays a key role in semiconductor high-density packaging technologies such as System in Package (SIP), Wafer Level Chip Scale Package (WLCSP) and Fan-Out Packaging because of its advantages of increasing input / output pin density, reducing package volume, improving packaged device performance and reducing package costs.

[0035] In the related art, the redistribution layer is usually formed on a semiconductor substrate on which chip signal lines have been arranged. Figure 1 The semiconductor substrate 100 may include a top metal layer 110 and a bottom device layer 120. The top metal layer 110 may be used to arrange chip signal lines 111 to form input / output ports of chip circuits, and realize chip signal and power distribution. The bottom device layer 120 may be used to provide support for the top metal layer 110, and a variety of semiconductor devices may be integrated therein.

[0036] The top metal layer 110 may include a chip signal line 111, an isolation layer 112, and a filling layer 113. Specifically, the chip signal line 111 may be a signal transmission line of a chip circuit, and its material may be a conductive metal such as copper (Cu), aluminum (Al), and tungsten (W). The isolation layer 112 may be used to isolate different lines to reduce short circuits and signal crosstalk between lines. The material of the isolation layer 112 may be silicon oxide, silicon nitride, and the like. The filling layer 113 may be used to fill the area not occupied by the chip signal line 111 to improve the electrical performance and mechanical stability of the chip. The material of the filling layer 113 may be the same as or different from that of the chip signal line 111. For example, when the material of the chip signal line 111 is copper, the material of the filling layer 113 may be copper to reduce electromigration and improve the reliability of the chip circuit. A through hole 114 (TV) for establishing an electrical connection between the chip signal line 111 and the redistribution layer signal line may also be formed at a position corresponding to the chip signal line 111 in the isolation layer 112 and the filling layer 113. The present application does not impose any specific limitation on the manufacturing method of each structure in the semiconductor substrate 100 .

[0037] The bottom device layer 120 may have functions such as realizing thermal management of semiconductor packaged devices and improving the integration of semiconductor packaged devices. Specifically, the semiconductor devices integrated in the bottom device layer 120 may include: various types of chips such as logic chips, memory chips, analog chips, etc.; passive devices such as resistors, capacitors and inductors for filtering and voltage stabilization of circuits; sensors such as temperature sensors and pressure sensors for monitoring environmental conditions in semiconductor packaged devices; RF switches, filters and other RF components for wireless communication, as well as voltage regulators, voltage converters and other power management devices for power management and distribution. The bottom device layer 120 may be a single-layer structure or a multi-layer structure. The present application does not impose specific restrictions on the specific structure of the bottom device layer 120 and the semiconductor devices integrated in the bottom device layer 120.

[0038] See also Figure 2. The redistribution layer 200 formed on the semiconductor substrate 100 may include a redistribution layer signal line 210 and an insulating layer 220. Specifically, the redistribution layer signal line 210 is the core of the redistribution layer 200, and can be used to realize the connection between the input / output ports of different chips or the connection between the input / output port of the chip and the input / output port of the external device. Similar to the material of the chip signal line 111, the material of the redistribution layer signal line 210 can be a conductive metal such as copper (Cu), aluminum (Al), and tungsten (W). Similar to the isolation layer 112, the insulating layer 220 can be used to isolate different lines of the redistribution layer 200 to reduce short circuits and signal crosstalk between lines. The preparation method thereof can be: using a process such as Chemical Vapor Deposition (CVD) to deposit insulating materials such as silicon oxide and silicon nitride on the redistribution layer signal line 210 to form a flat film. Therefore, the thickness of the insulating layer 220 is relatively small, and its shape is determined by the shape of the redistribution layer signal line 210.

[0039] After the redistribution layer 200 is formed, a dielectric layer 300 may be formed on the redistribution layer 200 to improve the isolation performance between different lines of the redistribution layer 200 and provide physical protection for the lines in the redistribution layer 200. A passivation layer window 400 is also formed in the dielectric layer 300 at a position corresponding to the redistribution layer signal line 210 to facilitate the subsequent preparation of the passivation layer.

[0040] As the semiconductor process node shrinks to below 28nm, in order to match the chip feature size, the line width of the redistribution layer signal line 210 in the redistribution layer 200 is gradually reduced to the micron level. Accordingly, in order to reduce the influence of the voltage drop (IR) of the redistribution layer signal line 210 connected to the chip signal line 111 on the electrical performance of the semiconductor package device, it is necessary to increase the thickness of the redistribution layer signal line 210 in the direction perpendicular to the semiconductor substrate 100.

[0041] The shape of the redistribution layer signal line 210 is determined based on a specific mask pattern. When the width of the redistribution layer signal line 210 is reduced and the thickness is increased, the researchers found that when the mask pattern designed using the existing mask pattern design method is used to first manufacture the redistribution layer signal line 210 and then deposit the insulating layer 220 on the redistribution layer signal line 210, part of the insulating layer 220 will break or fall off, and electrical leakage is easily caused at the location where the insulating layer 220 breaks or falls off, resulting in reduced performance or even failure of the semiconductor packaging device.

[0042] Further investigation of the reasons for the breakage or fall-off of the insulating layer 220 shows that there are internal angles of no more than 90° in the redistribution layer signal line 210. Since the line width of the redistribution layer signal line 210 is small and the thickness is large, for the insulating layer 220 deposited near these internal angles, less material is deposited on the vertex of the internal angle, while more material is deposited on the two sides of the internal angle. In addition, the material deposited on the vertex of the internal angle will be subjected to more concentrated stress, resulting in this part of the material being more fragile and prone to breakage or fall-off. Please refer to Figure 3 The researchers used an electron microscope to observe the redistribution layer where electrical leakage had occurred and found that the insulating layer deposited near the inner angle of the redistribution layer signal line no greater than 90° was more likely to break. Figure 3 The area circled by the white circle is where the insulation layer is broken.

[0043] Therefore, it is necessary to provide a method for generating a mask pattern. After receiving an initial mask pattern, an arc passivation treatment is performed on a target inner angle not greater than 90° in the initial mask pattern so that an arc transition can be formed between the two sides of the target inner angle. Then, a logical operation is performed on the arc passivation mask pattern obtained after the arc passivation treatment to obtain a target mask pattern. Therefore, when a redistribution layer is manufactured according to the target mask pattern, the stress concentration of the insulating layer film deposited near the inner corner of the redistribution layer signal line can be reduced, and the possibility of breakage or falling off of the insulating layer film can be reduced, thereby reducing electrical leakage and improving the performance of semiconductor packaging devices.

[0044] See also Figures 4 to 11 One embodiment of the present application provides a method for generating a mask pattern. The method for generating a mask pattern can be used to manufacture a semiconductor package device, and the semiconductor package device can include a redistribution layer formed on a semiconductor substrate according to the mask pattern.

[0045] The semiconductor substrate in this embodiment has a similar structure to that in the related art. The redistribution layer in this embodiment also includes a redistribution layer signal line and an insulating layer. The functions, materials, and preparation methods of the redistribution layer signal line and the insulating layer are similar to those of the redistribution layer signal line and the insulating layer in the related art, and will not be repeated here.

[0046] The method for generating a mask pattern provided in this embodiment can be executed by a mask pattern design software used for designing and simulating mask patterns. Figure 4 The method for generating the mask pattern may include the following steps.

[0047] S110: receiving an initial mask pattern.

[0048] In the supply chain of semiconductor packaging devices, the design and manufacture of mask patterns are different links and may be implemented by different companies. Therefore, in order to solve the problem of performance degradation of semiconductor packaging devices caused by breakage or peeling of the insulating layer in the redistribution layer, reduce the modification and adjustment of the mask pattern design rules, and reduce the design cost, the initial mask pattern designed according to conventional design rules can be optimized at the mask pattern manufacturing company.

[0049] In this embodiment, the initial mask pattern may be a mask pattern designed according to existing mask pattern design rules for defining the arrangement of redistribution layer signal lines. Specifically, the existing mask pattern design rules may include design rules for specific structures such as line width and line spacing design rules, window pattern design rules, and insulation layer design rules, as well as overall design rules such as signal integrity design rules, mechanical stability design rules, manufacturing accuracy design rules, and test design rules.

[0050] In this embodiment, the initial mask pattern can be input into the mask pattern design software by automatic calling instructions or manual operation, so that the mask pattern design software receives the initial mask pattern. Specifically, in the mask pattern design software, the processing of the initial mask pattern can be realized by executing a specified control instruction.

[0051] S120: When there is a target inner angle satisfying the first inner angle condition in the initial mask pattern, arc passivation processing is performed on the target inner angle in the initial mask pattern so that an arc transition is formed between two sides constituting the target inner angle.

[0052] When the inner angles of the redistribution layer signal lines are acute or right angles, the insulating layer deposited near these inner angles is susceptible to relatively concentrated stress. Since the inner angles in the redistribution layer signal lines are defined by the mask pattern, in order to reduce the breakage or falling off of the insulating layer in the redistribution layer, these inner angles can be rounded and passivated during the mask pattern design process to reduce the concentration of stress on the insulating layer film deposited near these inner angles.

[0053] In this embodiment, the first internal angle condition may be that the internal angle is not greater than 90°.

[0054] See also Figure 5 In this embodiment, the inner corner of the initial mask pattern may have a pattern length parameter and an inner corner line width parameter. The process of performing arc passivation processing on the target inner corner in the initial mask pattern may be implemented based on the pattern length parameter and the inner corner line width parameter, so that an arc transition is formed between the two sides constituting the target inner corner. Specifically, in the process of editing the control instruction executed by the mask pattern design software, the pattern length parameter and the inner corner line width parameter may be used as parameters that need to be called by the control instruction.

[0055] In this embodiment, the initial mask pattern is subjected to arc passivation treatment to form an arc passivation mask pattern. Specifically, since the arc passivation mask pattern is formed by performing arc passivation treatment on all target inner angles not greater than 90° in the initial mask pattern, there is no inner angle not greater than 90° in the arc passivation mask pattern.

[0056] See also Figures 6 to 11 When there is a target inner angle satisfying the first inner angle condition in the initial mask pattern, performing arc passivation processing on the target inner angle in the initial mask pattern so as to form an arc transition between two sides constituting the target inner angle may include the following steps.

[0057] S121: Screening the inner angles of the initial mask pattern based on the first inner angle condition to obtain a target inner angle that satisfies the first inner angle condition.

[0058] In this embodiment, the control instructions executed by the mask pattern design software can be edited to traverse all the internal angles in the initial mask pattern, and select the internal angles not greater than 90° as the target internal angles.

[0059] S122: Screening the target inner angles based on the second inner angle condition to obtain a first target inner angle that meets the second inner angle condition and a second target inner angle that does not meet the second inner angle condition.

[0060] In addition to the arrangement of the signal lines in the redistribution layer, the mask pattern also needs to define the shape and position of the window pattern in the redistribution layer to reserve connection points for realizing electrical connection between the redistribution layer and the adjacent layers. In order to reduce the interference of the arc passivation treatment on the target inner corner in the initial mask pattern to the window pattern in the redistribution layer in the initial mask pattern, in this embodiment, the target inner corner can be classified according to the relative position relationship between the window pattern of the redistribution layer in the initial mask pattern and the target inner corner, and different types of target inner corners can be subjected to different arc passivation treatments.

[0061] In this embodiment, the second inner angle condition may be that a specified window graphic exists within an angle region formed by a vertex of the target inner angle and two sides, and a specified positional relationship exists between the angle region and the specified window graphic.

[0062] In this embodiment, the specified window pattern may include a passivation layer (PV) window pattern and a via (RDV) window pattern. Specifically, the semiconductor packaging device may further include a passivation layer and a via. The passivation layer may be used to support the redistribution layer and protect the circuits on the surface of the chip from interference from environmental factors, and it may be formed on the side of the redistribution layer close to the semiconductor substrate. The via is a vertical conductive structure that can be used to connect the redistribution layer and the chip circuit, and it may be formed on the side of the redistribution layer away from the semiconductor substrate. Accordingly, the passivation layer window pattern may be located at the projection position of the passivation layer window in the passivation layer on the redistribution layer, and the via window pattern may be located at the projection position of the via on the redistribution layer.

[0063] Since the inward arc passivation process needs to remove part of the pattern in the target inner angle area, in order to avoid such removal affecting the shape and position of the passivation layer window pattern and the via window pattern located inside the target inner angle area, thereby affecting the subsequent processing technology, the outward arc passivation process can be performed on the target inner angle when the distance between the specified window pattern and the two sides of the target inner angle is short. Therefore, in this embodiment, the specified position relationship may include: the distance between the specified window pattern and the two sides constituting the target inner angle is not greater than 1 m. Specifically, the distance between the designated window graphic and the two sides constituting the target inner angle can be measured using the mask pattern design software. For example, the mask pattern design software can first traverse all the target inner angles in the initial mask pattern to determine whether there is a designated window graphic within the angle region of each target inner angle. In the case where it is identified that the designated window graphic does not exist within the angle region of the target inner angle, the target inner angle is determined to be a second target inner angle that does not satisfy the second inner angle condition. In the case where it is identified that the designated window graphic exists within the angle region of the target inner angle, each point in the designated window graphic is traversed again to calculate the distance between these points and the two sides constituting the target inner angle, and to determine whether there is a point in the designated window graphic whose distance to any side constituting the target inner angle is not greater than 1. m. In the case where the target point is identified in the specified window graphic, the target inner angle is determined to be the first target inner angle that satisfies the second inner angle condition. In the case where the target point is identified in the specified window graphic, the target inner angle is determined to be the second target inner angle.

[0064] S123: Performing arc passivation processing on the first target inner angle and the second target inner angle respectively using different arc passivation processing methods, so that the arc transition figure between the two sides constituting the first target inner angle is different from the arc transition figure between the two sides constituting the second target inner angle.

[0065] After the target inner angle is divided into the first target inner angle and the second target inner angle, different arc passivation processes may be respectively performed on the first target inner angle and the second target inner angle to obtain arc transition graphics of different shapes.

[0066] In this embodiment, different arc passivation processing methods are used to perform arc passivation processing on the first target inner angle and the second target inner angle respectively, so that the arc transition pattern between the two sides constituting the first target inner angle is different from the arc transition pattern between the two sides of the second target inner angle. The steps may include: using an outward-expanding arc passivation processing method to perform arc passivation processing on the first target inner angle to form an outward-expanding arc transition pattern; using an inward-expanding arc passivation processing method to perform arc passivation processing on the second target inner angle to form an inward-expanding arc transition pattern.

[0067] See also Figure 7 and Figure 8 . In this embodiment, the angle area formed by the vertex of the first target inner angle and the two sides is the first target inner angle figure 501, and the first target inner angle figure 501 contains a specified window figure 502. The steps of performing arc passivation processing on the first target inner angle using the outward-expanding arc passivation processing method to form an outward-expanding arc transition figure 500 may include: determining any point in the first target inner angle figure 501 as the first center point; forming an outward-expanding correction arc based on the first target inner angle figure 501 based on the first center point; and superimposing an outward-expanding figure 503 on the first target inner angle figure 501 to form an outward-expanding arc transition figure 500.

[0068] In this embodiment, the figure formed by the vertex of the first target inner angle, the two sides of the first target inner angle and the outward expansion correction arc is the outward expansion figure 503. The outward expansion correction arc can be formed with the first center point as the center and a specified value not less than the distance between the first center point and the vertex of the first target inner angle as the radius, wherein the outward expansion correction arc intersects with the two sides of the first target inner angle. When the specified value is equal to the distance between the first center point and the vertex of the first target inner angle, the vertex of the first target inner angle is located on the outward expansion correction arc, that is, Figure 7 When the specified value is greater than the distance between the first center point and the vertex of the first target inner angle, the vertex of the first target inner angle is located within the outward expansion figure 503 .

[0069] See also Fig. 9 (a) and Fig. 9 (b) Taking the arc passivation treatment of the first target inner corner by the outward arc passivation treatment method as an example, the concentration degree of stress on the insulating layer deposited near the inner corner of the redistribution layer signal line before and after the arc passivation treatment is explained. Fig. 9The arrow in (a) indicates the stress direction near the inner corner of the redistribution layer signal line manufactured according to the first target inner corner pattern 501 before the arc passivation process. Fig. 9 The arrow in (b) indicates the stress direction near the inner corner of the redistribution layer signal line manufactured according to the outward-expanded arc transition pattern 500 after the arc passivation treatment. Fig. 9 (a) and Fig. 9 The arrow in (b) points to the direction in which Fig. 9 The arrows in (a) point to the same direction, i.e., stress concentration near the inner corner of the redistribution layer signal line manufactured according to the first target inner corner pattern 501; Fig. 9 The arrows in (b) point to different directions, that is, the stress near the inner corner of the redistribution layer signal line manufactured according to the outward-expanded arc transition pattern 500 is dispersed. Therefore, after the arc passivation treatment is performed on the first target inner corner to form the arc transition pattern, the concentration of stress on the insulation layer deposited near the inner corner of the redistribution layer signal line manufactured according to the arc transition pattern is reduced.

[0070] See also Fig.10 and Fig.11 In this embodiment, the angle area formed by the vertex of the second target inner angle and the two sides is the second target inner angle figure 601. The step of performing arc passivation processing on the second target inner angle using the inward arc passivation processing method to form the inward arc transition figure 600 may include: determining any point in the second target inner angle figure 601 as the second center point; forming an inward correction arc based on the second target inner angle figure 601 based on the second center point; removing the inward figure 602 based on the second target inner angle figure 601 to form the inward arc transition figure 600.

[0071] In this embodiment, the process of forming the inward correction arc based on the second target inner angle figure 601 based on the second center point is similar to the process of forming the outward correction arc based on the first target inner angle figure 501 based on the first center point, and will not be repeated here. The inward correction arc intersects with the two sides of the second target inner angle, and the inward correction arc is located in the second target inner angle figure 601. The figure surrounded by the vertex of the second target inner angle, the two sides of the second target inner angle and the inward correction arc is the inward figure 602.

[0072] S130: performing logic operation processing on the arc passivation mask pattern to obtain a target mask pattern.

[0073] After arc passivation is performed on all target inner corners in the initial mask pattern to obtain an arc passivation mask pattern, Boolean logic operations, including AND, OR, NOT, XOR, and SUBTRACT operations, can be performed on the arc passivation mask pattern to correct logic errors in the arc passivation mask pattern and optimize the layout of the redistribution layer signal lines in the mask pattern to obtain a target mask pattern for manufacturing the redistribution layer signal lines.

[0074] In an embodiment of the present application, when a target inner angle not greater than 90° is screened out in an initial mask pattern for manufacturing a redistribution layer, an arc passivation treatment is performed on the target inner angle not greater than 90° in the initial mask pattern, so that an arc transition is formed between the two sides constituting the target inner angle, to obtain an arc passivation mask pattern, and then a logical operation is performed on the arc passivation mask pattern to obtain a target mask pattern for manufacturing a redistribution layer signal line. The unexpected effects achieved include: in the process of manufacturing the redistribution layer according to the target mask pattern, the concentration of stress on the insulating layer film deposited near the target inner angle is reduced, thereby reducing the possibility of breakage or falling off of the insulating layer film. On the one hand, the electrical leakage caused by the breakage or falling off of the insulating layer film is reduced, thereby improving the performance of the semiconductor packaging device; on the other hand, the number of defective products in the semiconductor packaging device is reduced, thereby improving the packaging yield of the semiconductor packaging device.

[0075] One embodiment of the present application provides a semiconductor packaging device, which may include a redistribution layer formed on a semiconductor substrate according to a target mask pattern, wherein the target mask pattern may be generated according to the mask pattern generation method described in the above embodiment.

[0076] An embodiment of the present application provides a method for manufacturing a semiconductor packaging device, which may include: providing a semiconductor substrate; forming a redistribution layer on the semiconductor substrate according to a target mask pattern; wherein the target mask pattern may be generated according to the mask pattern generation method described in the above embodiment.

[0077] Regarding the technical effects of the semiconductor packaging device and the method for manufacturing the semiconductor packaging device described in the above embodiments, reference can be made to other embodiments of the present application for comparative explanation and no further description will be given here.

[0078] It should be understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, rather than to limit the scope of this application.

[0079] It can be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0080] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0081] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application are the same as the meanings generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include majority forms, unless the context clearly indicates other meanings.

[0082] In several embodiments provided in this application, it should be understood that the disclosed semiconductor package device can be implemented in other ways. For example, the embodiments of the semiconductor package device described above are merely illustrative.

[0083] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for generating a mask pattern, the method being used for manufacturing a semiconductor package device, the semiconductor package device comprising a redistribution layer formed on a semiconductor substrate according to the mask pattern; characterized in that: The method comprises: receiving an initial mask pattern; In the case where there is a target inner angle satisfying a first inner angle condition in the initial mask pattern, arc passivation processing is performed on the target inner angle in the initial mask pattern so that an arc transition is formed between two sides constituting the target inner angle, including: Screening the inner angle of the initial mask pattern based on the first inner angle condition to obtain a target inner angle that satisfies the first inner angle condition; wherein the first inner angle condition is that the inner angle is not greater than 90°; The target inner angle is screened based on a second inner angle condition to obtain a first target inner angle that satisfies the second inner angle condition and a second target inner angle that does not satisfy the second inner angle condition; wherein the second inner angle condition is that a specified window graphic exists within an angle region formed by a vertex and two sides of the target inner angle, and a specified positional relationship exists between the angle region and the specified window graphic; The first target inner angle and the second target inner angle are respectively subjected to arc passivation treatment by using different arc passivation treatment methods, so that the arc transition pattern between the two sides constituting the first target inner angle is different from the arc transition pattern between the two sides constituting the second target inner angle; wherein the initial mask pattern forms an arc passivation mask pattern after the arc passivation treatment; A logic operation is performed on the arc passivation mask pattern to obtain a target mask pattern.

2. The method according to claim 1, characterized in that The specified position relationship includes: the distance between the specified window graphic and the two sides constituting the target inner angle is not greater than 1 m.

3. The method according to claim 2, characterized in that The semiconductor package device further comprises a passivation layer and a via hole; the passivation layer is formed on a side of the redistribution layer close to the semiconductor substrate, and the via hole is formed on a side of the redistribution layer away from the semiconductor substrate; The specified window pattern includes a passivation layer window pattern and a via window pattern; The passivation layer window pattern is located at a projection position of a passivation layer window in the passivation layer on the redistribution layer, and the via hole window pattern is located at a projection position of the via hole on the redistribution layer.

4. The method according to claim 1, characterized in that: The step of performing arc passivation processing on the first target inner angle and the second target inner angle respectively by using different arc passivation processing methods so that the arc transition pattern between the two sides constituting the first target inner angle is different from the arc transition pattern between the two sides constituting the second target inner angle comprises: Using an outward-expanding arc passivation processing method to perform arc passivation processing on the first target inner angle to form an outward-expanding arc transition pattern; The second target inner angle is subjected to arc passivation processing by adopting an inwardly contracted arc passivation processing method to form an inwardly contracted arc transition pattern.

5. The method according to claim 4, characterized in that The angle area formed by the vertex and two sides of the first target inner angle is the first target inner angle figure; The step of performing arc passivation processing on the first target inner angle by adopting an outward-expanding arc passivation processing method to form an outward-expanding arc transition pattern comprises: Determine any point in the first target inner angle figure as a first center point; Based on the first center point, an outward expansion correction arc is formed on the basis of the first target inner angle figure; wherein the outward expansion correction arc intersects with two sides of the first target inner angle; a figure enclosed by the vertex of the first target inner angle, the two sides of the first target inner angle and the outward expansion correction arc is an outward expansion figure; the vertex of the first target inner angle is located on the outward expansion correction arc or in the outward expansion figure; The outward expansion pattern is superimposed on the first target inner angle pattern to form the outward expansion arc transition pattern.

6. The method according to claim 4, characterized in that The angle area formed by the vertex and two sides of the second target inner angle is the second target inner angle figure; The step of performing arc passivation processing on the second target inner angle by adopting an inward arc passivation processing method to form an inward arc transition pattern comprises: Determine any point in the second target inner angle figure as a second center point; Based on the second center point, a retracted correction arc is formed on the basis of the second target inner angle figure; wherein the retracted correction arc intersects with two sides of the second target inner angle, and the retracted correction arc is located in the second target inner angle figure; the figure enclosed by the vertex of the second target inner angle, the two sides of the second target inner angle and the retracted correction arc is a retracted figure; The indented shape is removed on the basis of the second target inner angle shape to form the indented arc transition shape.

7. The method according to any one of claims 1 to 6, characterized in that: The inner corner of the initial mask pattern has a pattern length parameter and an inner corner line width parameter; arc passivation is performed on the target inner corner in the initial mask pattern based on the pattern length parameter and the inner corner line width parameter so that an arc transition is formed between two sides constituting the target inner corner.

8. A semiconductor packaging device, characterized in that: The semiconductor package device comprises a redistribution layer formed on a semiconductor substrate according to a target mask pattern; wherein the target mask pattern is generated according to the method for generating a mask pattern according to any one of claims 1 to 7.

9. A method for manufacturing a semiconductor packaging device, characterized in that: The method comprises: providing a semiconductor substrate; A redistribution layer is formed on the semiconductor substrate according to a target mask pattern; wherein the target mask pattern is generated according to the method for generating a mask pattern as claimed in any one of claims 1 to 7.

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