Low-dropout linear voltage stabilizing circuit and radio frequency module

Abstract

The invention relates to a low-dropout linear voltage stabilizing circuit and a radio frequency module. The low-dropout linear voltage stabilizing circuit comprises a charge pump, an isolation transistor, a transmission transistor, a feedback circuit and an operational amplifier, the charge pump is configured to receive an input power supply signal and boost the input power supply signal to generate a first gate end voltage signal. The first gate end voltage signal is provided for the control end of the isolation transistor; the second end of the isolation transistor is configured to receive an input power supply signal, and the first end of the isolation transistor is connected with the first end of the transmission transistor and configured to provide an operational amplifier power supply signal; the power supply end of the operational amplifier is configured to receive an operational amplifier power supply signal; and a cascode structure is formed at least based on the isolation transistor and the transmission transistor and is used for isolating transmission of power supply noise in the input power supply signal to the transmission transistor and the power supply end of the operational amplifier. According to the embodiment of the invention, the PSR performance of the low-dropout linear voltage stabilizing circuit can be improved.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a low voltage difference linear voltage regulator circuit and a radio frequency module. Background Art

[0002] LDO (low dropout regulator) is commonly used in power management. It has the characteristics of low static power consumption, low cost, no output ripple, and power supply rejection (PSR). And due to the development of CMOS technology, such as deep sub-micron gate length, various functional modules, such as analog, digital, RF and other circuit modules, can be integrated into one chip as a system.

[0003] The performance of these systems may be degraded due to the influence of noise from the power supply. Noise-sensitive circuit blocks such as analog-to-digital converters, phase-locked loops, and switching audio amplifiers can have their performance severely affected. Therefore, the power supply rejection capability of LDOs is often used to avoid degradation of the performance of noise-sensitive circuit blocks.

[0004] Therefore, it is crucial to improve the PSR capability of LDO. Summary of the invention

[0005] In view of this, the embodiments of the present application provide a low voltage difference linear voltage regulator circuit and a radio frequency module to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a low voltage difference linear voltage regulator circuit, wherein the low voltage difference linear voltage regulator circuit includes a charge pump, an isolation transistor, a transmission transistor, a feedback circuit and an operational amplifier;

[0007] The charge pump is configured to receive an input power supply signal and boost the input power supply signal to generate a first gate terminal voltage signal; the first gate terminal voltage signal is used to provide to the control terminal of the isolation transistor;

[0008] The second end of the isolation transistor is configured to receive the input power signal, and the first end of the isolation transistor is connected to the first end of the transmission transistor and is configured to provide an operational amplifier power signal;

[0009] The inverting input terminal of the operational amplifier is configured to receive a reference voltage signal, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback circuit, the output terminal of the operational amplifier is connected to the control terminal of the transmission transistor, the second terminal of the transmission transistor is respectively connected to the input terminal of the feedback circuit and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit, and the voltage stabilization output terminal is used to provide a voltage stabilization output signal; wherein the power supply terminal of the operational amplifier is configured to receive the operational amplifier power supply signal;

[0010] Wherein, at least a common source and common gate structure is formed based on the isolation transistor and the transmission transistor, so as to isolate the power supply noise in the input power supply signal from being transmitted to the transmission transistor and the power supply terminal of the operational amplifier.

[0011] In combination with the first aspect, in an optional implementation manner, the low voltage difference linear voltage stabilization circuit further includes a low-pass filter;

[0012] The low-pass filter is configured to low-pass filter the first gate terminal voltage signal to generate and output a second gate terminal voltage signal to the control terminal of the isolation transistor.

[0013] In combination with the first aspect, in an optional implementation, the charge pump adopts a Dickson charge pump having at least two-stage charge and discharge units;

[0014] Wherein, the charging and discharging unit includes an anti-reverse connection circuit using a MOS transistor.

[0015] In combination with the first aspect, in an optional implementation manner, the charge pump includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first boost capacitor, a second boost capacitor and an output capacitor;

[0016] The gate and source of the tenth PMOS transistor are connected and configured to receive an input power supply signal, the drain of the tenth PMOS transistor is respectively connected to the first end of the first boost capacitor, the gate of the eleventh PMOS transistor and the source of the eleventh PMOS transistor, the drain of the eleventh PMOS transistor is respectively connected to the first end of the second boost capacitor, the gate of the twelfth PMOS transistor and the source of the twelfth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the first end of the output capacitor and is configured to output the first gate terminal voltage signal;

[0017] The second end of the first boost capacitor is configured to receive a first clock signal; the second end of the second boost capacitor is configured to receive a second clock signal; the second end of the output capacitor is connected to the circuit ground;

[0018] The first clock signal and the second clock signal are clock signals with non-overlapping phases.

[0019] In combination with the first aspect, in an optional implementation manner, the low voltage difference linear voltage regulator circuit further includes a clock generation module;

[0020] The clock generation module is configured to generate oscillation under the stimulation of an enable start signal to generate and output a first clock signal and a second clock signal with two non-overlapping phases; the first clock signal and the second clock signal are respectively used to control the charge pump to generate a first gate voltage signal.

[0021] In combination with the first aspect, in an optional implementation, the clock generation module includes an oscillation module and a clock signal output module;

[0022] The oscillation module is configured to generate oscillation under the stimulation of the enable start signal to generate and output an oscillation signal;

[0023] The clock signal output module is configured to generate and output a first clock signal and a second clock signal with two non-overlapping phases under the control of the oscillation signal; the first clock signal includes a first high level and a first low level, the second clock signal includes a second high level and a second low level, the first high level and the second high level are respectively determined according to a first reference level, and the first low level and the second low level are respectively determined according to a second reference level.

[0024] In combination with the first aspect, in an optional implementation manner, the oscillation module includes a twentieth NMOS transistor and an odd number of first level conversion circuits connected in cascade;

[0025] The gate of the twentieth NMOS transistor is configured to input an enable start signal, the source of the twentieth NMOS transistor is connected to the second reference voltage terminal, and the drain of the twentieth NMOS transistor is configured to output an oscillation control signal;

[0026] The first level conversion circuit includes a first transistor and a second transistor connected in series between a first reference voltage terminal and a second reference voltage terminal, and a connection point between the first transistor and the second transistor is configured to output a first level conversion circuit output signal;

[0027] Among them, the first-stage first level conversion circuit is configured to be controlled by the oscillation control signal or the oscillation signal, and the first level conversion circuits of other stages are respectively configured to be controlled by the output signal of the first level conversion circuit of the previous stage, so that one of the first transistor and the second transistor is disconnected during the conduction period of the other.

[0028] In combination with the first aspect, in an optional implementation manner, the cascaded odd number of first level conversion circuits include a first-stage first level conversion circuit, a second-stage first level conversion circuit, a third-stage first level conversion circuit, a fourth-stage first level conversion circuit, and a fifth-stage first level conversion circuit;

[0029] The first-stage first level conversion circuit includes a twenty-first PMOS transistor and a twenty-second NMOS transistor, the gate of the twenty-first PMOS transistor is connected to the gate of the twenty-second NMOS transistor and is configured to input an oscillation control signal or an oscillation signal, the source of the twenty-first PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-second NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-first PMOS transistor is connected to the drain of the twenty-second NMOS transistor and is configured to output the first-stage first level conversion circuit output signal;

[0030] The second-stage first level conversion circuit includes a twenty-third PMOS transistor and a twenty-fourth NMOS transistor, the gate of the twenty-third PMOS transistor is connected to the gate of the twenty-fourth NMOS transistor and is configured to input the output signal of the first-stage first level conversion circuit, the source of the twenty-third PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-fourth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-third PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor and is configured to output the output signal of the second-stage first level conversion circuit;

[0031] The third-stage first level conversion circuit includes a twenty-fifth PMOS transistor and a twenty-sixth NMOS transistor, the gate of the twenty-fifth PMOS transistor is connected to the gate of the twenty-sixth NMOS transistor and is configured to input the output signal of the second-stage first level conversion circuit, the source of the twenty-fifth PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-sixth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-sixth NMOS transistor and is configured to output the output signal of the third-stage first level conversion circuit;

[0032] The fourth-stage first level conversion circuit includes a twenty-seventh PMOS transistor and a twenty-eighth NMOS transistor, the gate of the twenty-seventh PMOS transistor is connected to the gate of the twenty-eighth NMOS transistor and is configured to input the output signal of the third-stage first level conversion circuit, the source of the twenty-seventh PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-eighth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-eighth NMOS transistor and is configured to output the output signal of the fourth-stage first level conversion circuit;

[0033] The fifth-stage first level conversion circuit includes a twenty-ninth PMOS transistor and a thirtieth NMOS transistor, the gate of the twenty-ninth PMOS transistor is connected to the gate of the thirtieth NMOS transistor and is configured to input the output signal of the fourth-stage first level conversion circuit, the source of the twenty-ninth PMOS transistor is connected to the first reference voltage terminal, and the source of the thirtieth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-ninth PMOS transistor is connected to the drain of the thirtieth NMOS transistor and is configured to output an oscillation signal.

[0034] In combination with the first aspect, in an optional implementation manner, the clock signal output module includes a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor, and a thirty-fourth NMOS transistor;

[0035] a source of the thirty-first PMOS transistor connected to the first reference voltage terminal, a source of the thirty-second NMOS transistor connected to the second reference voltage terminal, a gate of the thirty-first PMOS transistor and a gate of the thirty-second NMOS transistor respectively configured to input the oscillation signal, and a drain of the thirty-first PMOS transistor and a drain of the thirty-second NMOS transistor connected to output the first clock signal;

[0036] a source of the thirty-third PMOS transistor connected to the first reference voltage terminal, a source of the thirty-fourth NMOS transistor connected to the second reference voltage terminal, a gate of the thirty-third PMOS transistor and a gate of the thirty-fourth NMOS transistor respectively configured to input the first clock signal, and a drain of the thirty-third PMOS transistor connected to a drain of the thirty-fourth NMOS transistor and configured to output the second clock signal;

[0037] And / or, the clock generation module further includes a current mirror circuit;

[0038] The current mirror circuit includes a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a forty-first NMOS transistor, a forty-second PMOS transistor, a forty-third PMOS transistor, a forty-fourth PMOS transistor, a forty-fifth PMOS transistor, a forty-sixth PMOS transistor and a forty-seventh PMOS transistor;

[0039] a drain of the thirty-fifth NMOS transistor configured to input a reference current signal and connected to the gate of the thirty-fifth NMOS transistor, the gate of the thirty-sixth NMOS transistor, the gate of the thirty-seventh NMOS transistor, the gate of the thirty-eighth NMOS transistor, the gate of the thirty-ninth NMOS transistor, the gate of the fortieth NMOS transistor, and the gate of the forty-first NMOS transistor, respectively;

[0040] The source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor, the source of the thirty-eighth NMOS transistor, the source of the thirty-ninth NMOS transistor, the source of the fortieth NMOS transistor, and the source of the forty-first NMOS transistor are respectively connected to the second reference voltage terminal, the drain of the thirty-seventh NMOS transistor is connected to the source of the twenty-second NMOS transistor, the drain of the thirty-eighth NMOS transistor is connected to the source of the twenty-fourth NMOS transistor, the drain of the thirty-ninth NMOS transistor is connected to the source of the twenty-sixth NMOS transistor, the drain of the fortieth NMOS transistor is connected to the source of the twenty-eighth NMOS transistor, and the drain of the forty-first NMOS transistor is connected to the source of the thirtieth NMOS transistor;

[0041] the drain of the thirty-sixth NMOS transistor is respectively connected to the drain of the forty-second PMOS transistor, the gate of the forty-second PMOS transistor, the gate of the forty-third PMOS transistor, the gate of the forty-fourth PMOS transistor, the gate of the forty-fifth PMOS transistor, the gate of the forty-sixth PMOS transistor, and the gate of the forty-seventh PMOS transistor;

[0042] The source of the forty-second PMOS transistor, the source of the forty-third PMOS transistor, the source of the forty-fourth PMOS transistor, the source of the forty-fifth PMOS transistor, the source of the forty-sixth PMOS transistor and the source of the forty-seventh PMOS transistor are respectively connected to the first reference voltage terminal, the drain of the forty-third PMOS transistor is connected to the source of the twenty-first PMOS transistor, the drain of the forty-fourth PMOS transistor is connected to the source of the twenty-third PMOS transistor, the drain of the forty-fifth PMOS transistor is connected to the source of the twenty-fifth PMOS transistor, the drain of the forty-sixth PMOS transistor is connected to the source of the twenty-seventh PMOS transistor, and the drain of the forty-seventh PMOS transistor is connected to the source of the twenty-ninth PMOS transistor.

[0043] In combination with the first aspect, in an optional implementation manner, the operational amplifier comprises a telescopic cascode amplifier;

[0044] And / or, the operational amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a Miller compensation capacitor;

[0045] The gate of the first NMOS transistor is configured as a non-inverting input terminal of the operational amplifier, the gate of the second NMOS transistor is configured as an inverting input terminal of the operational amplifier, and the drain of the fifth NMOS transistor is configured as an output terminal of the operational amplifier;

[0046] The drain of the first NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the second NMOS transistor is connected to the source of the fifth NMOS transistor; the drain of the fourth NMOS transistor is respectively connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor, and the drain of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor; the source of the sixth PMOS transistor is respectively connected to the drain of the eighth PMOS transistor, the gate of the eighth PMOS transistor and the gate of the ninth PMOS transistor, and the source of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor; the source of the eighth PMOS transistor and the source of the ninth PMOS transistor are respectively configured to receive the operational amplifier power supply signal; the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is connected to the circuit ground;

[0047] The gate of the third NMOS transistor is configured to receive a first low bias signal, and the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are respectively configured to receive a second low bias signal;

[0048] The first end of the Miller compensation capacitor is connected to the drain of the fifth NMOS transistor, the drain of the seventh PMOS transistor and the control end of the transmission transistor respectively, and the second end of the Miller compensation capacitor is connected to the voltage stabilization output end.

[0049] In combination with the first aspect, in an optional implementation manner, the isolation transistor is an NMOS transistor, whose gate, source and drain respectively correspond to the control terminal, the first terminal and the second terminal of the isolation transistor; the transmission transistor is a PMOS transistor, whose gate, source and drain respectively correspond to the control terminal, the first terminal and the second terminal of the transmission transistor;

[0050] And / or, the low-pass filter includes a filter resistor and a filter capacitor;

[0051] The first end of the filter resistor is connected to the output end of the charge pump for receiving the first gate voltage signal; the second end of the filter resistor is respectively connected to the first end of the filter capacitor and the control end of the isolation transistor for outputting the second gate voltage signal; the second end of the filter capacitor is connected to the circuit ground;

[0052] And / or, the feedback circuit includes a first resistor and a second resistor;

[0053] The non-inverting input terminal of the operational amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor, the second end of the transmission transistor is respectively connected to the first end of the first resistor and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit; the second end of the second resistor is connected to the circuit ground.

[0054] In a second aspect, an embodiment of the present application provides a radio frequency module, wherein the radio frequency module includes the low voltage difference linear voltage regulator circuit as described in the first aspect.

[0055] The beneficial effects brought by the technical solution provided by the embodiment of the present application include: utilizing the shielding characteristics of the cascode structure, and configuring the power supply terminal of the operational amplifier to receive the operational amplifier power supply signal provided by the isolation transistor, which can not only isolate the transmission of the power supply noise in the input power supply signal to the transmission transistor, but also isolate the transmission of the power supply noise to the power supply terminal of the operational amplifier, and comprehensively improve the PSR performance of the low-voltage difference linear voltage regulator circuit. And the input power supply signal is boosted by a charge pump, thereby generating a first gate terminal voltage signal to provide to the control terminal of the isolation transistor, so that the isolation transistor has the characteristic of low voltage difference; at the same time, the charge pump is used to power the operational amplifier without the need for other external power supplies, and the circuit structure can be simplified, which is conducive to the miniaturization of the low-voltage difference linear voltage regulator circuit and the module in which the circuit is located.

[0056] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0058] Figure 1 This is a circuit diagram of Example 1 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application;

[0059] Figure 2This is a circuit diagram of Example 2 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application;

[0060] Figure 3 This is a circuit diagram of Example 3 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application;

[0061] Figure 4 This is a circuit diagram of Example 4 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application;

[0062] Figure 5 A circuit diagram of a specific example of a clock generation module in an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0064] The embodiments of the present application are not exhaustive, but are only illustrative of some embodiments, and are not intended to be a specific limitation on the scope of protection of the present application. In the absence of contradiction, each step in a certain embodiment can be implemented as an independent embodiment, and the steps can be arbitrarily combined. For example, in a certain embodiment, the solution after removing some steps can also be implemented as an independent embodiment, and the order of the steps in a certain embodiment can be arbitrarily exchanged. In addition, the optional implementations in a certain embodiment can be arbitrarily combined; in addition, the embodiments can be arbitrarily combined, for example, some or all of the steps of different embodiments can be arbitrarily combined, and a certain embodiment can be arbitrarily combined with the optional implementations of other embodiments.

[0065] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0066] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0067] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0068] In the embodiments of the present application, "plurality" refers to two or more.

[0069] In some embodiments, the terms "at least one", "one or more", "a plurality of", "multiple", etc. can be used interchangeably.

[0070] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0071] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0072] Figure 1 The circuit diagram of Example 1 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application is shown. As shown in the figure, the low voltage difference linear voltage regulator circuit includes a charge pump CP, an isolation transistor MC, a transmission transistor MP, a feedback circuit FB and an operational amplifier;

[0073] The charge pump CP is configured to receive an input power signal vddldo and boost the input power signal vddldo to generate a first gate voltage signal; the first gate voltage signal is used to provide to the control terminal of the isolation transistor MC;

[0074] The second end of the isolation transistor MC is configured to receive the input power signal vddldo, and the first end of the isolation transistor MC is connected to the first end of the pass transistor MP and is configured to provide an operational amplifier power signal vddea;

[0075] The inverting input terminal of the operational amplifier is configured to receive a reference voltage signal vref, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback circuit FB, the output terminal of the operational amplifier is connected to the control terminal of the transmission transistor MP, the second terminal of the transmission transistor MP is respectively connected to the input terminal of the feedback circuit FB and the regulated output terminal of the low voltage difference linear voltage regulator circuit, and the regulated output terminal is used to provide a regulated output signal vldo; wherein the power supply terminal of the operational amplifier is configured to receive the operational amplifier power supply signal vddea;

[0076] Among them, at least a common source and common gate structure is formed based on the isolation transistor MC and the transfer transistor MP, which is used to isolate the power supply noise in the input power supply signal vddldo from being transmitted to the transfer transistor MP and the power supply terminal of the operational amplifier.

[0077] In the embodiments of the present application, the low voltage dropout linear voltage regulator circuit may be referred to by different names, such as a low voltage dropout linear regulator, a low voltage dropout voltage regulator circuit, a low voltage dropout regulator, an LDO circuit, etc., and the names are not limited here.

[0078] The input power signal vddldo may include power noise, such as power ripple. The input power signal vddldo may be provided through a circuit power supply terminal, and the circuit ground terminal vssldo may be grounded.

[0079] The isolation transistor MC and the transmission transistor MP may include at least one of a PMOS transistor (P-type metal oxide semiconductor field effect transistor, referred to as PMOS transistor), an NMOS transistor (N-type metal oxide semiconductor field effect transistor, referred to as NMOS transistor), a BJT transistor (bipolar junction transistor, commonly known as triode), etc., which has a control terminal, a first terminal and a second terminal, and its working principle is that under the control of a control signal input to the control terminal, the path between the first terminal and the second terminal is turned on or off to connect or block the signal transmission between the first terminal and the second terminal. For example, the first terminal may be a source or an emitter, and correspondingly, the second terminal may be a drain or a collector; or conversely, the first terminal may be a drain or a collector, and correspondingly, the second terminal may be a source or an emitter. Exemplarily, the transmission transistor MP may also include at least one of the following: IGBT (insulated gate bipolar transistor), GTO (gate turn-off thyristor), SCR (silicon controlled thyristor), MCT (MOS controlled thyristor), IGCT (integrated gate commutated thyristor), IEGT (electron injection enhanced gate transistor).

[0080] Exemplarily, the operational amplifier may include an error amplifier EA. The isolation transistor MC may be an NMOS transistor. The transfer transistor MP may be a PMOS transistor. The capacitor CL is a load capacitor, and the resistor RL is a load resistor.

[0081] like Figure 1 As shown, in the low voltage difference linear voltage regulator circuit of the embodiment of the present application, the main circuit loop is mainly formed by the error amplifier EA, the transmission transistor MP and the feedback circuit FB. By utilizing the shielding characteristics of the common source and common gate (cascode) structure formed by the isolation transistor MC and the transmission transistor MP, the power supply end of the error amplifier EA in the main loop receives the operational amplifier power supply signal vddea provided by the isolation transistor MC, which can isolate the power supply noise of the error amplifier EA; and can isolate the power supply noise and transmit it to the voltage stabilization output end through the transmission transistor MP, thereby improving the PSR performance of the low voltage difference linear voltage regulator circuit.

[0082] In some possible implementations, the charge pump CP may include a voltage doubling charge pump, which may utilize the control of a switch element to store and release the input voltage through a capacitor through a charging and discharging stage, thereby ultimately doubling the output voltage. The specific structure of the charge pump CP may be set according to actual needs, such as a diode rectifier circuit, a Dickson charge pump, etc.

[0083] In this way, the embodiment of the present application utilizes the shielding characteristics of the cascode structure, and configures the power supply terminal of the operational amplifier to receive the operational amplifier power supply signal provided by the isolation transistor, which can not only isolate the transmission of the power supply noise in the input power supply signal to the transmission transistor, but also isolate the transmission of the power supply noise to the power supply terminal of the operational amplifier, thereby comprehensively improving the PSR performance of the low-voltage difference linear voltage regulator circuit. The input power supply signal is boosted by a charge pump, thereby generating a first gate terminal voltage signal to provide to the control terminal of the isolation transistor, so that the isolation transistor has a low voltage difference characteristic; at the same time, the charge pump is used to power the operational amplifier without the need for other external power supplies, and the circuit structure can be simplified, thereby facilitating the miniaturization of the low-voltage difference linear voltage regulator circuit and the module in which the circuit is located.

[0084] Figure 2 The circuit diagram of Example 2 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application is shown. As shown in the figure, in an optional implementation, the low voltage difference linear voltage regulator circuit further includes a low pass filter LPF;

[0085] The low-pass filter LPF is configured to low-pass filter the first gate-terminal voltage signal to generate and output a second gate-terminal voltage signal to the control terminal of the isolation transistor MC.

[0086] In some possible implementations, the low-pass filter LPF may include at least one of an RC low-pass filter, an RLC low-pass filter, an RL low-pass filter and other high-pass filters, and may be set according to actual needs.

[0087] In this way, the embodiment of the present application can reduce the impact of the ripple of the charge pump CP output voltage on the control end of the isolation transistor MC (such as the gate of the NMOS transistor) through the low-pass filter LPF, thereby further improving the PSR performance of the low-voltage difference linear regulator circuit.

[0088] In an optional embodiment, the charge pump CP adopts a Dickson charge pump having at least two-stage charge and discharge units;

[0089] Wherein, the charging and discharging unit includes an anti-reverse connection circuit using a MOS transistor.

[0090] In some possible implementations, the specific number of stages of the Dickson charge pump can be set according to the voltage value actually required to be boosted, such as one stage, two stages, three stages, etc., which are not listed here in detail.

[0091] In some possible implementations, the reverse connection protection circuit using a MOS transistor may include a body diode formed by connecting the source and gate of the MOS transistor, wherein the MOS transistor may include at least one of a PMOS transistor and an NMOS transistor.

[0092] In this way, the embodiment of the present application replaces the diode by adopting the anti-reverse connection circuit of the MOS transistor to form a Dickson charge pump based on the CMOS process, which can obtain almost zero voltage drop, thereby reducing power loss, improving energy utilization efficiency, and simplifying the circuit structure, which is conducive to miniaturization.

[0093] Figure 3 A circuit diagram of Example 3 of a low voltage difference linear voltage regulator circuit in an embodiment of the present application is shown. As shown in the figure, in an optional implementation, the charge pump CP includes a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a first boost capacitor C1, a second boost capacitor C2 and an output capacitor Co;

[0094] The gate and source of the tenth PMOS transistor M10 are connected and configured to receive the input power supply signal vddldo, the drain of the tenth PMOS transistor M10 is respectively connected to the first end of the first boost capacitor C1, the gate of the eleventh PMOS transistor M11 and the source of the eleventh PMOS transistor M11, the drain of the eleventh PMOS transistor M11 is respectively connected to the first end of the second boost capacitor C2, the gate of the twelfth PMOS transistor M12 and the source of the twelfth PMOS transistor M12, the drain of the twelfth PMOS transistor M12 is connected to the first end of the output capacitor Co and is configured to output the first gate terminal voltage signal;

[0095] The second end of the first boost capacitor C1 is configured to receive the first clock signal phia; the second end of the second boost capacitor C2 is configured to receive the second clock signal phib; the second end of the output capacitor Co is connected to the circuit ground terminal vssldo;

[0096] The first clock signal phia and the second clock signal phib are clock signals with non-overlapping phases.

[0097] In the embodiment of the present application, the first clock signal phia and the second clock signal phib, which do not overlap in two phases, are staggered in period to ensure that when one of the first clock signal phia and the second clock signal phib is at a high level, the other is always at a low level. In the embodiment of the present application, the high level and the low level can be relative values, not limited to absolute values.

[0098] The tenth PMOS transistor M10 and the first boost capacitor C1 can constitute a first-stage charge and discharge unit, the eleventh PMOS transistor M11 and the second boost capacitor C2 can constitute a second-stage charge and discharge unit, and the twelfth PMOS transistor M12 and the output capacitor Co can constitute a third-stage charge and discharge unit, thereby forming a three-stage Dickson charge pump based on CMOS process.

[0099] Thus, the embodiment of the present application can obtain the required voltage value of the first gate voltage signal according to the voltage value of the input power supply signal vddldo and the high-level voltage values ​​of the first clock signal phia and the second clock signal phib through a three-stage Dickson charge pump based on CMOS technology. And it has a simple structure and is easy to implement a bias voltage higher than the power supply voltage to the control end of the isolation transistor MC, so that the isolation transistor MC achieves a low voltage difference.

[0100] The Dickson charge pump can realize the charging and discharging of the capacitor by controlling the on and off time of the switch based on the control of the clock signal, thereby gradually increasing the output voltage. The switch may include at least one of a diode, a MOS transistor, a BJT transistor, an IGBT, a GTO, a SCR, a MCT, an IGCT, and an IEGT. The specific circuit structure for generating the clock signal can be set according to actual needs. Figure 4 The circuit diagram of Example 4 of the low voltage difference linear voltage regulator circuit in the embodiment of the present application is shown. As shown in the figure, the low voltage difference linear voltage regulator circuit also includes a clock generating module CG (clock generator);

[0101] The clock generating module CG is configured to generate oscillation under the stimulation of an enable start signal to generate and output a first clock signal phia and a second clock signal phib that do not overlap in two phases; the first clock signal phia and the second clock signal phib are respectively used to control the charge pump CP to generate a first gate voltage signal.

[0102] In the embodiment of the present application, the enable start signal may be a high pulse signal. By stimulating the clock generation module with a high pulse to generate oscillation, it is possible to avoid the situation where the power supply voltage is insufficient and the clock generation module cannot be stimulated to generate oscillation, thereby improving the stability of the clock generation module outputting the first clock signal and the second clock signal.

[0103] Figure 5 A circuit diagram of a specific example of a clock generation module in an embodiment of the present application is shown.

[0104] The specific circuit structure of the clock generation module CG can be set according to actual needs and is not limited thereto. As shown in the figure, in an optional embodiment, the clock generation module CG includes an oscillation module 21 and a clock signal output module 22;

[0105] The oscillation module 21 is configured to generate oscillation under the stimulation of the enable start signal en, so as to generate and output an oscillation signal;

[0106] The clock signal output module 22 is configured to generate and output a first clock signal phia and a second clock signal phib with two non-overlapping phases under the control of an oscillation signal; the first clock signal phia includes a first high level and a first low level, and the second clock signal phib includes a second high level and a second low level, the first high level and the second high level are respectively determined according to a first reference level, and the first low level and the second low level are respectively determined according to a second reference level.

[0107] In the embodiment of the present application, the first reference level can be provided by the first reference voltage terminal vdd, and the second reference level can be provided by the second reference voltage terminal vss. The first reference level can be set according to actual needs, for example, the voltage value of the first reference level can be based on the voltage value of the first gate terminal voltage signal required to be provided by the charge pump CP. The second reference level can be 0V, for example, grounded.

[0108] In this way, the embodiment of the present application realizes the conversion and output of two non-overlapping clock signals through the clock signal output module, and realizes output localization and improves stability by determining the first high level and the second high level according to the first reference level, and by determining the first low level and the second low level according to the second reference level.

[0109] In an optional implementation, the oscillation module 21 includes a twentieth NMOS transistor M20 and an odd number of first level conversion circuits connected in cascade;

[0110] The gate of the twentieth NMOS transistor M20 is configured to input the enable start signal en, the source of the twentieth NMOS transistor M20 is connected to the second reference voltage terminal vss, and the drain of the twentieth NMOS transistor M20 is configured to output the oscillation control signal;

[0111] The first level conversion circuit includes a first transistor and a second transistor connected in series between a first reference voltage terminal vdd and a second reference voltage terminal vss, and a connection point between the first transistor and the second transistor is configured to output a first level conversion circuit output signal;

[0112] Among them, the first-stage first level conversion circuit is configured to be controlled by an oscillation control signal or an oscillation signal, and the first level conversion circuits of other stages are respectively configured to be controlled by the output signal of the first level conversion circuit of the previous stage, so that one of the first transistor and the second transistor is disconnected during the conduction period of the other.

[0113] In the embodiment of the present application, by determining the oscillation control signal according to the second reference level (which may be 0V), low-level excitation oscillation can be achieved, energy consumption can be reduced, and stability can be improved.

[0114] The twentieth NMOS transistor M20 may also be other transistors. For example, the other transistors may include at least one of BJT, SCR, GTO, IGBT, MCT and SIT.

[0115] In an embodiment of the present application, a plurality of first level conversion circuits may include a first-stage first level conversion circuit, a second-stage first level conversion circuit, ..., a last-stage first level conversion circuit according to the signal transmission direction. The number of first level conversion circuits may be set according to actual needs to obtain a desired oscillation frequency. The output signal of the first level conversion circuit of the last-stage first level conversion circuit may be used as an oscillation signal. As a specific example, the number of first level conversion circuits may be an odd number, such as 5.

[0116] In some possible implementations, the first transistor and the second transistor may be a single transistor; or multiple transistors may be connected in series and / or in parallel to form a power transistor combination circuit including a control terminal, a first terminal, and a second terminal. The working principle of the power transistor combination circuit is that under the control of a control signal input to the control terminal, the path between the first terminal and the second terminal is turned on or off to connect or block the signal transmission between the first terminal and the second terminal.

[0117] Exemplarily, the first transistor may include a PMOS transistor; the second transistor may include an NMOS transistor. The source of the first transistor is configured to input a signal determined according to a first reference level, and the source of the second transistor is configured to input a signal determined according to a second reference level; the drain of the first transistor is connected to the drain of the second transistor and is configured to output a first level conversion circuit output signal; the first reference level is provided by the first reference voltage terminal vdd, and the second reference level is provided by the second reference voltage terminal vss.

[0118] Among them, the gate of the first transistor and the gate of the second transistor of the first-stage first-level conversion circuit are respectively configured to input an oscillation control signal or an oscillation signal, and the gate of the first transistor and the gate of the second transistor of the other-stage first-level conversion circuit are respectively configured to input the output signal of the previous-stage first-level conversion circuit.

[0119] As a specific example, the cascaded odd-numbered first level conversion circuits include a first-stage first level conversion circuit, a second-stage first level conversion circuit, a third-stage first level conversion circuit, a fourth-stage first level conversion circuit, and a fifth-stage first level conversion circuit;

[0120] The first-stage first level conversion circuit includes a twenty-first PMOS transistor M21 and a twenty-second NMOS transistor M22, the gate of the twenty-first PMOS transistor M21 is connected to the gate of the twenty-second NMOS transistor M22 and is configured to input an oscillation control signal (respectively connected to the drain of the twentieth NMOS transistor M20) or an oscillation signal (respectively connected to the drain of the twenty-ninth PMOS transistor M29 and the drain of the thirtieth NMOS transistor M30), the source of the twenty-first PMOS transistor M21 is connected to the first reference voltage terminal vdd, and the source of the twenty-second NMOS transistor M22 is connected to the second reference voltage terminal vss; the drain of the twenty-first PMOS transistor M21 is connected to the drain of the twenty-second NMOS transistor M22 and is configured to output the output signal of the first-stage first level conversion circuit; the connection between the source of the twenty-first PMOS transistor M21 and the first reference voltage terminal vdd and / or the connection between the source of the twenty-second NMOS transistor M22 and the second reference voltage terminal vss may be a direct connection or an indirect connection established through other components;

[0121] The second-stage first level conversion circuit includes a twenty-third PMOS transistor M23 and a twenty-fourth NMOS transistor M24, the gate of the twenty-third PMOS transistor M23 is connected to the gate of the twenty-fourth NMOS transistor M24 and is configured to input the output signal of the first-stage first level conversion circuit (respectively connected to the drain of the twenty-first PMOS transistor M21 and the drain of the twenty-second NMOS transistor M22), the source of the twenty-third PMOS transistor M23 is connected to the first reference voltage terminal vdd, and the source of the twenty-fourth NMOS transistor M24 is connected to the second reference voltage terminal vss; the drain of the twenty-third PMOS transistor M23 is connected to the drain of the twenty-fourth NMOS transistor M24 and is configured to output the output signal of the second-stage first level conversion circuit; the connection between the source of the twenty-third PMOS transistor M23 and the first reference voltage terminal vdd and / or the connection between the source of the twenty-fourth NMOS transistor M24 and the second reference voltage terminal vss may be a direct connection or an indirect connection established through other components;

[0122] The third-stage first level conversion circuit includes a twenty-fifth PMOS transistor M25 and a twenty-sixth NMOS transistor M26, the gate of the twenty-fifth PMOS transistor M25 is connected to the gate of the twenty-sixth NMOS transistor M26 and is configured to input the output signal of the second-stage first level conversion circuit (respectively connected to the drain of the twenty-third PMOS transistor M23 and the drain of the twenty-fourth NMOS transistor M24), the source of the twenty-fifth PMOS transistor M25 is connected to the first reference voltage terminal vdd, and the source of the twenty-sixth NMOS transistor M26 is connected to the second reference voltage terminal vss; the drain of the twenty-fifth PMOS transistor M25 is connected to the drain of the twenty-sixth NMOS transistor M26 and is configured to output the output signal of the third-stage first level conversion circuit; the connection between the source of the twenty-fifth PMOS transistor M25 and the first reference voltage terminal vdd and / or the connection between the source of the twenty-sixth NMOS transistor M26 and the second reference voltage terminal vss may be a direct connection or an indirect connection established through other components;

[0123] The fourth-stage first level conversion circuit includes a twenty-seventh PMOS transistor M27 and a twenty-eighth NMOS transistor M28, the gate of the twenty-seventh PMOS transistor M27 is connected to the gate of the twenty-eighth NMOS transistor M28 and is configured to input the output signal of the third-stage first level conversion circuit (respectively connected to the drain of the twenty-fifth PMOS transistor M25 and the drain of the twenty-sixth NMOS transistor M26), the source of the twenty-seventh PMOS transistor M27 is connected to the first reference voltage terminal vdd, and the source of the twenty-eighth NMOS transistor M28 is connected to the second reference voltage terminal vss; the drain of the twenty-seventh PMOS transistor M27 is connected to the drain of the twenty-eighth NMOS transistor M28 and is configured to output the output signal of the fourth-stage first level conversion circuit; the connection between the source of the twenty-seventh PMOS transistor M27 and the first reference voltage terminal vdd and / or the connection between the source of the twenty-eighth NMOS transistor M28 and the second reference voltage terminal vss may be a direct connection or an indirect connection established through other components;

[0124] The fifth-stage first level conversion circuit includes a twenty-ninth PMOS transistor M29 and a thirtieth NMOS transistor M30, the gate of the twenty-ninth PMOS transistor M29 is connected to the gate of the thirtieth NMOS transistor M30 and is configured to input the output signal of the fourth-stage first level conversion circuit (respectively connected to the drain of the twenty-seventh PMOS transistor M27 and the drain of the twenty-eighth NMOS transistor M28), the source of the twenty-ninth PMOS transistor M29 is connected to the first reference voltage terminal vdd, and the source of the thirtieth NMOS transistor M30 is connected to the second reference voltage terminal vss; the drain of the twenty-ninth PMOS transistor M29 is connected to the drain of the thirtieth NMOS transistor M30 and is configured to output an oscillation signal; the connection between the source of the twenty-ninth PMOS transistor M29 and the first reference voltage terminal vdd and / or the connection between the source of the thirtieth NMOS transistor M30 and the second reference voltage terminal vss can be a direct connection or an indirect connection established through other components.

[0125] In an alternative embodiment, if Figure 5 As shown, the clock signal output module 22 includes a thirty-first PMOS transistor M31, a thirty-second NMOS transistor M32, a thirty-third PMOS transistor M33 and a thirty-fourth NMOS transistor M34;

[0126] A source of the thirty-first PMOS transistor M31 is connected to the first reference voltage terminal vdd, a source of the thirty-second NMOS transistor M32 is connected to the second reference voltage terminal vss, a gate of the thirty-first PMOS transistor M31 and a gate of the thirty-second NMOS transistor M32 are respectively configured to input an oscillation signal, and a drain of the thirty-first PMOS transistor M31 and a drain of the thirty-second NMOS transistor M32 are connected and configured to output a first clock signal phia;

[0127] The source of the thirty-third PMOS transistor M33 is connected to the first reference voltage terminal vdd, the source of the thirty-fourth NMOS transistor M34 is connected to the second reference voltage terminal vss, the gate of the thirty-third PMOS transistor M33 and the gate of the thirty-fourth NMOS transistor M34 are respectively configured to input the first clock signal phia, and the drain of the thirty-third PMOS transistor M33 is connected to the drain of the thirty-fourth NMOS transistor M34 and is configured to output the second clock signal phib.

[0128] And / or, the clock generation module CG further includes a current mirror circuit;

[0129] The current mirror circuit includes a thirty-fifth NMOS transistor M35, a thirty-sixth NMOS transistor M36, a thirty-seventh NMOS transistor M37, a thirty-eighth NMOS transistor M38, a thirty-ninth NMOS transistor M39, a forty-second NMOS transistor M40, a forty-first NMOS transistor M41, a forty-second PMOS transistor M42, a forty-third PMOS transistor M43, a forty-fourth PMOS transistor M44, a forty-fifth PMOS transistor M45, a forty-sixth PMOS transistor M46, and a forty-seventh PMOS transistor M47;

[0130] The drain of the thirty-fifth NMOS transistor M35 is configured to input a reference current signal and is respectively connected to the gate of the thirty-fifth NMOS transistor M35, the gate of the thirty-sixth NMOS transistor M36, the gate of the thirty-seventh NMOS transistor M37, the gate of the thirty-eighth NMOS transistor M38, the gate of the thirty-ninth NMOS transistor M39, the gate of the fortieth NMOS transistor M40, and the gate of the forty-first NMOS transistor M41;

[0131] The source of the thirty-fifth NMOS transistor M35, the source of the thirty-sixth NMOS transistor M36, the source of the thirty-seventh NMOS transistor M37, the source of the thirty-eighth NMOS transistor M38, the source of the thirty-ninth NMOS transistor M39, the source of the fortieth NMOS transistor M40, and the source of the forty-first NMOS transistor M41 are respectively connected to the second reference voltage terminal vss, the drain of the thirty-seventh NMOS transistor M37 is connected to the source of the twenty-second NMOS transistor M22, the drain of the thirty-eighth NMOS transistor M38 is connected to the source of the twenty-fourth NMOS transistor M24, the drain of the thirty-ninth NMOS transistor M39 is connected to the source of the twenty-sixth NMOS transistor M26, the drain of the fortieth NMOS transistor M40 is connected to the source of the twenty-eighth NMOS transistor M28, and the drain of the forty-first NMOS transistor M41 is connected to the source of the thirtieth NMOS transistor M30;

[0132] The drain of the thirty-sixth NMOS transistor M36 is respectively connected to the drain of the forty-second PMOS transistor M42, the gate of the forty-second PMOS transistor M42, the gate of the forty-third PMOS transistor M43, the gate of the forty-fourth PMOS transistor M44, the gate of the forty-fifth PMOS transistor M45, the gate of the forty-sixth PMOS transistor M46, and the gate of the forty-seventh PMOS transistor M47;

[0133] The source M42 of the forty-second PMOS transistor, the source of the forty-third PMOS transistor M43, the source of the forty-fourth PMOS transistor M44, the source of the forty-fifth PMOS transistor M45, the source of the forty-sixth PMOS transistor M46 and the source of the forty-seventh PMOS transistor M47 are respectively connected to the first reference voltage terminal vdd, the drain of the forty-third PMOS transistor M43 is connected to the source of the twenty-first PMOS transistor M21, the drain of the forty-fourth PMOS transistor M44 is connected to the source of the twenty-third PMOS transistor M23, the drain of the forty-fifth PMOS transistor M45 is connected to the source of the twenty-fifth PMOS transistor M25, the drain of the forty-sixth PMOS transistor M46 is connected to the source of the twenty-seventh PMOS transistor M27, and the drain of the forty-seventh PMOS transistor M47 is connected to the source of the twenty-ninth PMOS transistor M29.

[0134] In the embodiment of the present application, the thirty-first PMOS transistor M31 and the thirty-second NMOS transistor M32 can constitute a second level conversion circuit. The thirty-third PMOS transistor M33 and the thirty-fourth NMOS transistor M34 can constitute a third level conversion circuit. The thirty-first PMOS transistor M31 and the thirty-third PMOS transistor M33 can also use the above-mentioned first transistor; the thirty-second NMOS transistor M32 and the thirty-fourth NMOS transistor M34 can also use the above-mentioned second transistor. The first transistor and the second transistor can refer to the above, and will not be repeated here.

[0135] In this way, under the control of the oscillation signal, one of the thirty-first PMOS transistor M31 and the thirty-second NMOS transistor M32 is disconnected during the other conduction period to generate a first clock signal; and under the control of the first clock signal, one of the thirty-third PMOS transistor M33 and the thirty-fourth NMOS transistor M34 is disconnected during the other conduction period to generate a second clock signal, thereby enabling the output of the two-phase non-overlapping first clock signal and the second clock signal, and achieving the determination of their levels according to the first reference level and the second reference level, thereby achieving output localization and improving stability.

[0136] In the embodiment of the present application, the current mirror circuit is configured to inject current into the oscillation module 21 according to the input reference current signal osc_bias. The reference current signal osc_bias may be a zero-temperature current that is not affected by temperature, etc., to improve stability.

[0137] Thus, the embodiment of the present application can isolate the oscillator module 21 from the first reference voltage terminal vdd and the second reference voltage terminal vss respectively through the current mirror circuit, thereby improving the stability of the output clock signal. In addition, the power consumption is controlled through the MOS tube current mirror structure, and the power consumption can be reduced and the stability can be ensured.

[0138] Those skilled in the art should understand that the number of the thirty-seventh NMOS transistor M37, the thirty-eighth NMOS transistor M38, the thirty-ninth NMOS transistor M39, the fortieth NMOS transistor M40 and the forty-first NMOS transistor M41 and the number of the forty-third PMOS transistor M43, the forty-fourth PMOS transistor M44, the forty-fifth PMOS transistor M45, the forty-sixth PMOS transistor M46 and the forty-seventh PMOS transistor M47 can be set according to actual needs to correspond to (for example, be equal to) the number of the first level conversion circuits.

[0139] In an alternative embodiment, if Figure 3 As shown, the operational amplifier comprises a telescopic cascode amplifier;

[0140] And / or, the operational amplifier includes a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9 and a Miller compensation capacitor Cc;

[0141] The gate of the first NMOS transistor M1 is configured as the non-inverting input terminal of the operational amplifier, the gate of the second NMOS transistor M2 is configured as the inverting input terminal of the operational amplifier, and the drain of the fifth NMOS transistor M5 is configured as the output terminal of the operational amplifier;

[0142] The drain of the first NMOS transistor M1 is connected to the source of the fourth NMOS transistor M4, the drain of the second NMOS transistor M2 is connected to the source of the fifth NMOS transistor M5; the drain of the fourth NMOS transistor M4 is respectively connected to the drain of the sixth PMOS transistor M6, the gate of the sixth PMOS transistor M6 and the gate of the seventh PMOS transistor M7, the drain of the fifth NMOS transistor M5 is connected to the drain of the seventh PMOS transistor M7; the source of the sixth PMOS transistor M6 is respectively connected to the drain of the eighth PMOS transistor M8 , the gate of the eighth PMOS transistor M8 is connected to the gate of the ninth PMOS transistor M9, and the source of the seventh PMOS transistor M7 is connected to the drain of the ninth PMOS transistor M9; the source of the eighth PMOS transistor M8 and the source of the ninth PMOS transistor M9 are respectively configured to receive the operational amplifier power supply signal vddea; the source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are respectively connected to the drain of the third NMOS transistor M3, and the source of the third NMOS transistor M3 is connected to the circuit ground terminal vssldo;

[0143] The gate of the third NMOS transistor M3 is configured to receive the first low bias signal vbn1, and the gate of the fourth NMOS transistor M4 and the gate of the fifth NMOS transistor M5 are respectively configured to receive the second low bias signal vbn2;

[0144] The first end of the Miller compensation capacitor Cc is respectively connected to the drain of the fifth NMOS transistor M5, the drain of the seventh PMOS transistor M7 and the control end of the transmission transistor MP, and the second end of the Miller compensation capacitor Cc is connected to the voltage stabilization output end.

[0145] In the embodiment of the present application, an operational amplifier is formed by an error amplifier EA, and the first PMOS transistor M1 and the second PMOS transistor M2 are input pairs of the error amplifier EA. The gate of the first PMOS transistor M1 can be configured to receive a reference voltage signal vref. The gate of the second PMOS transistor M2 can be connected to the connection node between the first resistor R1 and the second resistor R2 to obtain a feedback voltage signal. The error amplifier EA adopts a sleeve-type common source and common gate amplifier, which can improve the loop gain and thus ensure the accuracy of the output. The transmission transistor MP is an adjustment power tube, which is the second-stage amplifier of the LDO as a common source, and Cc is a Miller compensation capacitor. Because the main pole of the LDO is at the gate end of the transmission transistor MP, the capacitance of the load capacitance CL of the output signal vldo can be relatively small, and no large external capacitor is required.

[0146] Miller compensation capacitor Cc may be a single capacitor, or a plurality of capacitors connected in series and / or in parallel, or may include a passive capacitor network or an active capacitor network of resistors, capacitors, inductors, etc. Miller compensation capacitor Cc can improve the stability of output signal vldo at the voltage regulated output terminal.

[0147] In the embodiment of the present application, the first low voltage bias signal vbn1 and the second low voltage bias signal vbn2 can be provided by external bias circuits, and these bias circuits can be controlled by logic control circuits. These are not the inventive points of the invention, and the bias circuits and logic control circuits are both prior art, and the present invention will not introduce them in detail.

[0148] In an optional implementation, the isolation transistor MC is an NMOS transistor, whose gate, source and drain respectively correspond to the control terminal, the first terminal and the second terminal of the isolation transistor MC; the transfer transistor MP is a PMOS transistor, whose gate, source and drain respectively correspond to the control terminal, the first terminal and the second terminal of the transfer transistor MP;

[0149] And / or, the low pass filter LPF comprises a filter resistor R and a filter capacitor C;

[0150] The first end of the filter resistor R is connected to the output end of the charge pump CP, and is used to receive the first gate voltage signal; the second end of the filter resistor R is respectively connected to the first end of the filter capacitor C and the control end of the isolation transistor MC, and is used to output the second gate voltage signal; the second end of the filter capacitor C is connected to the circuit ground end vssldo;

[0151] And / or, the feedback circuit FB includes a first resistor R1 and a second resistor R2;

[0152] The non-inverting input terminal of the operational amplifier is respectively connected to the second end of the first resistor R1 and the first end of the second resistor R2, the second end of the transmission transistor MP is respectively connected to the first end of the first resistor R1 and the voltage stabilization output terminal of the low voltage difference linear voltage regulator circuit; the second end of the second resistor R2 is connected to the circuit ground terminal vssldo.

[0153] In the embodiment of the present application, a cascode structure is formed by an isolation transistor MC of an NMOS transistor and a transfer transistor MP of a PMOS transistor. The isolation transistor MC is an NMOS cascode device, and the shielding characteristics of the NMOS cascode are used to isolate the power supply noise ripple and improve the PSR performance of the low voltage difference linear voltage regulator circuit.

[0154] The first resistor R1 and the second resistor R2 may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc. Moreover, the filter resistor R and the filter capacitor C in the low-pass filter LPF are not limited to a single resistor or capacitor, but may be a modified structure using series and / or parallel connections.

[0155] An embodiment of the present application also provides a radio frequency module, which includes a low voltage difference linear voltage regulator circuit as described in the above embodiment, thereby improving the PSR capability of the module at medium and high frequencies.

[0156] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: The low voltage difference linear voltage stabilization circuit comprises a charge pump, an isolation transistor, a transmission transistor, a feedback circuit and an operational amplifier; The charge pump is configured to receive an input power supply signal and boost the input power supply signal to generate a first gate terminal voltage signal; the first gate terminal voltage signal is used to provide to the control terminal of the isolation transistor; The second end of the isolation transistor is configured to receive the input power signal, and the first end of the isolation transistor is connected to the first end of the transmission transistor and is configured to provide an operational amplifier power signal; The inverting input terminal of the operational amplifier is configured to receive a reference voltage signal, the non-inverting input terminal of the operational amplifier is connected to the output terminal of the feedback circuit, the output terminal of the operational amplifier is connected to the control terminal of the transmission transistor, the second terminal of the transmission transistor is respectively connected to the input terminal of the feedback circuit and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit, and the voltage stabilization output terminal is used to provide a voltage stabilization output signal; wherein the power supply terminal of the operational amplifier is configured to receive the operational amplifier power supply signal; Wherein, at least a common source and common gate structure is formed based on the isolation transistor and the transmission transistor, so as to isolate the power supply noise in the input power supply signal from being transmitted to the transmission transistor and the power supply terminal of the operational amplifier.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The low voltage difference linear voltage stabilization circuit also includes a low pass filter; The low-pass filter is configured to low-pass filter the first gate terminal voltage signal to generate and output a second gate terminal voltage signal to the control terminal of the isolation transistor.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The charge pump adopts a Dickson charge pump having at least two-stage charge and discharge units; Wherein, the charging and discharging unit includes an anti-reverse connection circuit using a MOS transistor.

4. The low voltage difference linear voltage regulator circuit according to claim 3, characterized in that: The charge pump comprises a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a first boost capacitor, a second boost capacitor and an output capacitor; The gate and source of the tenth PMOS transistor are connected and configured to receive an input power supply signal, the drain of the tenth PMOS transistor is respectively connected to the first end of the first boost capacitor, the gate of the eleventh PMOS transistor and the source of the eleventh PMOS transistor, the drain of the eleventh PMOS transistor is respectively connected to the first end of the second boost capacitor, the gate of the twelfth PMOS transistor and the source of the twelfth PMOS transistor, and the drain of the twelfth PMOS transistor is connected to the first end of the output capacitor and is configured to output the first gate terminal voltage signal; The second end of the first boost capacitor is configured to receive a first clock signal; the second end of the second boost capacitor is configured to receive a second clock signal; the second end of the output capacitor is connected to the circuit ground; The first clock signal and the second clock signal are clock signals with non-overlapping phases.

5. The low voltage difference linear voltage regulator circuit according to claim 4, characterized in that: The low voltage difference linear voltage stabilization circuit also includes a clock generation module; The clock generation module is configured to generate oscillation under the stimulation of an enable start signal to generate and output a first clock signal and a second clock signal with two non-overlapping phases; the first clock signal and the second clock signal are respectively used to control the charge pump to generate a first gate voltage signal.

6. The low voltage difference linear voltage regulator circuit according to claim 5, characterized in that: The clock generation module includes an oscillation module and a clock signal output module; The oscillation module is configured to generate oscillation under the stimulation of the enable start signal to generate and output an oscillation signal; The clock signal output module is configured to generate and output a first clock signal and a second clock signal with two non-overlapping phases under the control of the oscillation signal; the first clock signal includes a first high level and a first low level, the second clock signal includes a second high level and a second low level, the first high level and the second high level are respectively determined according to a first reference level, and the first low level and the second low level are respectively determined according to a second reference level.

7. The low voltage difference linear voltage regulator circuit according to claim 6, characterized in that: The oscillation module comprises a twentieth NMOS transistor and an odd number of first level conversion circuits connected in cascade; The gate of the twentieth NMOS transistor is configured to input an enable start signal, the source of the twentieth NMOS transistor is connected to the second reference voltage terminal, and the drain of the twentieth NMOS transistor is configured to output an oscillation control signal; The first level conversion circuit includes a first transistor and a second transistor connected in series between a first reference voltage terminal and a second reference voltage terminal, and a connection point between the first transistor and the second transistor is configured to output a first level conversion circuit output signal; Among them, the first-stage first level conversion circuit is configured to be controlled by the oscillation control signal or the oscillation signal, and the first level conversion circuits of other stages are respectively configured to be controlled by the output signal of the first level conversion circuit of the previous stage, so that one of the first transistor and the second transistor is disconnected during the conduction period of the other.

8. The low voltage difference linear voltage regulator circuit according to claim 7, characterized in that: The odd number of first level conversion circuits in cascade connection include a first-stage first level conversion circuit, a second-stage first level conversion circuit, a third-stage first level conversion circuit, a fourth-stage first level conversion circuit and a fifth-stage first level conversion circuit; The first-stage first level conversion circuit includes a twenty-first PMOS transistor and a twenty-second NMOS transistor, the gate of the twenty-first PMOS transistor is connected to the gate of the twenty-second NMOS transistor and is configured to input an oscillation control signal or an oscillation signal, the source of the twenty-first PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-second NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-first PMOS transistor is connected to the drain of the twenty-second NMOS transistor and is configured to output the first-stage first level conversion circuit output signal; The second-stage first level conversion circuit includes a twenty-third PMOS transistor and a twenty-fourth NMOS transistor, the gate of the twenty-third PMOS transistor is connected to the gate of the twenty-fourth NMOS transistor and is configured to input the output signal of the first-stage first level conversion circuit, the source of the twenty-third PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-fourth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-third PMOS transistor is connected to the drain of the twenty-fourth NMOS transistor and is configured to output the output signal of the second-stage first level conversion circuit; The third-stage first level conversion circuit includes a twenty-fifth PMOS transistor and a twenty-sixth NMOS transistor, the gate of the twenty-fifth PMOS transistor is connected to the gate of the twenty-sixth NMOS transistor and is configured to input the output signal of the second-stage first level conversion circuit, the source of the twenty-fifth PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-sixth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-fifth PMOS transistor is connected to the drain of the twenty-sixth NMOS transistor and is configured to output the output signal of the third-stage first level conversion circuit; The fourth-stage first level conversion circuit includes a twenty-seventh PMOS transistor and a twenty-eighth NMOS transistor, the gate of the twenty-seventh PMOS transistor is connected to the gate of the twenty-eighth NMOS transistor and is configured to input the output signal of the third-stage first level conversion circuit, the source of the twenty-seventh PMOS transistor is connected to the first reference voltage terminal, and the source of the twenty-eighth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-seventh PMOS transistor is connected to the drain of the twenty-eighth NMOS transistor and is configured to output the output signal of the fourth-stage first level conversion circuit; The fifth-stage first level conversion circuit includes a twenty-ninth PMOS transistor and a thirtieth NMOS transistor, the gate of the twenty-ninth PMOS transistor is connected to the gate of the thirtieth NMOS transistor and is configured to input the output signal of the fourth-stage first level conversion circuit, the source of the twenty-ninth PMOS transistor is connected to the first reference voltage terminal, and the source of the thirtieth NMOS transistor is connected to the second reference voltage terminal; the drain of the twenty-ninth PMOS transistor is connected to the drain of the thirtieth NMOS transistor and is configured to output an oscillation signal.

9. The low voltage difference linear voltage regulator circuit according to claim 8, characterized in that: The clock signal output module includes a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor and a thirty-fourth NMOS transistor; a source of the thirty-first PMOS transistor connected to the first reference voltage terminal, a source of the thirty-second NMOS transistor connected to the second reference voltage terminal, a gate of the thirty-first PMOS transistor and a gate of the thirty-second NMOS transistor respectively configured to input the oscillation signal, and a drain of the thirty-first PMOS transistor and a drain of the thirty-second NMOS transistor connected to output the first clock signal; a source of the thirty-third PMOS transistor connected to the first reference voltage terminal, a source of the thirty-fourth NMOS transistor connected to the second reference voltage terminal, a gate of the thirty-third PMOS transistor and a gate of the thirty-fourth NMOS transistor respectively configured to input the first clock signal, and a drain of the thirty-third PMOS transistor connected to a drain of the thirty-fourth NMOS transistor and configured to output the second clock signal; And / or, the clock generation module further includes a current mirror circuit; The current mirror circuit includes a thirty-fifth NMOS transistor, a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a forty-first NMOS transistor, a forty-second PMOS transistor, a forty-third PMOS transistor, a forty-fourth PMOS transistor, a forty-fifth PMOS transistor, a forty-sixth PMOS transistor and a forty-seventh PMOS transistor; a drain of the thirty-fifth NMOS transistor configured to input a reference current signal and connected to the gate of the thirty-fifth NMOS transistor, the gate of the thirty-sixth NMOS transistor, the gate of the thirty-seventh NMOS transistor, the gate of the thirty-eighth NMOS transistor, the gate of the thirty-ninth NMOS transistor, the gate of the fortieth NMOS transistor, and the gate of the forty-first NMOS transistor, respectively; The source of the thirty-fifth NMOS transistor, the source of the thirty-sixth NMOS transistor, the source of the thirty-seventh NMOS transistor, the source of the thirty-eighth NMOS transistor, the source of the thirty-ninth NMOS transistor, the source of the fortieth NMOS transistor, and the source of the forty-first NMOS transistor are respectively connected to the second reference voltage terminal, the drain of the thirty-seventh NMOS transistor is connected to the source of the twenty-second NMOS transistor, the drain of the thirty-eighth NMOS transistor is connected to the source of the twenty-fourth NMOS transistor, the drain of the thirty-ninth NMOS transistor is connected to the source of the twenty-sixth NMOS transistor, the drain of the fortieth NMOS transistor is connected to the source of the twenty-eighth NMOS transistor, and the drain of the forty-first NMOS transistor is connected to the source of the thirtieth NMOS transistor; the drain of the thirty-sixth NMOS transistor is respectively connected to the drain of the forty-second PMOS transistor, the gate of the forty-second PMOS transistor, the gate of the forty-third PMOS transistor, the gate of the forty-fourth PMOS transistor, the gate of the forty-fifth PMOS transistor, the gate of the forty-sixth PMOS transistor, and the gate of the forty-seventh PMOS transistor; The source of the forty-second PMOS transistor, the source of the forty-third PMOS transistor, the source of the forty-fourth PMOS transistor, the source of the forty-fifth PMOS transistor, the source of the forty-sixth PMOS transistor and the source of the forty-seventh PMOS transistor are respectively connected to the first reference voltage terminal, the drain of the forty-third PMOS transistor is connected to the source of the twenty-first PMOS transistor, the drain of the forty-fourth PMOS transistor is connected to the source of the twenty-third PMOS transistor, the drain of the forty-fifth PMOS transistor is connected to the source of the twenty-fifth PMOS transistor, the drain of the forty-sixth PMOS transistor is connected to the source of the twenty-seventh PMOS transistor, and the drain of the forty-seventh PMOS transistor is connected to the source of the twenty-ninth PMOS transistor.

10. The low voltage difference linear voltage regulator circuit according to any one of claims 1 to 9, characterized in that: The operational amplifier comprises a telescopic cascode amplifier; And / or, the operational amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor and a Miller compensation capacitor; The gate of the first NMOS transistor is configured as a non-inverting input terminal of the operational amplifier, the gate of the second NMOS transistor is configured as an inverting input terminal of the operational amplifier, and the drain of the fifth NMOS transistor is configured as an output terminal of the operational amplifier; The drain of the first NMOS transistor is connected to the source of the fourth NMOS transistor, and the drain of the second NMOS transistor is connected to the source of the fifth NMOS transistor; the drain of the fourth NMOS transistor is respectively connected to the drain of the sixth PMOS transistor, the gate of the sixth PMOS transistor and the gate of the seventh PMOS transistor, and the drain of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor; the source of the sixth PMOS transistor is respectively connected to the drain of the eighth PMOS transistor, the gate of the eighth PMOS transistor and the gate of the ninth PMOS transistor, and the source of the seventh PMOS transistor is connected to the drain of the ninth PMOS transistor; the source of the eighth PMOS transistor and the source of the ninth PMOS transistor are respectively configured to receive the operational amplifier power supply signal; the source of the first NMOS transistor and the source of the second NMOS transistor are respectively connected to the drain of the third NMOS transistor, and the source of the third NMOS transistor is connected to the circuit ground; The gate of the third NMOS transistor is configured to receive a first low bias signal, and the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor are respectively configured to receive a second low bias signal; The first end of the Miller compensation capacitor is connected to the drain of the fifth NMOS transistor, the drain of the seventh PMOS transistor and the control end of the transmission transistor respectively, and the second end of the Miller compensation capacitor is connected to the voltage stabilization output end.

11. The low voltage difference linear voltage regulator circuit according to claim 10, characterized in that: The isolation transistor is an NMOS transistor, whose gate, source and drain correspond to the control terminal, the first terminal and the second terminal of the isolation transistor respectively; the transmission transistor is a PMOS transistor, whose gate, source and drain correspond to the control terminal, the first terminal and the second terminal of the transmission transistor respectively; And / or, the low-pass filter includes a filter resistor and a filter capacitor; The first end of the filter resistor is connected to the output end of the charge pump for receiving the first gate voltage signal; the second end of the filter resistor is respectively connected to the first end of the filter capacitor and the control end of the isolation transistor for outputting the second gate voltage signal; the second end of the filter capacitor is connected to the circuit ground; And / or, the feedback circuit includes a first resistor and a second resistor; The non-inverting input terminal of the operational amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor, the second end of the transmission transistor is respectively connected to the first end of the first resistor and the voltage stabilization output terminal of the low voltage difference linear voltage stabilization circuit; the second end of the second resistor is connected to the circuit ground.

12. A radio frequency module, characterized in that: The radio frequency module includes a low voltage drop linear voltage regulator circuit as described in any one of claims 1-11.

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