Data operation method, electronic equipment and chip system

Abstract

The embodiment of the invention discloses a data operation method, electronic equipment and a chip system.The method comprises the steps that a data operation instruction from a memory controller DDRC is received, and the data operation instruction comprises a target data address; determining a target memory space from a common data memory space and a near memory calculation PIM data memory space of the memory based on the target data address, wherein the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; and in response to the data operation instruction, executing data operation on the target memory space based on the target data address. Visibly, the memory is divided into the common data memory space and the PIM data memory space which are mutually independent, so that the operation instruction of the common data and the operation instruction of the PIM data can be accurately distinguished, the corresponding operation instruction is accurately executed in the memory space, and the validity of data operation is improved.

Description

Technical Field

[0001] The present application relates to the field of terminal technology, and in particular to a data operation method, an electronic device and a chip system. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, large language models are increasingly being used on the end side (such as mobile phones, tablets, laptops, PDAs, wearable devices, etc.). In actual applications, it is found that the deployment of large language models on the end side poses a great challenge to memory bandwidth. Taking dynamic random access memory (DRAM) as an example, since all the weights of the large model need to be read from DRAM each time the large language model generates a token (the basic unit for model processing and understanding text), it is difficult to achieve the ideal inference speed even if the full bandwidth of DRAM is used.

[0003] In order to improve the AI ​​reasoning bandwidth, DRAM-based near-memory computing (processor in memory, PIM) is an effective technical solution. Compared with the method that requires the processor to read the large model weight data from the memory and complete the data operation, PIM technology refers to completing the data operation of the large model weight directly in the processing unit (PU) of the DRAM memory. However, since the current system on chip (SoC) memory controller (double data rate controller, DDRC) does not support PIM data operation instructions (such as read instructions, write instructions), the PIM function needs to reuse standard memory read and write instructions. When DRAM is used for PIM data operations, it also needs to process the system's ordinary read and write instructions. However, due to the disassembly and re-arrangement of read and write instructions by DDRC, conflicts between ordinary instructions and PIM instructions will occur, resulting in the failure of data read and write operations.

[0004] It can be seen that how to improve the effectiveness of data operations in PIM solutions is an urgent problem to be solved. Summary of the invention

[0005] The embodiments of the present application provide a data operation method, an electronic device, and a chip system, which can divide the memory into independent common data memory space and PIM data memory space, so as to accurately distinguish the common operation instructions from the PIM operation instructions according to the memory space corresponding to the target data address, and accurately execute the corresponding operation instructions in the memory space, thereby improving the effectiveness of data operations in the PIM solution.

[0006] In the first aspect, an embodiment of the present application provides a data operation method, the method comprising: receiving a data operation instruction from a memory controller DDRC, the data operation instruction comprising a target data address, the data operation instruction being sent by the DDRC based on the target data address; determining the target memory space from the ordinary data memory space of the memory and the near memory PIM data memory space based on the target data address, the ordinary data memory space and the PIM data memory space being different memory spaces obtained by dividing the memory according to a preset division unit; responding to the data operation instruction, performing data operation on the target memory space based on the target data address. It can be seen that in this technical solution, by dividing the memory into an ordinary data memory space and a PIM data memory space that are independent of each other, the operation instructions for ordinary data and the operation instructions for PIM data can be accurately distinguished, and the corresponding operation instructions can be accurately executed in the memory space, which can improve the effectiveness of data operation in the PIM solution.

[0007] In combination with the first aspect, in a possible manner, determining the target memory space of the memory based on the target data address includes: obtaining memory space configuration information, the memory space configuration information including address information of the ordinary data memory space and address information of the PIM data memory space; and determining the ordinary data memory space or the PIM data memory space in the memory as the target memory space based on the memory space configuration information and the target data address. It can be seen that the target memory space corresponding to the data operation instruction can be accurately identified by using the memory space configuration information, so that the data operation instruction can be accurately and effectively executed in the target memory space.

[0008] In combination with the first aspect, in a possible manner, based on the memory space configuration information and the target data address, determining the ordinary data memory space or the PIM data memory space in the memory as the target memory space includes: when the target data address matches the address information of the PIM data memory space, that is, the target data address belongs to the address range indicated by the address information of the PIM data memory space, determining the PIM data memory space in the memory as the target memory space; when the target data address matches the address information of the ordinary data memory space, that is, the target data address belongs to the address range indicated by the address information of the ordinary data memory space, determining the ordinary data memory space in the memory as the target memory space. It can be seen that when determining the target memory space, by matching the target data address with the address information of the ordinary data memory space and the address information of the PIM data memory space included in the memory space configuration information, the target memory space corresponding to the current data operation instruction can be accurately identified.

[0009] In combination with the first aspect, in a possible manner, the method further includes: receiving a memory space configuration instruction sent by a processor, the memory space configuration instruction including memory space configuration information; and saving the memory space configuration information in response to the memory space configuration instruction. It can be seen that the memory can accurately divide the memory into independent common data memory space and PIM data memory space according to the memory space configuration information sent by the processor, which helps to isolate different types of data operation instructions from each other and prevent them from interfering with each other.

[0010] In combination with the first aspect, in a possible manner, the preset partitioning unit includes a rank, and the memory is partitioned according to the granularity of the rank. Assuming that the memory of the electronic device is dual-rank, the first rank in the dual rank is divided into a common data memory space, and the second rank is divided into a PIM data memory space. At this time, all banks in all memory particles included in the first rank are used as common data memory spaces, and all banks in all memory particles included in the second rank are used as PIM data memory spaces. In this case, performing data operations on the target memory space based on the target data address includes: When the target memory space is a normal data memory space, for each memory particle included in the first rank, the target bank is determined from each memory particle according to the target data address, and data operations are performed on the target bank according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a normal data operation instruction, and it is only necessary to execute the data operation instruction on the specific bank (such as the target bank mentioned above) indicated by the target data address in the relevant memory particles (that is, each memory particle included in the first rank) to complete operations such as reading or writing normal data.

[0011] When the target memory space is the PIM data memory space, for each memory particle included in the second rank, data operations are performed on all banks of each memory particle according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a PIM data operation instruction, and the data operation instruction needs to be executed on all banks of the relevant memory particles (that is, each memory particle included in the second rank) to complete operations such as reading or writing PIM data.

[0012] Among them, the first rank is different from the second rank. It can be seen that by dividing the memory into ordinary data memory space and PIM data memory space according to rank, the physical isolation between the ordinary data memory space and the PIM data memory space can be guaranteed, and the data operation instructions are executed independently in the corresponding rank, avoiding conflicts between different types of data operation instructions, thereby avoiding data read / write failures, and improving the effectiveness of data operations in the PIM solution.

[0013] In combination with the first aspect, in a possible manner, the preset partitioning unit includes a bank, and the memory is partitioned according to the granularity of the physical bank. Assuming that the memory of the electronic device is dual-rank, for any rank, recorded as the third rank, the multiple first banks of each memory particle included in the third rank are divided into ordinary data memory space, and the multiple second banks are divided into PIM data memory space. For example, each memory particle includes 16 banks, specifically bank 0-bank 15, the first bank can refer to bank 0-bank 7 in the memory particle, and the second bank can refer to bank 8-bank15 in the memory particle, that is, a part of the bank of each memory particle included in the third rank (such as the multiple first banks mentioned above) is divided into ordinary data memory space, and another part of the bank (such as the multiple second banks mentioned above) is divided into PIM data memory space. In this case, performing data operations on the target memory space based on the target data address includes: In the case where the target memory space is the normal data memory space, for each memory particle included in the third rank, the target bank corresponding to the target data address is determined from the multiple first banks allocated to the normal data memory space, and data operations are performed on the target bank according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a normal data operation instruction, and it is only necessary to execute the data operation instruction on the specific bank (such as the target bank mentioned above) indicated by the target data address in the bank allocated to the normal data memory space by the relevant memory particles (such as each memory particle included in the third rank) to complete operations such as reading or writing normal data.

[0014] When the target memory space is the PIM data memory space, for each memory particle included in the third rank, all banks (i.e., the second bank mentioned above) allocated to the PIM data memory space are determined, and data operations are performed on all second banks according to the target data address. It can be seen that at this time, the data operation instruction is recognized by the memory as a PIM data operation instruction, and the data operation instruction needs to be executed on all banks (such as the second bank mentioned above) allocated to the PIM data memory space by the relevant memory particles (such as each memory particle included in the third rank) to complete operations such as reading or writing PIM data.

[0015] Among them, the first bank is different from the second bank. It can be seen that by dividing the memory into the common data memory space and the PIM data memory space according to the bank, the physical isolation between the common data memory space and the PIM data memory space can be guaranteed, and the data operation instructions are independently executed in the corresponding bank, avoiding the mutual conflict of different types of data operation instructions, thereby avoiding the failure of data reading / writing, and improving the effectiveness of data operation in the PIM solution.

[0016] In combination with the first aspect, in one possible manner, performing a data operation on a target memory space based on a target data address includes: When the target memory space is the PIM data memory space, the working mode of the PIM data memory space is obtained.

[0017] When the working mode of the PIM data memory space is the PIM mode, a data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address.

[0018] When the working mode of the PIM data memory space is not the PIM mode, a data operation corresponding to the common data operation instruction is performed on the PIM data memory space based on the target data address.

[0019] It can be seen that when the working mode of the PIM data memory space is the PIM mode, the PIM data memory space can execute PIM data operation instructions to implement the read / write operation of the PIM data. When the working mode of the PIM data memory space is not the PIM mode (for example, the normal mode), the PIM data memory space can execute the normal data operation instructions to implement the read / write operation of the normal data. By identifying the working mode of the PIM data memory space, the PIM data memory space can be reused, thereby improving the utilization of memory resources.

[0020] In combination with the first aspect, in one possible manner, the method further includes: Obtain the PIM mode configuration instruction issued by the processor for the PIM data memory space. In response to the PIM mode configuration instruction, set the working mode of the PIM data memory space to the PIM mode. For example, the processor can send the PIM mode configuration instruction to the memory after the electronic device is powered on, or when the PIM data memory space and the ordinary data memory space are configured during the operation of the electronic device. It can be seen that the memory can flexibly set the working mode of the PIM data memory space according to the configuration of the processor, which helps to improve the utilization of memory resources.

[0021] In combination with the first aspect, in one possible manner, the method further includes: In the case where the data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address, a common mode configuration instruction issued by the processor for the PIM data memory space can be obtained. In response to the common mode configuration instruction, the working mode of the PIM data memory space is set to the common mode. It can be seen that after the PIM data memory space performs the operation of the PIM data, the memory can configure the working mode of the PIM data memory space to the common mode according to the configuration of the processor, so as to realize the reuse of the PIM data memory space, which is helpful to improve the utilization rate of memory resources.

[0022] In a second aspect, an embodiment of the present application provides another data operation method, the method comprising: Generate a data operation instruction based on a target data address; send a data operation instruction to a memory controller DDRC, the data operation instruction is used to trigger the DDRC to send the data operation instruction to a target memory particle of the memory based on the target data address; wherein the data operation instruction is used to trigger the target memory particle to determine a target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address, the target memory space is a common data memory space or a near memory computing PIM data memory space, and the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit.

[0023] It can be seen that in this technical solution, by dividing the memory into independent ordinary data memory space and PIM data memory space, when the processor sends data operation instructions to the memory, the memory can accurately distinguish the operation instructions for ordinary data from the operation instructions for PIM data, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM solution.

[0024] In conjunction with the second aspect, in a possible manner, the preset division unit includes a rank or a bank. It can be seen that by dividing the memory into a common data memory space and a PIM data memory space according to the granularity of a rank or a bank, the physical isolation between the common data memory space and the PIM data memory space can be ensured, and data operation instructions are independently executed in corresponding ranks, thereby avoiding data read / write failures, and improving the effectiveness of data operations in the PIM solution.

[0025] In combination with the second aspect, in one possible manner, a memory space configuration instruction is sent to each memory particle included in each rank of the memory, the memory space configuration instruction includes memory space configuration information, and the memory space configuration information includes address information of ordinary data memory space and address information of PIM data memory space; wherein the memory space configuration instruction is used to trigger each memory particle to save the memory space configuration information. It can be seen that the processor can send memory space configuration information to the memory according to actual needs, so that the memory can be accurately divided into independent ordinary data memory space and PIM data memory space, which helps to isolate different types of data operation instructions from each other and not interfere with each other.

[0026] In conjunction with the second aspect, in one possible manner, a PIM mode configuration instruction is sent to a memory particle allocated to the PIM data memory space in the memory, and the PIM mode configuration instruction is used to trigger the memory particle allocated to the PIM data memory space to set the working mode of the PIM data memory space to the PIM mode. For example, the processor can send the PIM mode configuration instruction to the memory after the electronic device is powered on, or when the PIM data memory space and the ordinary data memory space are configured during the operation of the electronic device. It can be seen that the processor can flexibly control the memory to set the working mode of the PIM data memory space as needed, which helps to improve the utilization of memory resources.

[0027] In conjunction with the second aspect, in a possible manner, when the target memory space is the PIM data memory space, a normal mode configuration instruction is sent to the memory particles in the memory that are allocated to the PIM data memory space, and the normal mode configuration instruction is used to trigger the memory particles that are allocated to the PIM data memory space to set the working mode of the PIM data memory space to the normal mode. It can be seen that after the PIM data memory space executes the operation of the PIM data, the processor can control the memory to configure the working mode of the PIM data memory space to the normal mode, thereby realizing the reuse of the PIM data memory space, which helps to improve the utilization rate of memory resources.

[0028] In a third aspect, the present application provides an electronic device, comprising: one or more processors, memory and storage; the storage is coupled to the memory and the one or more processors, the storage is used to store computer program code, the computer program code includes computer instructions, and the memory calls the computer instructions to execute a method as described in any one of the first aspects above.

[0029] In a fourth aspect, the present application provides an electronic device, comprising: one or more processors, memory and storage; the storage is coupled to the memory and the one or more processors, the storage is used to store computer program code, the computer program code includes computer instructions, and the one or more processors call the computer instructions to execute any method described in any one of the second aspects above.

[0030] In a fifth aspect, the present application provides a chip system, which includes a processor, a memory controller DDRC and a memory, wherein: A processor, configured to generate a data operation instruction based on a target data address, and send the data operation instruction to the DDRC; DDRC, used to receive data operation instructions sent by the processor, and send data operation instructions to memory particles of the memory based on the target data address; The memory granules of the memory are used to receive the data operation instructions sent by the DDRC, and determine the target memory space of the memory based on the target data address. The target memory space is the common data memory space or the near memory computing PIM data memory space. The common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit. The memory particles of the memory are also used to respond to data operation instructions and perform data operations on the target memory space based on the target data address. It can be seen that in this technical solution, the processor can divide the memory into independent common data memory space and PIM data memory space, so that when the memory receives a data operation instruction, it can accurately distinguish the operation instructions for common data from the operation instructions for PIM data, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM solution.

[0031] In conjunction with the fifth aspect, in one possible manner, the memory particles of the memory include the processing unit PU corresponding to the PIM data memory space, and do not include the PU corresponding to the general data memory space. It can be seen that in this technical solution, only the corresponding processing unit PU is configured for the PIM data memory space, for example, only the PU is configured for each bank allocated to the PIM data memory space, and no PU is configured for each bank allocated to the general data memory space. While improving the effectiveness of data operations in the PIM solution, the memory cost and memory volume can be reduced, which is conducive to the miniaturization and lightweight design of electronic devices.

[0032] In a sixth aspect, the present application provides a computer-readable storage medium storing a computer program, which, when executed by memory particles of a memory, implements the method described in any one of the first aspects above.

[0033] In a seventh aspect, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the method described in any one of the second aspects above.

[0034] In an eighth aspect, the present application provides a computer program product comprising instructions, which, when executed on an electronic device, enables memory particles of a memory of the electronic device to execute a method as described in any one of the above-mentioned first aspects.

[0035] In a ninth aspect, the present application provides a computer program product comprising instructions, which, when executed on an electronic device, enables a processor of the electronic device to execute a method as described in any one of the second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1a A schematic diagram of splitting and rearranging instructions in a PIM solution provided in an embodiment of the present application; Figure 1b A schematic diagram of a data read operation in a PIM solution provided in an embodiment of the present application; Figure 2 A flowchart of a data operation method provided in an embodiment of the present application; Figure 3 A flowchart of another data operation method provided in an embodiment of the present application; Figure 4a A schematic diagram of data operation for performing memory partitioning according to ranks provided in an embodiment of the present application; Figure 4b A schematic diagram of a memory structure provided in an embodiment of the present application; Figure 5a A schematic diagram of data operation for performing memory division according to banks provided in an embodiment of the present application; Figure 5b A schematic diagram of data operations within a memory cell provided in an embodiment of the present application; Figure 6 A flowchart of another data operation method provided in an embodiment of the present application; Figure 7 A schematic diagram of a large model reasoning calculation process provided in an embodiment of the present application; Figure 8 A schematic diagram of the software structure of an electronic device provided in an embodiment of the present application; Fig. 9 A schematic diagram of the hardware structure of a chip system provided in an embodiment of the present application; Fig.10A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] The terms "first", "second", "third", etc. in the embodiments of the present application are distinguished from different objects, rather than being used to describe a specific order. In addition, the terms "include" and "have" and any variation thereof are intended to cover non-exclusive inclusions. For example, a series of steps or units are included, or alternatively, steps or units not listed are also included, or other steps or units inherent to these processes, methods, products or devices are optionally included. The terms "one embodiment" or "some embodiments", etc. mean that the specific features, structures or characteristics described in conjunction with the embodiment are included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in the differences in the embodiments of the present application are not necessarily all with reference to the same embodiment, but mean "one or more but not all embodiments", unless otherwise particularly emphasized.

[0039] In the embodiments of the present application, words such as "exemplary", "for example", or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary", "for example", or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example", or "for example" is intended to present related concepts in a specific way.

[0040] In addition, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects before and after the association are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c, where a, b, c can be single or plural.

[0041] In the current PIM solution, since the DDRC of the SOC does not support PIM instructions, PIM instructions can be understood as read / write instructions for data stored in the memory in the PIM format. Data stored in the PIM format can be understood as PIM data, such as the weight data of a large language model, so that the PIM function needs to reuse standard read and write instructions. In the PIM solution, there are requirements for the placement format of PIM data such as the weight data of a large language model. PIM data needs to be distributed in the same physical address range of the DRAMbank. One current practice is to define the same memory area in each bank of the memory particles of the memory DRAM to store the weight data of the large model. For example, the 3rd row (row) and the 5th column (column) of each bank are used to store PIM data, and the remaining memory areas are used to store other ordinary data.

[0042] If a standard read or write instruction falls into a pre-set memory area (such as the memory area where the PIM data in the bank is located), it will be recognized by the DRAM as a PIM operation instruction, and the operation instruction will be processed as a PIM operation and will be effective for all banks; if it falls into other areas, it will be recognized as a normal operation instruction and will only be effective for the bank specified by the operation instruction. However, since DDRC does not support PIM instructions, obstacles will be encountered when processing PIM instructions. Taking reading data as an example, for the read operation instruction issued by the CPU, DDRC will disassemble the instruction into a series of instructions, including activation instructions (Activate), read instructions (Read), etc. The activation instruction (Activate) can be to activate a row of the bank, and the read instruction (Read) can be to read data from a column of the activated row. At the same time, in order to improve efficiency, DDRC will reorder the activation instructions for different banks.

[0043] The splitting and rearrangement of instructions can be as follows: Figure 1aAs shown in the figure. The CPU sends the common read operation instruction and the PIM read operation instruction to the DDRC in sequence. After the DDRC splits and rearranges the instructions, it obtains a total of four instructions: the common activation instruction, the PIM activation instruction, the common read instruction, and the PIM read instruction. After the memory DRAM receives the above instructions, the process of executing the data read operation can be as follows Figure 1b As shown, Figure 1b The figure shows the state changes of any memory particle of the DRAM when executing the above four instructions, including the state ① corresponding to executing the normal activation instruction, the state ② corresponding to executing the PIM activation instruction, the state ③ corresponding to executing the normal read instruction, and the state ④ corresponding to executing the PIM read instruction.

[0044] Assume that the memory chip includes 16 banks, specifically bank 0-bank 15, and the x-th row and n-th column of each bank is used as the memory area for storing PIM data. The ordinary read operation instruction is for the x-th row and m-th column of bank 0, that is, data needs to be read from the x-th row and m-th column of bank 0. The PIM read operation instruction is for the y-th row and n-th column of bank 15. Since it is a read operation instruction for the memory area storing PIM data, it will be recognized as a PIM read operation instruction by DRAM, and therefore is effective for all banks, that is, data needs to be read from the y-th row and n-th column of all banks.

[0045] First, the internal controller of the memory chip executes a normal activation instruction to activate row x of bank 0, such as Figure 1b Then, the internal controller of the memory particle executes the PIM activation instruction to activate the yth row of all banks (bank 0-bank 15), as shown in Figure 1b As shown in the status ②.

[0046] Next, the internal controller of the memory chip executes a normal read instruction and needs to read data from bank 0. However, since two rows (row x and row y) of bank 0 are both activated, the data cannot be read correctly, resulting in a failure to read normal data. Figure 1b As shown in the status ③.

[0047] Similarly, the internal controller of the memory chip executes the PIM read instruction and needs to read data from all banks. However, since two rows (row x and row y) of bank 0 are both activated, data cannot be read correctly from bank 0, which eventually leads to the failure of PIM data reading. Figure 1b As shown in the status ④.

[0048] It can be seen that DDRC is not compatible with the current PIM solution, and it is impossible to correctly and effectively read and write data without modifying DDRC. In the related art, in order to ensure that data can be correctly and effectively read and written in the PIM solution, DDRC can be adapted and the hardware design of DDRC can be changed. However, this method requires a lot of adaptation work for DDRC, which is relatively complex to implement and has high costs.

[0049] Based on this, the data operation method provided in the embodiment of the present application can be applied to the scenario where the electronic device is deployed with a large language model on the end side and needs to perform PIM operation processing on the data stored in the PIM format such as the weight data of the large language model. The data operation method provided in the embodiment of the present application can divide the memory into independent ordinary data memory space and PIM data memory space, so as to accurately distinguish the ordinary operation instructions from the PIM operation instructions according to the memory space corresponding to the target data address, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM scheme, and can achieve compatibility between DDRC and the PIM scheme without changing the design of DDRC, thereby reducing the implementation cost of data operations in the PIM scheme.

[0050] Based on the PIM solution introduced in the above content, the data operation method provided by the embodiment of this application is introduced below. Figure 2 , Figure 2 A flowchart of a data operation method provided in an embodiment of the present application, the method may include but is not limited to the following steps: 201. Receive a memory space configuration instruction sent by a processor, where the memory space configuration instruction includes memory space configuration information.

[0051] The memory space configuration information includes address information of a common data memory space and address information of a near memory computing PIM data memory space. The address information of the common data memory space indicates the location of a memory area in the memory that is allocated to the common data memory space, and the address information of the PIM data memory space indicates the location of a memory area in the memory that is allocated to the PIM data memory space.

[0052] Specifically, the processor of the electronic device may send a memory space configuration instruction to the DDRC of the electronic device, the DDRC forwards the memory space configuration instruction to each memory cell of the memory of the electronic device, and the memory cell receives the memory space configuration instruction.

[0053] In one embodiment, the processor may send a memory space configuration instruction to a memory cell after the electronic device is powered on, or during the operation of the electronic device.

[0054] In one embodiment, DDRC may also save memory space configuration information, so that when the processor performs memory data operations, it can determine whether the data is located in the ordinary data memory space or the PIM data memory space based on the data address and the memory space configuration information, so that data operation instructions can be forwarded to the corresponding data memory space to achieve separation of different types of operation instructions.

[0055] In one embodiment, a memory particle may also be referred to as a memory chip or Die.

[0056] 202. In response to the memory space configuration instruction, save memory space configuration information.

[0057] Specifically, the memory particles respond to the memory space configuration instruction and save the memory space configuration information, that is, record the memory space configuration information. Since the memory space configuration information indicates the address information of the ordinary data memory space and the address information of the near-memory computing PIM data memory space, by saving the memory space configuration information, the memory particles can know the division of the memory, that is, the memory area corresponding to the ordinary data memory space and the memory area corresponding to the PIM data memory space in the memory.

[0058] In one embodiment, the memory space configuration information may be saved by an internal controller of the memory particle. For example, the memory space configuration information may be recorded in a mode register, or the memory space configuration information may be recorded using a designated memory space of the memory particle, thereby achieving accurate and complete recording of the memory space configuration information.

[0059] In one embodiment, the memory particles divide the memory into ordinary data memory space and PIM data memory space according to the address information of the ordinary data memory space and the address information of the PIM data memory space included in the memory space configuration information, according to the preset division unit. The ordinary data memory space and the PIM data memory space are different memory spaces. The memory can be divided into independent ordinary data memory space and PIM data memory space according to the preset division unit.

[0060] In one embodiment, the preset partitioning unit may be a rank or a bank.

[0061] In one embodiment, when the address information included in the memory space configuration information is a rank identifier, the preset division unit is a rank, that is, the first rank corresponding to the rank identifier in the address information of the ordinary data memory space is used as the ordinary data memory space. At this time, all banks of the memory particles included in the first rank are divided into the ordinary data memory space. Similarly, the second rank corresponding to the rank identifier in the address information of the PIM data memory space is used as the PIM data memory space. At this time, all banks of the memory particles included in the second rank are divided into the PIM data memory space. The first rank is different from the second rank, so that the memory is divided into two independent memory spaces according to the granularity of the rank, and physical isolation of the ordinary data memory space and the PIM data memory space at the rank level is realized. At this time, all memory spaces of a rank (specifically, all banks included in each memory particle in the rank) belong to the ordinary data memory space or the PIM data memory space.

[0062] In one embodiment, when the address information included in the memory space configuration information is a bank identifier, the preset division unit is a bank, that is, the first bank corresponding to the bank identifier in the address information of the ordinary data memory space is used as the ordinary data memory space. At this time, the first bank in each memory particle is divided into the ordinary data memory space. Similarly, the second bank corresponding to the bank identifier in the address information of the PIM data memory space is used as the PIM data memory space. At this time, the second bank in each memory particle is divided into the PIM data memory space. The first bank is different from the second bank, so that the memory is divided into two independent memory spaces according to the granularity of the bank, and physical isolation of the ordinary data memory space and the PIM data memory space at the bank level is achieved. At this time, a part of the memory space of each memory particle (specifically, it can be a part of the bank included in the memory particle) belongs to the ordinary data memory space, and the other part of the memory space (specifically, it can be another part of the bank included in the memory particle) belongs to the PIM data memory space.

[0063] 203. Obtain a PIM mode configuration instruction issued by the processor for the PIM data memory space.

[0064] Among them, the processor can perform mode management on the PIM data memory space. The working mode of the PIM data memory space can be divided into PIM mode and normal mode. In the PIM mode, the PIM data memory space is used to store PIM data and can execute operation instructions of PIM data; in the normal mode, the PIM data memory space is used to store normal data and can execute operation instructions of normal data.

[0065] Specifically, when the memory space configuration is completed, the processor can send a PIM mode configuration instruction for the PIM data memory space to the DDRC, the DDRC forwards the PIM mode configuration instruction to the memory particles in the memory allocated to the PIM data memory space, and the memory particles receive the PIM mode configuration instruction for the PIM data memory space.

[0066] 204. In response to the PIM mode configuration instruction, configure the working mode of the PIM data memory space to the PIM mode.

[0067] Specifically, the memory particle configures the working mode of the PIM data memory space to the PIM mode in response to the PIM mode configuration instruction. For example, the memory particle can use the reserved bit in the mode register to record the working mode of the PIM data memory space, and configure the working mode of the PIM data memory space to the PIM mode by modifying the value of the reserved bit, or the memory particle can also use the designated memory space to record whether the current working mode of the PIM data memory space is the PIM mode or the normal mode, thereby achieving effective management of the working mode of the PIM data memory space.

[0068] In one embodiment, the value of the reserved bit may be 0, indicating that the working mode of the PIM data memory space is the normal mode; the value of the reserved bit may be 1, indicating that the working mode of the PIM data memory space is the PIM mode. The value of the reserved bit may be 1, indicating that the working mode of the PIM data memory space is the normal mode; the value of the reserved bit may be 0, indicating that the working mode of the PIM data memory space is the PIM mode, which is not limited in the embodiments of the present application.

[0069] 205. Receive a data operation instruction from a memory controller DDRC, where the data operation instruction includes a target data address.

[0070] The data operation instruction is sent by the DDRC based on the target data address.

[0071] Among them, the data operation instruction can be a data read instruction or a data write instruction, which is not limited in the embodiment of the present application.

[0072] The target data address indicates the corresponding location of the data operation in the memory.

[0073] In one embodiment, the target data address includes rank information (such as rank identification), bank information (such as bank identification) and row and column information (such as row and column identification), that is, the target data address indicates the target rank targeted by this data operation, the target bank within the target rank, and the specific row and column positions within the target bank.

[0074] Specifically, the processor sends a data operation instruction to the DDRC, the DDRC determines the corresponding rank based on the target data address, and sends the data operation instruction to each memory particle included in the corresponding rank. For example, if the target data address indicates rank 0, the DDRC sends the data operation instruction to each memory particle included in rank 0, and each memory particle receives the data operation instruction from the DDRC.

[0075] In one embodiment, the DDRC may split the data operation instructions sent by the processor to obtain split operation instructions, and the DDRC sends the split operation instructions to the corresponding memory particles based on the target data address. For example, the data operation instructions sent by the processor are read operation instructions, and the operation instructions obtained after the DDRC splits the read operation instructions may include read activation instructions and read instructions.

[0076] 206. Determine a target memory space of the memory by matching the target data address with the memory space configuration information.

[0077] The target memory space is a common data memory space or a PIM data memory space. The common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit.

[0078] Specifically, the memory particle can obtain the saved memory space configuration information, match the target data address and the memory space configuration information to obtain a matching result, and determine the target memory space targeted by the data operation instruction according to the matching result. The target memory space is one of the ordinary data memory space and the PIM data memory space.

[0079] In one embodiment, a specific implementation of the memory particle determining the target memory space may include: When the target data address matches the address information of the PIM data memory space, the memory particle determines that the PIM data memory space in the memory is the target memory space. When the target data address matches the address information of the ordinary data memory space, the memory particle determines that the ordinary data memory space in the memory is the target memory space. It can be seen that by matching the target data address with the address information of the ordinary data memory space included in the memory space configuration information and the address information of the PIM data memory space, the target memory space corresponding to the current data operation instruction can be accurately identified.

[0080] In one embodiment, when the target memory space is a normal data memory space, the memory particle identifies the data operation instruction as a normal data operation instruction, and performs the data operation corresponding to the normal data operation instruction on the normal data memory space based on the target data address. When the target memory space is a PIM data memory space, the memory particle identifies the data operation instruction as a PIM data operation instruction, and performs the data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address. It can be seen that there is no need for DDRC to participate in identifying the type of data operation instruction. The memory particle accurately distinguishes the normal operation instruction from the PIM operation instruction according to the memory space corresponding to the target data address, and accurately executes the corresponding operation instruction in the memory space, which can improve the effectiveness of data operations in the PIM solution, and can achieve compatibility between the DDRC and the PIM solution without changing the design of the DDRC.

[0081] 207. When the target memory space is a normal data memory space, a data operation corresponding to a normal data operation instruction is performed on the normal data memory space based on the target data address.

[0082] Specifically, when the target memory space is a common data memory space, the memory particle identifies the data operation instruction as a common data operation instruction, and performs the data operation corresponding to the common data operation instruction on the common data memory space based on the target data address.

[0083] 208. When the target memory space is a PIM data memory space, obtain a working mode of the PIM data memory space.

[0084] 209. When the working mode of the PIM data memory space is the PIM mode, perform a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0085] 210. When the working mode of the PIM data memory space is not the PIM mode, perform a data operation corresponding to a common data operation instruction on the PIM data memory space based on a target data address.

[0086] Specifically, when the target memory space is the PIM data memory space, the memory particle may obtain the working mode of the PIM data memory space.

[0087] When the working mode of the PIM data memory space is the PIM mode, the memory particle determines that the data operation instruction is a PIM data operation instruction, and performs a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0088] When the working mode of the PIM data memory space is not the PIM mode, the memory particle determines that the data operation instruction is a common data operation instruction, and performs a data operation corresponding to the common data operation instruction on the PIM data memory space based on the target data address.

[0089] It can be seen that by identifying the working mode of the PIM data memory space, it can be determined whether the current data operation instruction for the PIM data memory space is a common data operation instruction or a PIM data operation instruction, thereby realizing the reuse of the PIM data memory space and helping to improve the utilization of memory resources.

[0090] In one embodiment, the memory particle includes a processing unit PU corresponding to the PIM data memory space, and the memory particle does not include a PU corresponding to the ordinary data memory space. The data operation instruction may be a read operation instruction of the PIM data. When the data operation corresponding to the PIM data operation instruction is performed on the PIM data memory space based on the target data address, the memory particle sends the data operation result to the PU. The data operation result may be the read PIM data (such as the weight data of the large language model). The PU performs arithmetic processing on the read PIM data to complete the PIM operation. It can be seen that the memory particle only needs to configure the PU for the PIM data memory space. While ensuring that the PIM data can be operated correctly and effectively, the memory cost and memory volume can be reduced, which is conducive to the miniaturization and lightweight design of electronic devices.

[0091] In one embodiment, when a data operation corresponding to a PIM data operation instruction is performed on the PIM data memory space based on a target data address, that is, when the PIM operation is completed, the processor can adjust the working mode of the PIM data memory space so that the PIM data memory space can be used to execute a normal data operation instruction. Specifically, the memory particle obtains the normal mode configuration instruction issued by the processor for the PIM data memory space, and in response to the normal mode configuration instruction, clears the data in the PIM data memory space and sets the working mode of the PIM data memory space to the normal mode. It can be seen that when the PIM operation is completed, the data in the PIM data memory space can be cleared, and the working mode can be set to the normal mode, so that the PIM data memory space can be used for normal data read and write operations, thereby realizing the reuse of the memory space and improving the utilization rate of memory resources.

[0092] In one embodiment, the preset division unit includes ranks, the first rank of the memory is divided into a common data memory space, the second rank of the memory is divided into a PIM data memory space, and the first rank is different from the second rank. In this case, the specific implementation method of performing data operations on the target memory space based on the target data address may include: When the target memory space is a normal data memory space, the memory particle that receives the data operation instruction is the first memory particle, and the first memory particle is any memory particle included in the first rank. The first memory particle identifies the data operation instruction as a normal data operation instruction, determines the target bank from the first memory particle according to the bank information included in the target data address, and performs normal data operations on the corresponding row and column positions in the target bank according to the row and column information included in the target data address.

[0093] When the target memory space is the PIM data memory space, the memory particle that receives the data operation instruction is the second memory particle, and the second memory particle is any memory particle included in the second rank. The second memory particle identifies the data operation instruction as a PIM data operation instruction, and the target data address includes certain bank information, such as the identifier of a certain bank. Since the data operation instruction is identified as a PIM data operation instruction at this time, the second memory particle performs the PIM data operation on the corresponding row and column positions in all banks of the second memory particle according to the row and column information included in the target data address.

[0094] It can be seen that by dividing the memory into ordinary data memory space and PIM data memory space according to rank, the physical isolation between the ordinary data memory space and the PIM data memory space can be guaranteed, and the data operation instructions are executed independently in the corresponding rank, avoiding conflicts between different types of data operation instructions, thereby avoiding data read / write failures, and improving the effectiveness of data operations in the PIM solution.

[0095] In one embodiment, the preset partitioning unit includes a bank, and the memory is partitioned according to the granularity of the physical bank. Assuming that the memory of the electronic device is dual-rank, for any rank, recorded as the third rank, multiple first banks of each memory particle included in the third rank are divided into ordinary data memory space, and multiple second banks are divided into PIM data memory space. For example, each memory particle includes 16 banks, specifically bank 0-bank 15, the first bank can refer to bank 0-bank 7 in the memory particle, and the second bank can refer to bank 8-bank 15 in the memory particle, that is, a part of the bank (such as the multiple first banks mentioned above) of each memory particle included in the third rank is divided into ordinary data memory space, and another part of the bank (such as the multiple second banks mentioned above) is divided into PIM data memory space, and the first bank is different from the second bank. In this case, the specific implementation method of performing data operations on the target memory space based on the target data address may include: When the target memory space is a normal data memory space, the memory particle that receives the data operation instruction is a third memory particle, and the third memory particle is any memory particle included in the third rank of the memory, that is, each third memory particle will receive the data operation instruction, and each third memory particle will identify the data operation instruction as a normal data operation instruction, and determine the target bank, such as bank 0, from the multiple first banks divided into the normal data memory space according to the bank information included in the target data address, and perform normal data operations on the corresponding row and column positions in the target bank according to the row and column information included in the target data address.

[0096] When the target memory space is the PIM data memory space, the memory particle that receives the data operation instruction is the third memory particle, and the third memory particle is any memory particle included in the third rank of the memory, that is, each third memory particle will receive the data operation instruction, and each third memory particle will identify the data operation instruction as a PIM data operation instruction. The target data address includes certain bank information, such as the identifier of a certain bank. Since the data operation instruction is identified as a PIM data operation instruction at this time, the third memory particle performs the PIM data operation on the corresponding row and column positions in all banks (such as all the second banks mentioned above) divided into the PIM data memory space according to the row and column information included in the target data address.

[0097] It can be seen that by dividing the memory into ordinary data memory space and PIM data memory space according to banks, the physical isolation between the ordinary data memory space and the PIM data memory space can be guaranteed, and data operation instructions are executed independently in the corresponding banks, avoiding conflicts between different types of data operation instructions, thereby avoiding data read / write failures, and improving the effectiveness of data operations in the PIM solution.

[0098] Based on the PIM solution introduced in the above content, the data operation method provided by the embodiment of this application is introduced below. Figure 3 , Figure 3 A flowchart of another data operation method provided in an embodiment of the present application, the method may include but is not limited to the following steps: 301. Send a memory space configuration instruction to each memory particle included in each rank of the memory, where the memory space configuration instruction includes memory space configuration information.

[0099] The memory space configuration information includes address information of the common data memory space and address information of the PIM data memory space.

[0100] The memory space configuration instruction is used to trigger each memory particle to save the memory space configuration information to complete the configuration of the memory space.

[0101] In one embodiment, the processor of the electronic device can send a memory space configuration instruction to the DDRC after the electronic device is powered on or during the operation of the electronic device, and the DDRC then forwards the memory space configuration instruction to each memory particle included in each rank.

[0102] 302. Send a PIM mode configuration instruction to a memory cell in the memory allocated to the PIM data memory space.

[0103] The PIM mode configuration instruction is used to trigger the memory particles allocated to the PIM data memory space to set the working mode of the PIM data memory space to the PIM mode.

[0104] Specifically, when the memory space configuration is completed, the processor can configure the working mode of the PIM data memory space. In the initial state, the working mode of the PIM data memory space can be a normal mode. When the PIM data memory space needs to be used to perform PIM data operations, the working mode of the PIM data memory space can be switched, and the PIM mode configuration instruction is sent to the DDRC. Then the DDRC sends the PIM mode configuration instruction to the memory particles in the memory allocated to the PIM data memory space.

[0105] Correspondingly, the memory particle receives the PIM mode configuration instruction and sets the working mode of the PIM data memory space to the PIM mode.

[0106] In one embodiment, the DDRC stores memory space configuration information. The DDRC can determine the memory particles allocated to the PIM data memory space based on the memory space configuration information, and send the PIM mode configuration instruction to the memory particles allocated to the PIM data memory space.

[0107] In one embodiment, the DDRC may send a PIM mode configuration instruction to all memory particles of the memory, and each memory particle receives the PIM mode configuration instruction. When it is determined that it is a memory particle allocated to the PIM data memory space according to the saved memory space configuration information, the PIM mode configuration instruction is executed to set the working mode of the PIM data memory space to the PIM mode. When it is determined that it is not a memory particle allocated to the PIM data memory space according to the saved memory space configuration information, the PIM mode configuration instruction is not executed. For example, when the memory is divided according to rank, all memory particles included in the rank allocated to the PIM data memory space may execute the PIM mode configuration instruction. When the memory is divided according to bank, all memory particles included in the memory may execute the PIM mode configuration instruction.

[0108] 303. Generate a data operation instruction based on the target data address.

[0109] The target data address indicates the corresponding location of the current data operation in the memory.

[0110] In one embodiment, the target data address includes rank information (such as rank identification), bank information (such as bank identification) and row and column information (such as row and column identification), that is, the target data address indicates the target rank targeted by this data operation, the target bank within the target rank, and the specific row and column positions within the target bank.

[0111] Specifically, for the processor, the storage location of the data to be read in the memory is known, including the storage location of the ordinary data in the memory and the storage location of the PIM data in the memory, or the specific location of the data to be written in the memory is known, including the memory location to be written to the ordinary data and the memory location to be written to the PIM data. According to the memory space configuration information, the target data address targeted by the data operation instruction can be determined, and the data operation instruction is generated according to the target data address.

[0112] 304. Send a data operation instruction to the memory controller DDRC, where the data operation instruction is used to trigger the DDRC to send the data operation instruction to the target memory cell of the memory based on the target data address.

[0113] The data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operation on the target memory space based on the target data address, the target memory space is the ordinary data memory space or the near memory computing PIM data memory space, and the ordinary data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit. The preset division unit includes rank or bank.

[0114] Specifically, the processor sends a data operation instruction to the memory controller DDRC. The DDRC does not need to identify the data operation instruction, and sends the data operation instruction to the corresponding target memory particle in the memory according to the target data address. The data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address.

[0115] In one embodiment, the data operation instruction sent by the DDRC to the target memory cell may be a split operation instruction, such as an activation instruction and a specific operation instruction arranged in sequence, for a read operation, specifically a read activation instruction and a read instruction, and for a write operation, specifically a write activation instruction and a write instruction.

[0116] Accordingly, the target memory particle receives the split operation instruction and executes the split operation instruction in the target memory space. For example, the target memory particle executes the activation instruction in the target memory space, and then executes the specific operation instruction in the activation area. For the PIM read operation, the target memory particle can execute the activation instruction for all banks corresponding to the target memory space (PIM data memory space in this case) according to the target data address, and then execute the PIM read operation instruction in the activation area of ​​each bank. For the normal read operation, the target memory particle can execute the activation instruction for the corresponding bank of the target memory space (normal data memory space in this case) according to the target data address, and then execute the normal read operation instruction in the activation area of ​​the bank.

[0117] The specific implementation of the target memory particle determining the target memory space of the memory based on the target data address and performing data operations on the target memory space can refer to the relevant description of steps 206-210 in the above embodiment, which will not be repeated here.

[0118] It can be seen that by dividing the memory into independent normal data memory space and PIM data memory space, when the processor sends data operation instructions to the memory, the memory particles can accurately distinguish the operation instructions for normal data from the operation instructions for PIM data, and accurately execute the corresponding operation instructions in the memory space, which can improve the effectiveness of data operations in the PIM solution.

[0119] 305. When the target memory space is the PIM data memory space, send a common mode configuration instruction to a memory cell in the memory that is allocated to the PIM data memory space.

[0120] The common mode configuration instruction is used to trigger the memory particles allocated to the PIM data memory space to set the working mode of the PIM data memory space to the common mode.

[0121] Specifically, when the target memory space is the PIM data memory space, the processor can send a common mode configuration instruction to the memory particles allocated to the PIM data memory space in the memory after performing data operations on the PIM data memory space. The common mode configuration instruction is used to trigger the memory particles allocated to the PIM data memory space to set the working mode of the PIM data memory space to the common mode. It can be seen that after the PIM data memory space performs the PIM data operation, the processor can control the memory to configure the working mode of the PIM data memory space to the common mode, thereby realizing the reuse of the PIM data memory space and helping to improve the utilization of memory resources.

[0122] In one embodiment, the processor can obtain the memory utilization rate, and when the memory utilization rate reaches a preset threshold, for example, the memory utilization rate is greater than or equal to 80%, a normal mode configuration instruction is sent to the memory particles in the memory that are allocated to the PIM data memory space, that is, when the remaining memory is insufficient, the PIM data memory space is considered to be released, for example, when the memory utilization rate does not reach the preset threshold, the working mode of the PIM data memory space does not need to be reconfigured at the next PIM operation, so as to ensure the efficiency of the PIM operation. It can be seen that by adjusting the working mode of the PIM data memory space in combination with the memory usage, the normal operation of various services such as the normal service and the PIM service can be ensured, which helps to improve the efficiency of service execution.

[0123] In one embodiment, Figure 4a As shown, it is a schematic diagram of data operation based on memory partitioning according to rank provided in an embodiment of the present application.

[0124] Among them, the memory rank 0 is divided into the normal data memory space (ie, normal DRAM), and the memory rank 1 is divided into the PIM data memory space (ie, PIM DRAM). The corresponding memory structure can be as follows Figure 4b As shown. In this case, taking the data read operation as an example, the CPU sends a common read operation instruction and a PIM read operation instruction to the DDRC. The DDRC splits the common read operation instruction to obtain the corresponding common activation instruction and common read instruction. The DDRC splits the PIM read operation instruction to obtain the corresponding PIM activation instruction and PIM read instruction. The DDRC sends the common activation instruction and the common read instruction to the common data memory space according to the rank information (i.e., rank 0) indicated by the data address included in the common read operation instruction. Specifically, the common activation instruction and the common read instruction may be sent to each memory particle included in rank 0, and each memory particle included in rank 0 executes the common activation instruction and the common read instruction on the corresponding bank according to the bank information indicated by the data address. The DDRC sends the PIM activation instruction and the PIM read instruction to the PIM data memory space according to the rank information (i.e., rank 1) indicated by the data address included in the PIM read operation instruction. Specifically, the PIM activation instruction and the PIM read instruction may be sent to each memory particle included in rank 1, and each memory particle included in rank 1 executes the PIM activation instruction and the PIM read instruction on all banks.

[0125] In one embodiment, Figure 4bAs shown, PIM DRAM (i.e., rank 1) uses PIM DRAM Die (including PIM DRAM Die 0, PIM DRAM Die 1, PIM DRAM Die 2, and PIM DRAM Die 3), and ordinary DRAM (i.e., rank 0) uses ordinary DRAM Die (including ordinary DRAM Die 0, ordinary DRAM Die 1, ordinary DRAM Die 2, and ordinary DRAM Die 3). Among them, each bank in PIM DRAM Die is configured with a corresponding processing unit PU, while each bank in ordinary DRAM Die is not configured with a corresponding PU. This can improve the effectiveness of data operations in the PIM solution while reducing memory costs and memory size, which is beneficial to the miniaturization and lightweight design of electronic devices.

[0126] In one embodiment, Figure 5a As shown, it is a schematic diagram of data operation of performing memory division according to banks provided in an embodiment of the present application.

[0127] Among them, bank 0-bank 7 of each memory particle is divided into ordinary data memory space (ie, ordinary DRAM), and bank 8-bank 15 of each memory particle is divided into PIM data memory space (ie, PIM DRAM).

[0128] In this case, taking the data read operation as an example, the data operation process in each memory particle can be as follows: Figure 5b As shown. The CPU sends a common read operation instruction and a PIM read operation instruction to the DDRC. The DDRC splits the common read operation instruction to obtain the corresponding common activation instruction and common read instruction. The DDRC splits the PIM read operation instruction to obtain the corresponding PIM activation instruction and PIM read instruction. The DDRC sends the split and rearranged operation instructions to all memory particles in the same rank, including the common activation instruction, the PIM activation instruction, the common read instruction, and the PIM read instruction. The memory particles recognize the common activation instruction and the common read instruction as common instructions, and recognize the PIM activation instruction and the PIM read instruction as PIM instructions according to the data addresses included in each operation instruction. The common instructions are executed for the common data memory space (i.e., bank 0-bank 7) in the memory particles, and the PIM instructions are executed for the PIM data memory space (i.e., bank 8-bank 15) in the memory particles.

[0129] Among them, it is assumed that the normal instruction is for the xth row and mth column of bank 0, that is, data needs to be read from the xth row and mth column of bank 0, and the PIM instruction is for the yth row and nth column of bank 15. Since it is a read operation instruction for the PIM data memory space, it will be recognized by DRAM as a PIM read operation instruction, so it is effective for all banks corresponding to the PIM data memory space, that is, data needs to be read from the yth row and nth column of all banks corresponding to the PIM data memory space. The specific execution process of the instruction can be as follows: The internal controller of the memory chip activates the xth row of bank 0 of the normal data memory space according to the data address included in the normal activation instruction (such as the xth row of bank 0), corresponding to Figure 5b The state in ①.

[0130] The internal controller of the memory chip activates the yth row of all banks (i.e., bank 8-bank 15) of the PIM data memory space according to the data address included in the PIM activation instruction (e.g., the yth row of bank 15), corresponding to Figure 5b Status② in .

[0131] When executing a normal read instruction, since only the xth row of bank 0 is activated, the internal controller of the memory chip successfully reads data from the mth column of the xth row of bank 0 according to the data address included in the normal read instruction (such as the mth column of bank 0), corresponding to Figure 5b Status ③.

[0132] When executing the PIM read instruction, since only the yth row of bank 8-bank 15 is activated, the internal controller of the memory chip can successfully read data from the nth column of the yth row activated in bank 8-bank 15 according to the data address included in the PIM read instruction (such as the nth column of bank 15), corresponding to Figure 5b Status ④.

[0133] In one embodiment, Figure 5b As shown, the corresponding processing unit PU can be configured only for the bank corresponding to the PIM data memory space (such as bank8-bank 15), while the bank corresponding to the common data memory space (such as bank 0-bank 7) is not configured with a PU. This can improve the effectiveness of data operations in the PIM solution while reducing memory costs and memory volume, which is beneficial to the miniaturization and lightweight design of electronic devices.

[0134] It can be seen that by dividing the memory into ordinary data memory space and PIM data memory space according to rank or bank, physical isolation between ordinary data memory space and PIM data memory space can be guaranteed, and data operation instructions are executed independently in the corresponding memory space, avoiding conflicts between different types of data operation instructions, thereby avoiding data read / write failures, and improving the effectiveness of data operations in the PIM solution. In addition, DDRC does not need to participate in the identification of instruction types, that is, the compatibility of DDRC and PIM solutions can be achieved without changing the design of DDRC.

[0135] Based on the PIM solution introduced in the above content, the data operation method provided by the embodiment of this application is introduced below. Figure 6 , Figure 6 A flowchart of another data operation method provided in an embodiment of the present application is provided. The method may include but is not limited to the following steps: 601. The processor sends memory space configuration information to the DDRC.

[0136] The memory space configuration information includes address information of the common data memory space and address information of the PIM data memory space.

[0137] 602. DDRC sends memory space configuration information to the memory cell.

[0138] Specifically, the DDRC receives the memory space configuration information sent by the processor, and sends the memory space configuration information to each memory cell of the memory.

[0139] 603. The memory particle stores memory space configuration information.

[0140] 604. The processor sends a PIM mode configuration instruction to the DDRC.

[0141] 605. DDRC sends a PIM mode configuration instruction to the memory cell.

[0142] Specifically, the DDRC sends the PIM mode configuration instruction to the memory particles in the memory that are allocated to the PIM data memory space.

[0143] 606. The memory particle configures the working mode of the PIM data memory space to the PIM mode.

[0144] 607. The processor sends a data operation instruction to the DDRC.

[0145] 608. DDRC sends a data operation instruction to the memory cell.

[0146] 609. The memory particle determines the target memory space of the memory by matching the target data address included in the data operation instruction with the memory space configuration information.

[0147] 610. When the target memory space is a common data memory space, the memory particle performs a data operation corresponding to a common data operation instruction on the common data memory space based on the target data address.

[0148] 611. The memory chip sends a first data operation result to the DDRC.

[0149] 612. The DDRC sends a first data operation result to the processor.

[0150] 613. When the target memory space is the PIM data memory space and the working mode of the PIM data memory space is the PIM mode, the memory particle performs a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address.

[0151] 614. The memory particle sends the second data operation result to the PU.

[0152] The second data operation result may refer to PIM data obtained by executing a data operation corresponding to a PIM data operation instruction on a PIM data memory space, such as weight data of a large language model.

[0153] 615. The PU performs a data operation based on the second data operation result.

[0154] 616. The processor obtains the data operation result from the PU.

[0155] 617. When the target memory space is the PIM data memory space and the working mode of the PIM data memory space is not the PIM mode, the memory particle performs a data operation corresponding to a common data operation instruction on the PIM data memory space based on the target data address.

[0156] 618. The memory chip sends the third data operation result to the DDRC.

[0157] 619. The DDRC sends the third data operation result to the processor.

[0158] The specific implementation of the above steps 601-619 can refer to the relevant description in the above embodiments, which will not be repeated here.

[0159] Based on the PIM solution introduced in the above content, the large model reasoning calculation method provided by the embodiment of this application is introduced below. Figure 7 , Figure 7A schematic diagram of a large model reasoning calculation process provided in an embodiment of the present application, the method may include but is not limited to the following steps: 701. Configure the physical address information corresponding to the PIM, with the minimum unit being bank.

[0160] The physical address information corresponding to the PIM may correspond to the address information of the PIM data memory space mentioned above.

[0161] 702. Clear or move data in the PIM DRAM and allocate the PIM DRAM to the PIM process.

[0162] 703. Load the large model weight data into PIM DRAM.

[0163] The PIM DRAM may be a type of memory of the PIM data memory space mentioned above.

[0164] Specifically, when the processor completes the configuration of the PIM DRAM, it can clear the data in the PIM DRAM, or move the data in the PIM DRAM to other storage spaces, which can be local disk spaces or cloud storage spaces, and the local disk space can include universal flash storage (UFS), etc. The processor allocates the cleared PIM DRAM to the PIM process, and can load PIM data such as large model weight data from the current disk space into the PIM DRAM.

[0165] Among them, before the PIM DRAM is configured to the PIM mode, the PIM DRAM is used as a storage space for ordinary data and can execute ordinary read and write instructions. The processor can use the write instructions of ordinary data to load large model weight data into the PIM DRAM.

[0166] 704. Configure the PIM DRAM to a PIM mode.

[0167] 705. Use the PIM mode to perform large model reasoning calculations.

[0168] Specifically, the processor uses PIM instructions to perform inference calculations on large models. The instructions required for the calculations can be converted into read instructions for a specific PIM DRAM bank, which are then split and rearranged by the DDRC and sent to the PIM DRAM. The PIM DRAM recognizes the instructions as PIM instructions, executes the reading of the large model weight data, and uses the PU to perform arithmetic processing on the large model weight data.

[0169] It can be seen that by dividing the memory into independent normal data memory space and PIM data memory space, when executing PIM operations (such as large model inference business), the normal operation instructions and PIM operation instructions are accurately distinguished according to the memory space corresponding to the data address (such as the specific PIM DRAM bank mentioned above), and the corresponding operation instructions are accurately executed in the memory space, which can improve the effectiveness of data operations in the PIM solution, thereby efficiently completing the inference calculation of the large model.

[0170] 706. Configure the PIM DRAM to a normal mode to release PIM DRAM space.

[0171] Specifically, the processor can configure the PIM DRAM to a normal mode and release the PIM DRAM space when the PIM DRAM operation processing is completed, such as clearing the PIM DRAM space and allocating the PIM DRAM to other processes for use, thereby realizing the reuse of the PIM data memory space and helping to improve the utilization of memory resources.

[0172] An embodiment of the present application also provides a software architecture for an electronic device.

[0173] In one embodiment, the software structure of the electronic device may adopt a layered architecture, an event-driven architecture, a micro-core architecture, a micro-service architecture, or a cloud architecture. The following takes the Android system of the layered architecture as an example to introduce a software structure of an electronic device.

[0174] like Figure 8 As shown, the layered architecture of the electronic device can be divided into several layers by software, and each layer has a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the Android system is divided into an application layer, an application framework layer, and a kernel layer from top to bottom.

[0175] The application layer may include a series of application packages, which may include camera, gallery, video playback, map, calendar, music, call and other applications. In the embodiment of the present application, the application layer may also include an AI assistant. The AI ​​assistant can provide a variety of services such as image processing, translation, writing, shopping, etc. by leveraging the capabilities of the large language model on the end side.

[0176] The application framework layer provides an application programming interface (API) and programming framework for the applications in the application layer. The application framework layer includes some predefined functions.

[0177] The application framework layer may include a window manager. The window manager is used to manage window programs. The window manager can obtain the display screen size, determine whether there is a status bar, lock the screen, capture the screen, etc.

[0178] The application framework layer can also include a view system, a notification manager, etc.

[0179] The view system includes visual controls, such as controls for displaying text, controls for displaying images, etc. The view system can be used to build applications. A display interface can be composed of one or more views. For example, a display interface including a text notification icon can include a view for displaying text and a view for displaying images.

[0180] The notification manager enables applications to display notification information in the status bar, which can be used to convey notification-type messages and disappear automatically after a short stay without user interaction.

[0181] The kernel layer is the layer between hardware and software. The kernel layer includes at least display driver, camera driver, audio driver, memory driver, processor driver, etc.

[0182] It should be noted that the various functional modules included in the above software structure are only exemplary and do not constitute a specific limitation on the software architecture of the mobile phone of the present application. In other embodiments, the various functional modules included in the above software structure may be more or less, and the present application does not limit this. Although the embodiments of the present application are described using the Android system as an example, the basic principles are also applicable to electronic devices based on operating systems such as iOS or Windows.

[0183] In the embodiments of the present application, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a personal digital assistant (PDA), etc., and the embodiments of the present application are not limited to this.

[0184] See also Fig. 9 , Fig. 9 A schematic diagram of the hardware structure of a chip system provided in an embodiment of the present application, the chip system may include but is not limited to: a processor, a DDRC and a memory, wherein: The processor is used to generate a data operation instruction based on a target data address and send the data operation instruction to the DDRC.

[0185] DDRC is used to receive data operation instructions sent by the processor and send data operation instructions to memory particles of the memory based on the target data address.

[0186] The memory particles of the memory are used to receive data operation instructions sent by DDRC, and determine the target memory space of the memory based on the target data address. The target memory space is the ordinary data memory space or the near memory computing PIM data memory space. The ordinary data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to the preset division unit.

[0187] The memory particles of the memory are also used to respond to data operation instructions and perform data operations on the target memory space based on the target data address.

[0188] In one embodiment, the memory granules of the memory include the processing units PU corresponding to the PIM data memory space, and do not include the PU corresponding to the common data memory space.

[0189] Exemplarily, the hardware structure of the electronic device in the embodiment of the present application is introduced below.

[0190] like Fig.10As shown, the electronic device may include: a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, a display screen 194, and a subscriber identification module (SIM) card interface 195, etc. Among them, the sensor module 180 may include a pressure sensor 180A, a gyroscope sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, etc.

[0191] The processor 110 may include one or more processing units, for example, the processor 110 may include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU), etc. Different processing units may be independent devices or integrated into one or more processors.

[0192] NPU is a neural network computing processor. It can quickly process input information and continuously self-learn by drawing on the structure of biological neural networks, such as the transmission mode between neurons in the human brain. NPU can realize applications such as intelligent cognition of electronic devices, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0193] The processor 110 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may store instructions or data that the processor 110 has just used or cyclically used. If the processor 110 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 110, and thus improves the efficiency of the system.

[0194] The internal memory 121 may be the aforementioned memory, such as a dynamic random access memory DRAM, for providing a common data memory space and a PIM data memory space. The electronic device may also include a DDRC, and the processor 110 sends a data operation instruction to the memory via the DDRC to perform a read / write operation on the memory.

[0195] The electronic device implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0196] The wireless communication function of the electronic device can be implemented through antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modem processor and baseband processor.

[0197] Antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve the utilization of the antennas. For example, antenna 1 can be reused as a diversity antenna for a wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0198] The mobile communication module 150 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to electronic devices. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 150 can receive electromagnetic waves from the antenna 1, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 1. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 can be set in the same device as at least some of the modules of the processor 110.

[0199] The wireless communication module 160 can provide wireless communication solutions including wireless local area networks (WLAN) (such as WiFi networks), Bluetooth (Blue Tooth, BT), BLE broadcasting, global navigation satellite system (GNSS), frequency modulation (FM), near field communication technology (NFC), infrared technology (IR), etc., which are applied to electronic devices. The wireless communication module 160 can be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, modulates the frequency of the electromagnetic wave signal and performs filtering, and sends the processed signal to the processor 110. The wireless communication module 160 can also receive the signal to be sent from the processor 110, modulate the frequency of it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 2.

[0200] The electronic device implements the display function through a GPU, a display screen 194, and an application processor. The GPU is a microprocessor for image processing, which connects the display screen 194 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 110 may include one or more GPUs that execute program instructions to generate or change display information.

[0201] The display screen 194 is used to display images, videos, etc. The display screen 194 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light emitting diode (OLED), an active matrix organic light emitting diode or an active matrix organic light emitting diode (AMOLED), a flexible light emitting diode (FLED), Miniled, MicroLed, MicrooLed, a quantum dot light emitting diode (QLED), etc. In some embodiments, the electronic device may include 1 or N display screens 194, where N is a positive integer greater than 1.

[0202] The touch sensor 180K is also called a "touch panel". The touch sensor 180K can be set on the display screen 194, and the touch sensor 180K and the display screen 194 form a touch screen, also called a "touch screen". The touch sensor 180K is used to detect touch operations acting on or near it. The touch sensor 180K can pass the detected touch operation to the application processor to determine the type of touch event. Visual output related to the touch operation can be provided through the display screen 194. In other embodiments, the touch sensor 180K can also be set on the surface of the electronic device, which is different from the position of the display screen 194.

[0203] It is to be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device. In other embodiments, the electronic device may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0204] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in this application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk Solid State Disk), etc.

[0205] It should be noted that, for the above-mentioned various method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0206] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs.

[0207] The modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0208] A person of ordinary skill in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable storage medium, which may include a flash drive, ROM, RAM, a magnetic disk or an optical disk, etc.

[0209] The above disclosure is only a preferred embodiment of the present application, which is only a part of the embodiments of the present application and cannot be used to limit the scope of rights of the present application.

Claims

1. A data operation method, characterized in that: The method comprises: receiving a data operation instruction from a memory controller DDRC, wherein the data operation instruction includes a target data address, and the data operation instruction is sent by the DDRC based on the target data address; Determine a target memory space of the memory based on the target data address, the target memory space is a common data memory space or a near memory computing PIM data memory space, the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; In response to the data operation instruction, a data operation is performed on the target memory space based on the target data address.

2. The method according to claim 1, characterized in that The determining a target memory space of a memory based on the target data address includes: Acquire memory space configuration information, where the memory space configuration information includes address information of a common data memory space and address information of a PIM data memory space; Based on the memory space configuration information and the target data address, determine the common data memory space or the PIM data memory space in the memory as the target memory space.

3. The method according to claim 2, characterized in that The determining, based on the memory space configuration information and the target data address, that a common data memory space or a PIM data memory space in the memory is a target memory space includes: In a case where the target data address matches the address information of the PIM data memory space, determining the PIM data memory space in the memory as the target memory space; In a case where the target data address matches the address information of the common data memory space, the common data memory space in the memory is determined to be the target memory space.

4. The method according to claim 2 or 3, characterized in that The method further comprises: Receive a memory space configuration instruction issued by a processor, wherein the memory space configuration instruction includes memory space configuration information; In response to the memory space configuration instruction, the memory space configuration information is saved.

5. The method according to any one of claims 1 to 3, characterized in that: The preset division unit includes a rank, and the performing a data operation on the target memory space based on the target data address includes: In the case where the target memory space is the common data memory space, a target bank is determined from a first memory particle according to the target data address, and a data operation is performed on the target bank according to the target data address, wherein the first memory particle is any memory particle included in a first rank in the memory allocated to the common data memory space; In the case where the target memory space is the PIM data memory space, performing data operations on all banks of a second memory cell according to the target data address, the second memory cell being any memory cell included in a second rank of the memory allocated to the PIM data memory space; The first rank is different from the second rank.

6. The method according to any one of claims 1 to 3, characterized in that: The preset partitioning unit includes a bank, and the performing a data operation on the target memory space based on the target data address includes: In the case where the target memory space is the common data memory space, determining a plurality of first banks included in a third memory particle and allocated to the common data memory space, determining a target bank from the plurality of first banks according to the target data address, and performing a data operation on the target bank according to the target data address; In the case where the target memory space is the PIM data memory space, determining all second banks allocated to the PIM data memory space from the third memory granule, and performing data operations on all the second banks according to the target data address; The third memory particle is any memory particle included in the third rank of the memory, and the first bank is different from the second bank.

7. The method according to any one of claims 1 to 3, characterized in that: The performing a data operation on the target memory space based on the target data address includes: When the target memory space is the PIM data memory space, obtaining a working mode of the PIM data memory space; When the working mode of the PIM data memory space is the PIM mode, performing a data operation corresponding to the PIM data operation instruction on the PIM data memory space based on the target data address; When the working mode of the PIM data memory space is not the PIM mode, a data operation corresponding to a common data operation instruction is performed on the PIM data memory space based on the target data address.

8. The method according to claim 7, characterized in that The method further comprises: Obtaining a PIM mode configuration instruction issued by the processor for the PIM data memory space; In response to the PIM mode configuration instruction, the operating mode of the PIM data memory space is set to the PIM mode.

9. The method according to claim 7, characterized in that The method further comprises: In a case where a data operation corresponding to a PIM data operation instruction is performed on the PIM data memory space based on the target data address, obtaining a common mode configuration instruction issued by a processor for the PIM data memory space; In response to the normal mode configuration instruction, the operating mode of the PIM data memory space is set to the normal mode.

10. A data operation method, characterized in that: The method comprises: generating a data operation instruction based on a target data address; Sending the data operation instruction to a memory controller DDRC, wherein the data operation instruction is used to trigger the DDRC to send the data operation instruction to a target memory particle of the memory based on the target data address; Among them, the data operation instruction is used to trigger the target memory particle to determine the target memory space of the memory based on the target data address, and perform data operations on the target memory space based on the target data address. The target memory space is a normal data memory space or a near memory computing PIM data memory space. The normal data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit.

11. The method according to claim 10, characterized in that The preset division unit includes a rank or a bank.

12. The method according to claim 10 or 11, characterized in that The method further comprises: Sending a memory space configuration instruction to each memory particle included in each rank of the memory, wherein the memory space configuration instruction includes memory space configuration information, and the memory space configuration information includes address information of a common data memory space and address information of a PIM data memory space; The memory space configuration instruction is used to trigger each memory particle to save the memory space configuration information.

13. The method according to claim 12, characterized in that The method further comprises: A PIM mode configuration instruction is sent to a memory cell in the memory that is allocated to the PIM data memory space, wherein the PIM mode configuration instruction is used to trigger the memory cell that is allocated to the PIM data memory space to set the working mode of the PIM data memory space to the PIM mode.

14. The method according to claim 13, characterized in that The method further comprises: When the target memory space is the PIM data memory space, a normal mode configuration instruction is sent to a memory particle in the memory allocated to the PIM data memory space, wherein the normal mode configuration instruction is used to trigger the memory particle allocated to the PIM data memory space to set the working mode of the PIM data memory space to the normal mode.

15. An electronic device, characterized in that: The electronic device comprises: one or more processors, storage and memory; the memory is used to store a first program code; the memory particles included in the memory are used to run the first program code to implement the method according to any one of claims 1-9.

16. An electronic device, characterized in that: The electronic device comprises: one or more processors, a memory and a storage; the memory is used to store a second program code; the processor is used to run the second program code to implement the method as described in any one of claims 10-14.

17. A chip system, characterized in that: The chip system includes a processor, a memory controller DDRC and a memory, wherein: The processor is used to generate a data operation instruction based on a target data address, and send the data operation instruction to the DDRC; The DDRC is used to receive the data operation instruction sent by the processor, and send the data operation instruction to the memory cell of the memory based on the target data address; The memory granule of the memory is used to receive the data operation instruction sent by the DDRC, and determine the target memory space of the memory based on the target data address, wherein the target memory space is a common data memory space or a near memory computing PIM data memory space, and the common data memory space and the PIM data memory space are different memory spaces obtained by dividing the memory according to a preset division unit; The memory particles of the memory are also used to respond to the data operation instruction and perform data operation on the target memory space based on the target data address.

18. The chip system according to claim 17, characterized in that: The memory particles of the memory include the processing units PU corresponding to the PIM data memory space, and do not include the PU corresponding to the common data memory space.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by the memory particles of the memory, implements the method according to any one of claims 1 to 9.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 10 to 14 is implemented.

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