Layout evaluation optimization method for high-speed and high-performance 3DIC

Abstract

The invention discloses a layout evaluation optimization method for a high-speed and high-performance 3DIC (three-dimensional integrated circuit), which relates to the technical field of electric data processing and comprises the following steps: acquiring a layout layout of the 3DIC; obtaining layout position data according to the layout layout of the 3DIC; according to the layout position data, carrying out design rule check on the layout of the 3DIC; according to the check result, adjusting the layout of the 3DIC; wherein the layout position data comprises the position data of the TSV, the position data of the electronic device and the position data of the marking module. According to the method, the layout layout of the 3DIC is obtained, the position data of important devices and modules are obtained from the layout layout, the layout is checked according to the layout position data, the layout structure needing to be evaluated and optimized is obtained, the layout of the 3DIC is adjusted in time, and the layout quality and performance of the 3DIC are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electrical data processing, and in particular to a layout evaluation and optimization method for high-speed and high-performance 3DIC. Background Art

[0002] TSV technology, namely through-silicon via technology, plays a key role in the field of three-dimensional integration. It allows chips to be electrically connected through tiny conductive holes in the vertical direction, thereby achieving high-density and high-performance packaging. However, when manufacturing 3DIC (Integrated Circuit), TSV will cause stress to devices within a certain range. At the same time, the high-frequency signal of TSV will also have a crosstalk risk to devices within a certain range. Therefore, it is necessary to check the TSV layout of 3DIC to ensure that the production of 3DIC can achieve the expected results.

[0003] The existing design rule check only meets the requirements of ordinary integrated circuits. The TSV layout check of highly sensitive and high-performance 3DICs is usually performed manually with the naked eye. The layout check of 3DICs has great limitations, resulting in low layout quality of 3DICs and low performance of the produced 3DICs. Summary of the invention

[0004] The purpose of the present invention is to provide a layout evaluation and optimization method for high-speed and high-performance 3DIC. The present invention obtains the layout map of the 3DIC, obtains the position data of important devices and modules from the layout map, and checks the layout according to the layout position data to obtain the layout structure that needs to be evaluated and optimized, and then timely adjusts the layout of the 3DIC, thereby improving the layout quality and performance of the 3DIC.

[0005] The purpose of the present invention is achieved by the following technical means: In a first aspect, the present invention provides a layout evaluation and optimization method for high-speed and high-performance 3DIC, comprising the following steps: Get the layout of 3DIC; According to the layout of the 3DIC, obtaining layout position data; Performing a design rule check on the layout of the 3DIC according to the layout position data; According to the inspection result, adjusting the layout of the 3DIC; The layout position data includes TSV position data, electronic device position data and marking module position data.

[0006] Preferably, the step of performing a design rule check on the layout of the 3DIC according to the layout position data comprises the following steps: Performing stress inspection on the TSV according to the position data of the TSV; Performing a spacing inspection on the electronic device according to the position data of the TSV and the position data of the electronic device; Performing a spacing check on the marking module according to the position data of the TSV and the position data of the marking module; Wherein, the electronic device includes an inductor device and a capacitor device.

[0007] Preferably, the stress inspection of the TSV according to the position data of the TSV comprises the following steps: According to the TSV position data, the area of ​​the TSV, the number of the TSVs and the spacing between the TSVs are acquired; Calculating a stress assessment parameter according to the area of ​​the TSV, the number of the TSVs, and the spacing between the TSVs; When the stress assessment parameter is less than the assessment threshold, it indicates that the stress is abnormal; The calculation formula of the stress assessment parameter is as follows: , in, is the stress assessment parameter, is the number of TSVs, is the area of ​​TSV, is the area of ​​3DIC, is the TSV pitch.

[0008] Preferably, the performing spacing inspection on the electronic device according to the position data of the TSV and the position data of the electronic device comprises the following steps: Acquiring edge data of the electronic device according to the position data of the electronic device; According to the position data of the TSV, obtaining the center data of the TSV and the radius data of the TSV; Calculating the distance between the TSV and the electronic device to obtain a first distance according to the edge data of the electronic device and the center data of the TSV; According to the first distance, the radius data of the TSV and the preset first spacing; performing spacing inspection on the electronic device; When the difference between the first distance and the radius data of the TSV is smaller than the preset first spacing, the position data of the TSV and the position data of the electronic device are output and a prompt indicating that the spacing is abnormal is displayed.

[0009] Preferably, before checking the spacing of the marking module according to the position data of the TSV and the position data of the marking module, the method further includes: marking the analog circuit module; specifically, the method includes the following steps: Acquire an analog circuit module in the layout diagram of the 3DIC; Using a rectangular boundary box to enclose the analog circuit module; The coordinate data of the rectangular bounding box is recorded to obtain the position data of the marking module.

[0010] Preferably, the step of performing spacing inspection on the marking module according to the position data of the TSV and the position data of the marking module comprises the following steps: According to the position data of the marking module, the center data of the marking module, the width data of the marking module and the height data of the marking module are acquired; According to the position data of the TSV, obtaining the center data of the TSV and the radius data of the TSV; According to the sum of the preset second spacing and the radius data of the TSV, the center data of the marking module, the width data of the marking module, and the height data of the marking module, the marking module is expanded outward to obtain a first area; Performing a spacing check on the marking module according to the center data of the first area and the TSV; When the center data of the TSV is located in the first area, the position data of the TSV and the position data of the marking module are output and a prompt indicating that the spacing is abnormal is displayed.

[0011] Preferably, adjusting the layout of the 3DIC according to the inspection result comprises the following steps: When the stress check of TSV is abnormal, adjust the layout of TSV; When the spacing inspection of electronic devices is abnormal, adjust the layout of the electronic devices; When the spacing check of the marking module is abnormal, set a grounded metal protection ring.

[0012] In a second aspect, the present invention provides a layout evaluation and optimization system for high-speed and high-performance 3DIC, which applies the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC, including: a layout acquisition module, a data acquisition module, a layout inspection module and a layout adjustment module; The layout acquisition module is used to acquire the layout of the 3DIC; The data acquisition module is used to acquire layout position data according to the layout of the 3DIC; The layout checking module is used to perform a design rule check on the layout of the 3DIC according to the layout position data; The layout adjustment module is used to adjust the layout of the 3DIC according to the inspection report; The layout position data includes TSV position data, electronic device position data and marking module position data.

[0013] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory is used to store computer program code, and the computer program code comprises computer instructions. When the processor executes the computer instructions, the electronic device executes the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC.

[0014] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, wherein the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention obtains the layout of 3DIC, obtains the position data of important devices and modules from the layout, checks the layout according to the layout position data, obtains the layout structure that needs to be evaluated and optimized, and then adjusts the layout of 3DIC in time, thereby improving the layout quality and performance of 3DIC. The present invention reduces the influence of TSV and its preparation process on the device and improves the layout quality and performance of 3DIC by checking the stress of TSV, the spacing of electronic devices and the spacing of marking modules according to the position data of TSV, the position data of electronic devices and the position data of marking modules. The present invention obtains the area, number and spacing of TSVs and calculates stress evaluation parameters, thereby providing a data basis for 3DIC layout evaluation. The present invention obtains edge data of the electronic device and center data of the TSV to calculate the first distance, thereby providing a data basis for the layout evaluation of the 3DIC; The present invention obtains the center data, width data and height data of the marking module and the radius data of the TSV to calculate the first area, thereby providing a data basis for the layout evaluation of the 3DIC. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A schematic diagram of a flow chart of a layout evaluation and optimization method for high-speed and high-performance 3DIC provided in this embodiment; Figure 2 A schematic diagram of the process of step S3 provided in this embodiment; Figure 3 A schematic diagram of the process of step S31 provided in this embodiment; Figure 4 A schematic diagram of the process of step S33 provided in this embodiment; Figure 5 A schematic diagram of the process of step S34 provided in this embodiment; Figure 6 A schematic diagram of the process of step S35 provided in this embodiment; Figure 7 A schematic diagram of the process of step S4 provided in this embodiment; Figure 8 A schematic diagram of the structure of a layout evaluation and optimization method for high-speed and high-performance 3DIC provided in this embodiment; Fig. 9 A schematic diagram of the structure of an electronic device provided in this embodiment. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0021] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0022] This embodiment provides a layout evaluation optimization method for high-speed and high-performance 3DIC. Figure 1 As shown, the following steps are included: S1, obtain the layout of 3DIC; S2, obtaining layout position data according to the layout of 3DIC; S3, performing design rule check on the layout of 3DIC based on the layout position data; S4, adjusting the layout of 3DIC according to the inspection results; The layout position data includes TSV position data, electronic device position data and marking module position data.

[0023] It should be noted that 3DIC is the layout of the integrated circuit 3DIC, which is the arrangement of various electronic devices and their interconnection methods. The layout data records all the information describing the physical structure and layout of the integrated circuit, including the location and size of electronic devices, interconnection lines, connection holes, layer information and layer structure, etc. The design rule check is to check whether the layout design meets the requirements of the preparation process. It can be checked before the chip is produced to find the layout structure that needs to be optimized.

[0024] In this embodiment, by obtaining the layout of the 3DIC, obtaining the position data of important devices and modules from the layout, and checking the layout according to the layout position data, the layout structure that needs to be evaluated and optimized is obtained, and then the layout of the 3DIC is adjusted in time, thereby improving the layout quality and performance of the 3DIC.

[0025] In some embodiments, step S3, a design rule check is performed on the layout of the 3DIC according to the layout position data, such as Figure 2 As shown, the following steps are included: S31, performing stress inspection on the TSV according to the position data of the TSV; S33, performing a spacing inspection on the electronic device according to the position data of the TSV and the position data of the electronic device; S35, performing a spacing check on the marking module according to the position data of the TSV and the position data of the marking module; Among them, the electronic devices include inductive devices and capacitive devices.

[0026] It should be noted that the layout position data includes the position data of TSV, electronic devices and marking modules. The introduction of TSV needs to consider the following aspects: TSV will generate thermal or mechanical stress in semiconductor devices. When this stress becomes larger, it will cause TSV cracking or deformation of surrounding materials, thereby affecting the performance of 3DIC; capacitive coupling between TSVs will cause crosstalk between signals, thereby affecting signal integrity; contaminants in the TSV preparation process will diffuse to the surrounding device area, thereby affecting the performance of 3DIC. Therefore, it is necessary to ensure that the stress generated by TSV has little effect on 3DIC and that the interference generated by TSV has little effect on the devices or modules of the integrated circuit. Therefore, the design rule check of the layout of 3DIC based on TSV, electronic devices and marking modules requires the stress check of TSV, the spacing check between electronic devices and TSV, and the spacing check between the marking module and TSV in turn.

[0027] In this embodiment, by checking the stress of TSV, the spacing of electronic devices and the spacing of marking modules according to the position data of TSV, the position data of electronic devices and the position data of marking modules, the influence of TSV and its preparation process on devices is reduced, and the layout quality and performance of 3DIC are improved.

[0028] In some embodiments, in step S31, a stress check is performed on the TSV according to the position data of the TSV, such as Figure 3 As shown, the following steps are included: S311, acquiring the area of ​​the TSV, the number of the TSVs, and the spacing between the TSVs according to the position data of the TSVs; S312, calculating stress assessment parameters according to the area of ​​the TSV, the number of the TSVs, and the spacing between the TSVs; S313, when the stress assessment parameter is less than the assessment threshold, a stress abnormality is indicated; The calculation formula of stress assessment parameters is as follows: , in, is the stress assessment parameter, is the number of TSVs, is the area of ​​TSV, is the area of ​​3DIC, is the TSV pitch.

[0029] It should be noted that the stress assessment parameter is used to indicate the result of stress assessment. It measures stress by the size of TSV, the number of TSVs and the spacing between TSVs, and can directly reflect the stress condition of TSV. The larger the stress assessment parameter, the better the stress condition of TSV. Therefore, an assessment threshold can be set in advance. When the stress assessment parameter is less than the assessment threshold, the inspection result indicates that the stress is abnormal. The assessment threshold is set according to actual production and is not limited in this embodiment.

[0030] In this embodiment, by obtaining the area, number and spacing of TSVs and calculating stress evaluation parameters, a data basis is provided for layout evaluation of 3DIC.

[0031] In some embodiments, in step S33, a spacing check is performed on the electronic device based on the position data of the TSV and the position data of the electronic device, such as Figure 4 As shown, the following steps are included: S331, acquiring edge data of the electronic device according to the position data of the electronic device; S332, acquiring the center data of the TSV and the radius data of the TSV according to the position data of the TSV; S333. Calculate the distance between the TSV and the electronic device to obtain a first distance based on the edge data of the electronic device and the center data of the TSV; S334, performing a spacing inspection on the electronic device according to the first distance, the radius data of the TSV and the preset first spacing; S335 , when the difference between the first distance and the radius data of the TSV is smaller than the preset first spacing, outputting the position data of the TSV and the position data of the electronic device and indicating that the spacing is abnormal.

[0032] It should be noted that electronic devices include inductors and capacitors, and these electronic devices have different shapes. When checking the spacing of electronic devices, the inspection is performed by obtaining the first distance, the radius data of the TSV, and the preset first spacing. The first distance is the closest distance between the center of the TSV and the edge of the electronic device. The preset first spacing is the distance threshold at which the electronic device is affected by the TSV. It is set according to actual production and is not limited in this embodiment. When the difference between the first distance and the radius of the TSV is less than the preset first spacing, the inspection result indicates that the spacing with the electronic device is abnormal.

[0033] In this embodiment, the first distance is calculated by acquiring edge data of the electronic device and center data of the TSV, thereby providing a data basis for layout evaluation of the 3DIC.

[0034] In some embodiments, before step S35, based on the position data of the TSV and the position data of the marking module, the marking module is checked for spacing, the step further includes: step S34, marking the analog circuit module; Figure 5 As shown, the specific steps include: S341, obtaining an analog circuit module in a layout diagram of a 3DIC; S342, using a rectangular bounding box to enclose the analog circuit module; S343, record the coordinate data of the rectangular boundary box to obtain the position data of the marking module.

[0035] In some embodiments, in step S35, a spacing check is performed on the marking module according to the position data of the TSV and the position data of the marking module, such as Figure 6 As shown, the following steps are included: S351, acquiring center data of the marking module, width data of the marking module, and height data of the marking module according to the position data of the marking module; S352, acquiring the center data of the TSV and the radius data of the TSV according to the position data of the TSV; S353, according to the sum of the preset second spacing and the radius data of the TSV, the center data of the marking module, the width data of the marking module, and the height data of the marking module, the marking module is expanded outward to obtain a first area; S354, performing a spacing check on the marking module according to the center data of the first area and the TSV; S355 , when the center data of the TSV is located in the first area, the position data of the TSV and the position data of the marking module are output and a prompt indicating that the spacing is abnormal is displayed.

[0036] It should be noted that the analog circuit modules of 3DIC, such as power modules, RF modules, and analog-to-digital conversion modules, are easily affected by chemical contamination during the TSV preparation process. A rectangular bounding box is used to mark the analog circuit modules, and the position representation of the core modules is unified. The position data of the marking module includes the center coordinates, the module width, and the module height. The spacing of the marking module is checked by expanding the marking module outward to obtain the first area. Specifically, for the edge of the marking module, the value of the preset second spacing is directly expanded outward on the basis of the original edge. When the second spacing is preset, the distance threshold of the marking module affected by TSV is set according to actual production and is not limited in this embodiment. Specifically, taking the center data as , the width data is , the height data is , the second spacing is preset to For example, the horizontal coordinate of the original side on the left side of the marking module is , the vertical axis is , then the horizontal coordinate of the new side after the left extension is , the vertical axis is ; For the expansion of the upper left corner of the marking module, the radius is the preset second spacing, and the coordinates of the corner point of the upper left corner are formed as a quarter of the circle of the center. Other positions are deduced in this way to obtain the first area. When the center data of the TSV is located in the first area, the inspection result indicates that the spacing of the marking module is abnormal.

[0037] In this embodiment, the first area is calculated by acquiring the center data, width data and height data of the mark module and the radius data of the TSV, thereby providing a data basis for the layout evaluation of the 3DIC.

[0038] In some embodiments, in step S4, the layout of the 3DIC is adjusted according to the inspection result, such as Figure 7 As shown, the following steps are included: S41, when the stress check of the TSV is abnormal, adjusting the layout of the TSV; S42, when the spacing check of the electronic device is abnormal, adjusting the layout of the electronic device; S43, when the spacing check of the marking module is abnormal, a grounded metal protection ring is set.

[0039] It should be noted that the inspection process is, in sequence, TSV stress inspection, TSV and electronic device spacing inspection, and TSV and marking module spacing inspection. The adjustments to these three abnormal situations are to adjust the layout of TSV, the layout of electronic devices, and set a ground protection ring. When the layout of TSV is adjusted, it will affect the inspection results of electronic devices and marking modules. Similarly, when the layout of electronic devices is adjusted, it will affect the inspection results of the marking module. Therefore, the above-mentioned design rule check can set inspection termination monitoring. When one of the inspections finds an abnormality, the inspection is stopped and the inspection report is output, and then the layout of 3DIC is adjusted, which improves the layout quality and performance of 3DIC, and at the same time, improves the inspection efficiency and R&D rate of 3DIC.

[0040] This embodiment provides a layout evaluation and optimization system for high-speed and high-performance 3DIC, and applies the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC, such as Figure 8 As shown, it includes: a layout acquisition module, a data acquisition module, a layout checking module and a layout adjustment module; Layout acquisition module, used to obtain the layout of 3DIC; A data acquisition module is used to acquire layout position data according to the layout of 3DIC; The layout check module is used to perform design rule check on the layout of 3DIC based on the layout position data; The layout adjustment module is used to adjust the layout of 3DIC according to the inspection report; The layout position data includes TSV position data, electronic device position data and marking module position data.

[0041] In this embodiment, by obtaining the layout of the 3DIC, obtaining the position data of important devices and modules from the layout, and checking the layout according to the layout position data, the layout structure that needs to be evaluated and optimized is obtained, and then the layout of the 3DIC is adjusted in time, thereby improving the layout quality and performance of the 3DIC.

[0042] It should be understood that the disclosed system can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, each functional module can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0043] This embodiment provides an electronic device 2, such as Fig. 9 As shown, a processor 21 and a memory 22, the memory 22 is used to store computer program codes, the computer program codes include computer instructions, when the processor 21 executes the computer instructions, the electronic device executes the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC.

[0044] The electronic device 2 includes a processor 21, a memory 22, an output device 23, and an input device 24. The processor 21, the memory 22, the output device 23, and the input device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0045] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor 21 may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0046] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory 22 includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), and the memory 22 is used for related instructions and data.

[0047] The input device 24 is used to input data and / or signals, and the output device 23 is used to output data and / or signals. The output device 23 and the input device 24 can be independent devices or an integrated device.

[0048] This embodiment provides a computer-readable storage medium, in which a computer program is stored. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes the above-mentioned layout evaluation and optimization method for high-speed and high-performance 3DIC.

[0049] The above are only specific embodiments of the present invention, which enable those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A layout evaluation and optimization method for high-speed and high-performance 3DIC, characterized in that: The following steps are involved: Get the layout of 3DIC; According to the layout of the 3DIC, obtaining layout position data; Performing a design rule check on the layout of the 3DIC according to the layout position data; According to the inspection result, adjusting the layout of the 3DIC; Wherein, the layout position data includes TSV position data, electronic device position data and marking module position data; The step of performing a design rule check on the layout of the 3DIC according to the layout position data comprises the following steps: Performing stress inspection on the TSV according to the position data of the TSV; Performing a spacing inspection on the electronic device according to the position data of the TSV and the position data of the electronic device; Performing a spacing check on the marking module according to the position data of the TSV and the position data of the marking module; Wherein, the electronic device includes an inductor device and a capacitor device.

2. The layout evaluation and optimization method for high-speed and high-performance 3DIC according to claim 1, characterized in that: The step of performing stress inspection on the TSV according to the position data of the TSV comprises the following steps: According to the TSV position data, the area of ​​the TSV, the number of the TSVs and the spacing between the TSVs are acquired; Calculating a stress assessment parameter according to the area of ​​the TSV, the number of the TSVs, and the spacing between the TSVs; When the stress assessment parameter is less than the assessment threshold, it indicates that the stress is abnormal; The calculation formula of the stress assessment parameter is as follows: ， in, is the stress assessment parameter, is the number of TSVs, is the area of ​​TSV, is the area of ​​3DIC, is the TSV pitch.

3. The layout evaluation and optimization method for high-speed and high-performance 3DIC according to claim 1, characterized in that: The step of performing spacing inspection on the electronic device according to the position data of the TSV and the position data of the electronic device comprises the following steps: Acquiring edge data of the electronic device according to the position data of the electronic device; According to the position data of the TSV, the center data of the TSV and the radius data of the TSV are acquired; Calculating the distance between the TSV and the electronic device to obtain a first distance according to the edge data of the electronic device and the center data of the TSV; According to the first distance, the radius data of the TSV and the preset first spacing; performing spacing inspection on the electronic device; When the difference between the first distance and the radius data of the TSV is smaller than the preset first spacing, the position data of the TSV and the position data of the electronic device are output and a prompt indicating that the spacing is abnormal is displayed.

4. The layout evaluation and optimization method for high-speed and high-performance 3DIC according to claim 1, characterized in that: Before checking the spacing of the marking module according to the position data of the TSV and the position data of the marking module, the method further includes: marking the analog circuit module; specifically, the following steps are included: Acquire an analog circuit module in the layout diagram of the 3DIC; Using a rectangular boundary box to enclose the analog circuit module; The coordinate data of the rectangular bounding box is recorded to obtain the position data of the marking module.

5. The layout evaluation and optimization method for high-speed and high-performance 3DIC according to claim 1, characterized in that: The step of performing spacing inspection on the marking module according to the position data of the TSV and the position data of the marking module comprises the following steps: According to the position data of the marking module, the center data of the marking module, the width data of the marking module and the height data of the marking module are acquired; According to the position data of the TSV, obtaining the center data of the TSV and the radius data of the TSV; According to the sum of the preset second spacing and the radius data of the TSV, the center data of the marking module, the width data of the marking module, and the height data of the marking module, the marking module is expanded outward to obtain a first area; Performing a spacing check on the marking module according to the center data of the first area and the TSV; When the center data of the TSV is located in the first area, the position data of the TSV and the position data of the marking module are output and a prompt indicating that the spacing is abnormal is displayed.

6. The layout evaluation and optimization method for high-speed and high-performance 3DIC according to claim 1, characterized in that: The step of adjusting the layout of the 3DIC according to the inspection result comprises the following steps: When the stress check of TSV is abnormal, adjust the layout of TSV; When the spacing inspection of electronic devices is abnormal, adjust the layout of the electronic devices; When the spacing check of the marking module is abnormal, set a grounded metal protection ring.

7. A layout evaluation and optimization system for high-speed and high-performance 3DIC, using a layout evaluation and optimization method for high-speed and high-performance 3DIC as claimed in any one of claims 1 to 6, characterized in that: include: Layout acquisition module, data acquisition module, layout checking module and layout adjustment module; The layout acquisition module is used to acquire the layout of the 3DIC; The data acquisition module is used to acquire layout position data according to the layout of the 3DIC; The layout checking module is used to perform a design rule check on the layout of the 3DIC according to the layout position data; The layout adjustment module is used to adjust the layout of the 3DIC according to the inspection report; The layout position data includes TSV position data, electronic device position data and marking module position data.

8. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store computer program codes, and the computer program codes include computer instructions. When the processor executes the computer instructions, the electronic device executes a layout evaluation and optimization method for high-speed and high-performance 3DIC as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a layout evaluation and optimization method for high-speed and high-performance 3DIC as described in any one of claims 1 to 6.

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