QFN (quad flat no-lead) packaged semiconductor device and manufacturing method thereof
By designing a molded compound structure with different thicknesses in the QFN package semiconductor device, the solder breakage problem caused by mismatch in the thermal expansion coefficient in the QFN package is solved, and the plate-level reliability and the reliability of the solder joint are improved.
Patent Information
- Application Number
- CN202310785840.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
The plate-level reliability and solder joint reliability of QFN packages are problematic due to mismatch between the coefficient of thermal expansion between the EMC compound and the metal lead frame, resulting in the solder being prone to break at the bonding wire.
Design a QFN packaged semiconductor device, including a die pad on the bottom surface, a plurality of leads and molded compounds, to form thickness differences between the central and peripheral regions by reducing the thickness in the peripheral region to reduce the thermal expansion mismatch effect, The thickness of the molded compound is between 0.7 and 3 times the peripheral region, and the distance extending inward from the periphery of the device is between 1 and 1.3 times the length of the lead exposure.
By reducing the thermal expansion mismatch effect between the package molded compounds and the die and the metal lead frame, the stress on the lead is reduced, the plate-level reliability of QFN packages and the reliability of solder joints are improved, and the possibility of welding failures is reduced.
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Figure CN119230487A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to integrated circuit (IC) packaging. More particularly, the present disclosure relates to quad flat no-lead (QFN) packaged semiconductor devices and methods of manufacturing the same. Background Art
[0002] For QFN packages, especially small QFNs, board-level reliability and solder joint reliability have always been challenges.
[0003] The limitations on board-level reliability and solder joint reliability of QFN packages are mainly caused by the mismatch of CTE (coefficient of thermal expansion) between the EMC compound and the metal lead frame. Specifically, solder fractures are prone to occur at the bonding wires around the QFN. This is mainly because a lot of stress is concentrated at the top of the bonding wires around the QFN, and the solder is more likely to fall off or break at the bonding wires around the QFN than in the middle area of the QFN.
[0004] Therefore, reducing the thermal expansion mismatch effect between the encapsulation EMC compound and the metal lead frame can improve the board-level reliability and solder joint reliability of the QFN package. Summary of the invention
[0005] According to a first aspect of the present disclosure, a QFN packaged semiconductor device having a bottom surface is provided, the QFN packaged semiconductor device comprising: a die pad on the bottom surface; a die on the die pad; a plurality of leads, the leads being spaced apart from the die pad and surrounding a peripheral area of the bottom surface; a plurality of bonding wires, the bonding wires connecting the die to the leads; and a molding compound covering the die and the bonding wires, wherein the QFN packaged semiconductor device has a first thickness in a central area and a second thickness across the peripheral area, and wherein the second thickness is less than the first thickness.
[0006] In one or more embodiments, the peripheral region surrounds the central region.
[0007] In one or more embodiments, a thickness of the molding compound in the central region ranges between 0.7 and 3 times a thickness of the molding compound in the peripheral region.
[0008] In one or more embodiments, the central region extends beyond the perimeter of the die by a distance in a range between 0.7 and 1.3 times the thickness of the molding compound in the central region.
[0009] In one or more embodiments, the peripheral region extends inwardly from the perimeter of the device by a distance that is in a range between 1 and 1.3 times an exposed length of the lead on the bottom surface.
[0010] In one or more embodiments, the thickness of the peripheral area is in the range between 0.2 mm and 0.6 mm. In one or more embodiments, the thickness of the peripheral area is 0.2 mm and 0.4 mm. In one or more embodiments, the central area has a first top surface, and the distance from the first top surface to the top surface of the tube core is in the range between 0.4 mm and 0.7 mm. In one or more embodiments, the central area has a first top surface and a first side, the peripheral area has a second top surface and a second side, and the angle between the second top surface and the first side is a right angle. In one or more embodiments, the angle between the second top surface and the first side is an obtuse angle. In one or more embodiments, each first side is a flat surface. In one or more other embodiments, each first side is a curved surface.
[0011] According to another aspect of the present disclosure, a method for manufacturing a QFN packaged semiconductor device is provided, wherein the QFN packaged semiconductor device has a bottom surface and includes a die pad on the bottom surface and a plurality of leads spaced apart from the die pad and surrounding a peripheral region of the bottom surface, the method comprising: attaching a die to the die pad; forming wire bonds between the die and the plurality of leads; encapsulating the die and the wire bonds with a molding compound so that the QFN packaged semiconductor device has a first thickness in a central region and a second thickness across the peripheral region of the QFN packaged semiconductor device, wherein the second thickness is less than the first thickness; and singulating the QFN package.
[0012] In one or more embodiments, the peripheral region surrounds the central region.
[0013] In one or more embodiments, a thickness of the molding compound in the central region ranges between 0.7 and 3 times a thickness of the molding compound in the peripheral region.
[0014] In one or more embodiments, the peripheral region extends inwardly from the perimeter of the device a distance between 1 and 1.3 times the exposed length of the leads on the bottom surface.
[0015] In one or more embodiments, the method further includes forming a second thickness in the peripheral area by sawing the molding compound of the peripheral area.
[0016] In one or more embodiments, the method further includes forming a second thickness in the peripheral region by adding a raised portion in the mold of the molding compound.
[0017] In one or more embodiments, the thickness of the peripheral zone is in the range between 0.2 mm and 0.6 mm.
[0018] In one or more embodiments, each central region has a first top surface and a first side, each peripheral region has a second top surface and a second side, and the angle between the second top surface and the first side is a right angle. In one or more other embodiments, the angle between the second top surface and the first side is an obtuse angle. In one or more embodiments, the first side is a flat surface. In one or more other embodiments, the first side is a curved surface.
[0019] According to one or more embodiments, the thickness of the peripheral region of the molding compound surrounding the QFN package is reduced. Thus, the stress on the leads generated by the mismatch of the thermal expansion coefficients between the package molding compound (on the one hand) and the die and / or metal lead frame (on the other hand) is reduced.
[0020] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The embodiments will be described by way of example only with reference to the accompanying drawings, in which
[0022] Figure 1 is a cross-sectional view of a QFN packaged semiconductor device according to one or more embodiments of the present disclosure;
[0023] Figure 2 is a cross-sectional view of a QFN packaged semiconductor device according to one or more embodiments of the present disclosure;
[0024] Figure 3 is a cross-sectional view of a QFN packaged semiconductor device according to one or more embodiments of the present disclosure;
[0025] Figure 4 is a flow chart for manufacturing a QFN packaged semiconductor device according to one or more embodiments of the present disclosure.
[0026] It should be noted that the figures are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative dimensions and proportions of the various parts of these figures have been shown as enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION
[0027] Detailed description embodiments of the present invention are disclosed herein. However, for the purpose of describing the exemplary embodiments of the present invention, the specific structural and functional details disclosed herein are merely representative. The present invention can be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein. In addition, the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the exemplary embodiments of the present invention.
[0028] As used herein, the singular forms "a / an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms "comprises, comprising, includes and / or including" specify the presence of stated features, steps or components, but do not exclude the presence or addition of one or more other features, steps or components. It should also be noted that in some alternative embodiments, the functions / actions mentioned may not appear in the order mentioned in the figures. For example, depending on the functionality / actions involved, two figures shown in succession may actually be executed substantially simultaneously or may sometimes be executed in reverse order.
[0029] Reference Figure 1 , a cross-sectional view of a QFN packaged semiconductor device according to one or more embodiments of the present disclosure is shown. The QFN packaged semiconductor device 100 includes: a die pad 10, a plurality of leads 20, a die 30 (which is typically rectangular or square and may also be referred to as a semiconductor die), and a molding compound 40. The leads 20 typically include copper or a copper alloy. The die 30 is typically mounted on the die pad 10, which may also be referred to as a die pad, by means of a conductive epoxy or other means known to those skilled in the art. The die pad 10 is typically rectangular and may be square and is typically larger than the die 30. The die pad 10 is typically located in the center, and the lower face of the die pad forms part of the bottom surface of the QFN packaged semiconductor device 100, that is, the lower face is away from the periphery of the QFN packaged semiconductor device 100. The leads 20 typically surround the die 30 on all four sides of the die 30 and the die pad 10, and are spaced apart from the die 30 with the molding compound 40 therebetween. Typically, the leads 30 are formed from the same lead frame as the die pad 10 and are initially integral, but then separated during the assembly process. Bond wires 33 are shown connecting bond pads 32 on the top surface of the die 30 to the leads 20. Except on the underside or lowermost surface of the die pad 10 and the leads 20, the structures are encapsulated in a mold compound 40. As shown in the figure, the lowermost surface and outermost ends of the leads 20 are exposed and are not encapsulated or covered by the mold compound 40.
[0030] The mold compound 40 has a central region 47 and a peripheral region 42. The central region 47 is the central region of the mold compound 40. The peripheral region 42 is the peripheral region of the mold compound 40. The central region 47 is generally located at the center above the tube core 30, that is, the central region 47 is away from the periphery of the QFN package semiconductor device 100. The peripheral region 42 is above the leads 20 surrounding the periphery of the QFN package semiconductor device 100. The central region 47 has a thickness corresponding to the full thickness of the mold compound. This portion can be described as having a full thickness and can be referred to as a full thickness portion. The peripheral region 42 can be thinned during the assembly process and can therefore be described as a half-thickness region.
[0031] Each central region 47 has a first top surface 41 and a first side 43, and each peripheral region 42 has a second top surface 46 and a second side 44, wherein each first side 43 extends between the first top surface 41 and the second top surface 46 and is at an angle θ with the second top surface 46, and each second side 44 extends vertically between the second top surface 46 and the bottom surface 45. The first side 43 can be a flat surface. The angle θ can be a right angle. The thickness T of the peripheral region 42 can typically be in the range of 0.1 mm to 0.4 mm. The distance D from the top surface 41 of the mold compound 40 to the top surface of the tube core 30 can typically be in the range of 0.4 mm to 0.7 mm. The thickness T can be one-fifth to four-fifths of the distance D.
[0032] Comparing the QFN packaged semiconductor device 100 to a conventional QFN package in which the mold compound does not include a relatively thin peripheral region, it will be appreciated that the thickness T is less than the thickness of the mold compound over the leads of the conventional QFN package. Figure 1 ” is shown as “P” in . Specifically, according to an embodiment of the present invention, the molding compound is substantially thicker around the peripheral region, and particularly above the leads, than in the central region. This can reduce or even completely avoid problems associated with differences in the coefficient of thermal expansion (CTE) between the molding compound and other portions of the packaged semiconductor device (particularly the semiconductor die 30 and the die pad 10 and leads 20). In conventional devices, as already mentioned, CTE differences can result in increased stress and / or strain occurring around the peripheral region, leading to potential delamination or failure of the solder joints. Considered from another perspective, the molding compound according to an embodiment of the present disclosure more closely resembles a conformal coating or conformal covering of a die mounted on a lead frame (separated into electrically isolated die pads 10 and leads 20). Providing the molding compound as a conformal coating or similar or near conformal coating can again more evenly distribute the stress and / or strain caused by the CTE differences between the molding compound 40 and the die 30 or the die pad 10 and the leads 20, thereby again reducing the possibility of delamination or solder joint failure.
[0033] Reference Figure 2 , similar to Figure 1 , the QFN packaged semiconductor device 200 includes: a die pad 10, a plurality of leads 20, and a die 30. Each central region 47 has a first top surface 41 and a first side 43, and each peripheral region 42 has a second top surface 46 and a second side 44, wherein each first side 43 extends between the first top surface 41 and the second top surface 46 and is at an angle θ with the second top surface 46, and each second side 44 extends vertically between the second top surface 46 and the QFN bottom surface 45. The first side 43 may be a flat surface. The angle θ may be an obtuse angle. That is, the top of the central region 47 is smaller than the bottom. Providing an inclined sidewall may help facilitate demolding. Specifically, in the absence of a vertical surface of a molded device, it is generally much easier to remove the packaged semiconductor device 200 by vertically ejecting from an injection molding tool that can be used to encapsulate the mounted semiconductor die with a molding compound. This is because the vertical surface may "stick" to the vertical tool wall during ejection. The thickness T of the peripheral region 42 may conveniently be 0.1 mm to 0.4 mm. The distance D from the top surface 41 of the mold compound 40 to the top surface of the die 30 may conveniently be 0.4 mm to 0.7 mm. The thickness T may typically be one-fifth to four-fifths of the distance D. Specifically, it will be appreciated that because the leads 20 are thinner and less rigid than the combination of the die pad 10 and the mounted die 30, equal bending forces or stresses applied to the leads due to the CTE difference may provide a greater deflection or strain of the leads 20 than the die 30 mounted on the die pad 10. Therefore, it may be desirable for the thickness T of the mold compound over the leads 20 to be less than the distance D corresponding to the thickness of the mold compound over the die 30 in order to reduce the stress at the leads 20 relative to the stress at the die 1030.
[0034] Reference Figure 3 , similar to Figure 1 and 2 The device shown in , the QFN packaged semiconductor device 300 includes: a die pad 10, a plurality of leads 20, and a die 30. Each central area 47 has a first top surface 41 and a first side 43, and each peripheral area 42 has a second top surface 46 and a second side 44, wherein each first side 43 extends between the first top surface 41 and the second top surface 46, and each second side 44 extends vertically between the second top surface 46 and the QFN bottom surface 45. The first side 43 may be a curved surface. The approximate thickness of the peripheral area 42 is T, which may conveniently be 0.1 mm to 0.4 mm. The distance from the first top surface 41 of the molding compound 40 to the top surface of the die 30 is D, and D may conveniently be 0.4 mm to 0.7 mm. The thickness T may typically be one-fifth to four-fifths of the distance D. The curved profile, and in particular, for example Figure 3, providing a thinner area of molding compound to facilitate molding in a molding molding tool as discussed above. Where the profile is provided by the shape of the molding tool, the corners 48 between the molded sidewall or first side 43 and the top surface and the corners 49 between the molded sidewall and the second face 43 may conveniently be rounded (not shown) to simplify the injection molding process, as will be familiar to those skilled in the art. In other embodiments, as will be discussed in more detail below, the molded profile may be provided by a partial cut through the packaged device by a saw blade; in this case, the corners need not be rounded, but may be sharp, such as Figure 3 as shown in .
[0035] Reference Figure 4 , this figure shows a flow chart depicting a method for manufacturing a QFN packaged semiconductor device according to one or more embodiments of the present invention. The QFN packaged semiconductor has a bottom surface and includes a die pad on the bottom surface, and a plurality of leads spaced apart from the die pad and surrounding a peripheral region of the bottom surface. The method includes: S101, attaching a die to the die pad; S102, forming wire bonds between the die and the plurality of leads; S103, encapsulating the die and the wire bonds with a molding compound having a central region and a peripheral region, wherein the height of the peripheral region is lower than the height of the central region; and S104, singulating QFN packaging.
[0036] In one or more embodiments, each central region has a first top surface and a first side, each peripheral region has a second top surface, and each first side extends between the first top surface and the second top surface and is angled with the second top surface.
[0037] In one or more embodiments, optionally, there are at least two methods of forming the peripheral region: the first method is to form the peripheral region of the molding compound, which is initially above the leads at full thickness, and then remove the top part (part or portion), such as by partially cutting with a saw or cutting wheel; the second method is to use a forming molding tool used during injection molding of the molding compound. This can be achieved, for example, by adding a raised portion to form a frame around the periphery of the upper half of the molding tool. Since the molding compound fills the space between the mold and the assembly of the die and leads on the die pad, adding the raised portion to the mold reduces the amount of molding compound that can be injected. The raised portion corresponds to the opposite position and shape of the desired peripheral region, and the peripheral region is formed after demolding. For example, if Figure 1 As shown, the cross-section of the raised portion may be rectangular, so the cross-section of the peripheral region has a corresponding rectangular recess. Figure 2 As shown in , the cross section of the raised portion may be trapezoidal, so that the cross section of the peripheral region has a corresponding trapezoidal depression. Figure 3As shown in , the cross-section of the raised portion may be a portion of a circle or ellipse or other generally smooth curve, so that the cross-section of the peripheral region has a corresponding depression of the portion of the circle or curve. Of course, those skilled in the art will appreciate that the molding tool itself may be manufactured to include a "raised portion" rather than the raised portion being a separate frame added to the mold.
[0038] In one or more embodiments, after singulation, each side surface of each lead and each second side surface of the peripheral region extending vertically between the second top surface and the bottom surface are exposed.
[0039] In one or more embodiments, a method of manufacturing a QFN packaged semiconductor device includes: a thickness of the peripheral region is one fifth to four fifths of a distance from the first top surface to a top surface of the die.
[0040] In one or more embodiments, a method of manufacturing a QFN packaged semiconductor device includes: a thickness of the peripheral region is 0.1 mm to 0.4 mm.
[0041] In one or more embodiments, a method of manufacturing a QFN packaged semiconductor device includes: a distance from the first top surface to a top surface of the die is 0.4 mm to 0.7 mm.
[0042] In one or more embodiments, the angle with the surface of the peripheral region is a right angle. In one or more embodiments, the angle with the surface of the peripheral region is an obtuse angle. In one or more embodiments, the first side of the semiconductor device is a flat surface. In one or more embodiments, the first side of the semiconductor device is a curved surface.
[0043] It will be apparent to one skilled in the art that any range or device value given herein may be expanded or altered without losing the effect sought.
[0044] Although the present invention has been described in the context of an IC package having a single die and a single electrical connector, it will be appreciated that the present invention may be implemented in the context of an IC package having any suitable number of dies and any suitable number of electrical connectors.
[0045] Moreover, for the purposes of this specification, the term "connect, connecting or connected" refers to any means known in the art or subsequently developed, which allows energy to be transferred between two or more elements, and the insertion of one or more additional elements is expected, but not required. In contrast, the terms "directly coupled", "directly connected", etc. imply the absence of such additional elements.
[0046] The use of figure numbers and / or figure reference signs in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use should not be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures.
[0047] Unless expressly stated otherwise, each numerical value and range should be interpreted as approximations as if the word "about" or "approximately" preceded such value or range.
[0048] It will be appreciated that persons skilled in the art may make various changes in the details, materials and arrangements of parts which have been described and shown to explain embodiments of the invention without departing from the embodiments of the invention as encompassed in the appended claims.
[0049] It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be exemplary only. Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined in methods consistent with various embodiments of the present invention.
[0050] Although elements in the following method claims (if any) are recited in a specific order with corresponding labels, those elements are not necessarily intended to be limited to implementation in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of those elements.
[0051] References herein to "one embodiment" or "embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily refer to all of the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. The same applies to the term "embodiment".
[0052] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any novel feature combination or any generalized form thereof disclosed explicitly or implicitly herein, regardless of whether it relates to the same invention as currently claimed in any claim or whether it alleviates the same technical problem as any or all of the technical problems alleviated by the present invention.
[0053] It should be noted that one or more of the above embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method claims, while other embodiments may have been described with reference to apparatus claims. However, those skilled in the art will appreciate from the foregoing that, unless otherwise stated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, in particular a combination of features of method claims and features of apparatus claims, are also deemed to be disclosed with this document.
Claims
1. A QFN packaged semiconductor device having a bottom surface, characterized in that: The QFN packaged semiconductor device comprises: a die pad on said bottom surface; a die on the die pad; a plurality of leads spaced apart from the die pad and surrounding a peripheral region of the bottom surface; a plurality of bonding wires connecting the die to the leads, and a molding compound covering the die and the bond wires, wherein the QFN packaged semiconductor device has a first thickness in a central region and a second thickness across the peripheral region, and The second thickness is smaller than the first thickness.
2. The QFN packaged semiconductor device according to claim 1, wherein: The central region has a first top surface and a first side surface, the peripheral region has a second top surface and a second side surface, and an angle between the second top surface and the first side surface is a right angle.
3. The QFN packaged semiconductor device according to claim 1, wherein: The central region has a first top surface and a first side surface, the peripheral region has a second top surface and a second side surface, and an angle between the second top surface and the first side surface is an obtuse angle.
4. The QFN packaged semiconductor device according to claim 1, wherein: The central region has first sides, and each first side is a flat surface.
5. The QFN packaged semiconductor device according to claim 1, wherein: The central area has a first side, and the first side is a curved surface.
6. A method of manufacturing a QFN packaged semiconductor device having a bottom surface and comprising a die pad on the QFN bottom surface and a plurality of leads spaced from the die pad and surrounding a peripheral region of the bottom surface, characterized in that: The method comprises: attaching a die to the die pad; forming wire bonds between the die and a plurality of leads; encapsulating the die and the wire bonds with a molding compound such that the QFN packaged semiconductor device has a first thickness in a central region of the QFN packaged semiconductor device and a second thickness across the peripheral region of the QFN packaged semiconductor device, wherein the second thickness is less than the first thickness; and The QFN packaged semiconductor devices are singulated.
7. The method for manufacturing a QFN packaged semiconductor device according to claim 6, wherein: Also includes: A second thickness is formed in the peripheral region by sawing the molding compound of the peripheral region.
8. The method for manufacturing a QFN packaged semiconductor device according to claim 6, wherein: Also includes: A second thickness is formed in the peripheral region by adding raised portions in the mold of the molding compound.
9. The method for manufacturing a QFN packaged semiconductor device according to claim 6, wherein: The central region has a first top surface and a first side surface, the peripheral region has a second top surface and a second side surface, and an angle between the second top surface and the first side surface is a right angle or an obtuse angle.
10. The method for manufacturing a QFN packaged semiconductor device according to claim 6, wherein: The central area has a first side, and the first side is a flat surface or a curved surface.