Chip overheating automatic protection control method and system

Abstract

The present invention provides a chip overheating automatic protection control method and system, which relates to the field of chip protection technology, including arranging distributed temperature sensors on a chip, acquiring real-time temperature data of different areas inside the chip, dynamically adjusting the frequency and accuracy of data collection, and generating an optimized temperature data stream; inputting the optimized temperature data stream into a pre-trained temperature anomaly detection model, detecting the temperature anomaly of each area in the chip in real time, and outputting the temperature anomaly level of the abnormal area, triggering thermal emergency processing of different intensities according to the temperature anomaly level, and sending the temperature and power consumption information of the abnormal area to a global manager; generating an initial chip protection strategy, and predicting the future temperature change trend of the chip, identifying potential high-temperature abnormal areas, optimizing the initial chip protection strategy in combination with the prediction results, generating an optimal chip protection strategy, and realizing chip overheating automatic protection control according to the optimal chip protection strategy.

Description

Technical Field

[0001] The present invention relates to chip protection technology, and in particular to a chip overheating automatic protection control method and system. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, the integration and power density of chips are constantly improving. The heat generated by high-performance chips during operation is also increasing. Chip overheating has become one of the key factors affecting chip reliability and performance. Chip overheating will not only lead to accelerated device aging and functional failure, but may even cause serious consequences such as chip burning. Therefore, the thermal management of chips has attracted much attention.

[0003] Traditional chip thermal management methods mainly include passive heat dissipation and active heat dissipation. Passive heat dissipation is to enhance the heat conduction between the chip and the heat sink by optimizing the layout and wiring of the chip and selecting high thermal conductivity materials, so as to promote the dissipation of the heat generated by the chip. Active heat dissipation is to forcibly take away the heat from the chip surface through fans, liquid cooling and other methods. However, traditional thermal management methods are difficult to adapt to the heating requirements of modern high-performance chips. There are problems such as slow response speed and delayed overheating protection, and it is impossible to achieve real-time perception and dynamic control of the chip's thermal state. In response to the above problems, the industry has proposed a variety of improved solutions for chip overheating protection. One solution is to integrate a temperature sensor on the chip to monitor the temperature distribution of the chip in real time, and trigger a protection mechanism when an overheating risk is detected, such as reducing the chip frequency and shutting down some functional units. Another solution is to integrate a thermal management controller on the chip to dynamically adjust the power consumption allocation and working mode of the chip according to temperature feedback. Another solution is predictive thermal management based on thermal models. By building a thermal model of the chip, the future temperature changes of the chip are predicted, and overheating protection measures are taken in advance. Although the above solutions have improved the effect of chip overheating protection to a certain extent, there are still some limitations.

[0004] Therefore, there is an urgent need for a more intelligent and adaptive chip overheating automatic protection control method that can achieve real-time perception, accurate prediction and dynamic optimization of the chip thermal state, while reducing the chip area and power consumption overhead and improving the chip reliability and performance. Summary of the invention

[0005] The embodiments of the present invention provide a chip overheating automatic protection control method and system, which can solve the problems in the prior art.

[0006] According to a first aspect of the embodiments of the present invention,

[0007] A chip overheating automatic protection control method is provided, comprising:

[0008] Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip. The temperature data is transmitted through the on-chip interconnection network, and the data is aggregated and compressed. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream.

[0009] The optimized temperature data stream is input into the pre-trained temperature anomaly detection model to detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area. Different intensity thermal emergency processing is triggered according to the temperature anomaly level, and the temperature and power consumption information of the abnormal area is sent to the global manager.

[0010] The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. Automatic chip overheating protection control is implemented based on the optimal chip protection strategy.

[0011] In an optional embodiment,

[0012] Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip, including:

[0013] Discretize the chip plane into a set of grid cells, each grid cell represents a possible sensor placement position, and the sensor layout scheme is represented as a binary string, and the sensor layout problem is mathematically modeled and encoded;

[0014] According to the obtained grid cells, a plurality of initial sensor layout schemes are randomly generated as initial particles, where the position and velocity of each particle are represented by the corresponding binary string;

[0015] For the sensor layout scheme represented by each particle, the corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, a comprehensive objective function of each initial sensor layout scheme is constructed to evaluate the fitness of the particle. The prior rules of sensor layout constructed based on the power consumption distribution and hot spot distribution of the chip are used as constraints for the sensor layout problem.

[0016] According to the fitness evaluation results of the particles, the individual optimal position and the global optimal position of each particle are updated. The speed update formula is used to combine the current position, individual optimal position and global optimal position of each particle to update the speed of the particle at the next moment. According to the updated speed, the position of the particle is updated to generate a new sensor layout plan.

[0017] Based on the new sensor layout scheme, the Gaussian mutation operation is introduced, and the non-dominated sorting algorithm is used to screen the particles to obtain the updated particle swarm. The iteration is repeated until the maximum number of iterations is reached, and the sensor layout scheme represented by the global optimal particle is output as the optimal sensor layout scheme.

[0018] The optimal sensor layout scheme is mapped to the chip physical design, and the layout and interconnection topology of the sensor array are automatically generated. According to the obtained layout and interconnection topology of the sensor array, distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip.

[0019] In an optional embodiment,

[0020] The corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, the calculation formula for the comprehensive objective function of each initial sensor layout scheme is constructed as follows:

[0021] ;

[0022] Among them, J represents the comprehensive objective function, ω 1 represents the sensor weight, N represents the number of grid cells, and x i represents a binary variable, which determines whether a sensor is placed in the i-th grid cell in the sensor layout scheme. ω 2 represents the monitoring coverage weight, β represents the density coefficient, γ represents the exponential function attenuation parameter of the control distance, d(i, j) represents the distance between the i-th grid cell and the j-th grid cell, ω 3 represents the sensitivity weight of hotspot detection, H represents the sample subset, T(i) represents the temperature parameter of grid cell i, λ represents the penalty coefficient, and P(x) represents the degree of violation of the prior rules by the layout scheme.

[0023] In an optional embodiment,

[0024] The optimized temperature data stream is input into the pre-trained temperature anomaly detection model to detect the temperature anomalies in each area of ​​the chip in real time. The steps before that also include:

[0025] A temperature anomaly detection model is constructed based on a long short-term memory neural network, wherein the temperature anomaly detection model includes an encoder and a decoder. The encoder maps the input temperature sequence to a latent space, and the decoder reconstructs the output temperature sequence from the latent space.

[0026] Acquire historical temperature data when the chip is working normally and perform preprocessing to obtain a normal temperature sequence data set, use the normal temperature sequence data set to pre-train the anomaly detection model, and obtain initial model parameters by minimizing the reconstruction error between the input temperature sequence and the reconstructed temperature sequence;

[0027] In each training iteration, a batch of normal samples are sampled from the normal temperature sequence data set, the normal samples are input into the current anomaly detection model, the gradient information of the samples is calculated, and the gradient information is used to add perturbations to the normal samples to obtain adversarial samples;

[0028] The normal samples and adversarial samples are combined to obtain comprehensive training samples, and the adversarial loss function on the comprehensive training samples is calculated. The gradient of the temperature anomaly detection model parameters is calculated according to the adversarial loss function using the stochastic gradient descent method, the initial model parameters are updated, and the iteration is repeated until the preset termination condition is met to obtain the final trained temperature anomaly detection model.

[0029] In an optional embodiment,

[0030] The normal sample and the adversarial sample are combined to obtain a comprehensive training sample, and the adversarial loss function on the comprehensive training sample is calculated, including:

[0031] The singular values ​​of the weight matrix are introduced as low-rank constraints, and the classification loss of normal samples and the classification loss of adversarial samples are combined to construct a joint adversarial loss function. The calculation formula is as follows:

[0032] ;

[0033] Among them, L represents the adversarial loss function, E n represents the expected value of normal samples, f(·) represents the discriminator function of the temperature anomaly detection model, and E a represents the expected value of the adversarial sample, x represents the normal sample, and x a represents the adversarial sample, ζ represents the weight coefficient of the low-rank constraint term, G represents the number of neural network layers, m g represents the rank of the weight matrix, σ s represents the sth singular value, W g represents the weight matrix of the g-th layer.

[0034] In an optional embodiment,

[0035] The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. The automatic chip overheating protection control is implemented according to the optimal chip protection strategy, including:

[0036] The global manager aggregates the temperature and power consumption information reported by each abnormal area, combines the power consumption and temperature distribution of the entire chip, generates a chip state feature matrix, generates an initial chip protection strategy based on the chip state feature matrix, and inputs the chip state feature matrix into a pre-trained graph neural network model to obtain temperature prediction values ​​for multiple future time steps;

[0037] Based on the obtained temperature prediction value, the potential high temperature abnormal area in the chip is identified by comprehensively considering the abnormal detection index of the temperature prediction value, the temperature change rate and the power consumption factor;

[0038] The initial chip protection strategy and the potential high-temperature abnormal area identification results are combined to model the chip overheating protection problem as a Markov decision process, wherein the state space includes the temperature, power consumption information and task allocation of each abnormal area, the action space includes regional frequency adjustment, power consumption budget allocation and task migration decision, and the reward function comprehensively considers the chip performance, power consumption and temperature indicators;

[0039] Based on the Markov decision process, a hybrid learning architecture combining a value function and a policy gradient is adopted to construct a chip protection strategy optimization model, wherein the input of the chip protection strategy optimization model is a chip state feature matrix, and the output is a value function or a policy function;

[0040] Construct a chip thermal simulation environment, use the finite element method to solve the heat conduction equation, simulate the thermal operation process of the chip, optimize the parameters of the chip protection strategy optimization model through the interaction between the intelligent agent and the chip thermal simulation environment, and introduce a greedy strategy in the training process to select the action that the current strategy considers to be optimal according to the preset probability to generate the optimal chip protection strategy;

[0041] According to the optimal chip protection strategy, the global manager controls the working status of the chip, including issuing frequency and voltage control instructions to each region, coordinating the operating system or runtime system to remap and schedule tasks, and adjusting the speed of the cooling fan or the flow of the liquid cooling pump to achieve automatic protection control of chip overheating.

[0042] In an optional embodiment,

[0043] The steps before inputting the chip state feature matrix into the pre-trained graph neural network model to obtain the temperature prediction values ​​for multiple future time steps also include:

[0044] The chip is divided into multiple thermal nodes, each thermal node corresponds to an area of ​​the chip, and there is a thermal coupling relationship between different thermal nodes;

[0045] Constructing a chip thermal conduction diagram, wherein the chip thermal conduction diagram has thermal nodes as nodes and thermal coupling relationships between thermal nodes as edges, the characteristics of each node include geometric parameters, material properties and power density properties of the node, and the characteristics of each edge are thermal conductivity between nodes;

[0046] Generate training samples by sampling from physical simulation or measured data, each training sample includes the temperature distribution, power distribution and heat dissipation conditions of each thermal node of the chip at a certain moment;

[0047] According to the training samples, a graph neural network model is trained, wherein the graph neural network model includes a plurality of graph convolutional layers and a fully connected layer, the hidden state of the node is updated through information aggregation and feature transformation, and the temperature is predicted using the updated hidden state of the node;

[0048] The trained graph neural network model is deployed to the chip's thermal management system, and the chip state feature matrix is ​​input to obtain the temperature prediction values ​​for multiple future time steps.

[0049] According to a second aspect of the embodiments of the present invention,

[0050] Provided is a chip overheating automatic protection control system, comprising:

[0051] The first unit is used to arrange distributed temperature sensors on the chip, obtain real-time temperature data of different areas inside the chip, transmit the temperature data through the on-chip interconnection network, and perform data aggregation and compression. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream;

[0052] The second unit is used to input the optimized temperature data stream into the pre-trained temperature anomaly detection model, detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area, trigger different intensities of thermal emergency processing according to the temperature anomaly level, and send the temperature and power consumption information of the abnormal area to the global manager;

[0053] The third unit is used by the global manager to summarize the temperature and power consumption information reported by each abnormal area, and generate an initial chip protection strategy based on the overall power consumption and temperature distribution of the chip. At the same time, it predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. According to the optimal chip protection strategy, automatic chip overheating protection control is implemented.

[0054] According to a third aspect of the embodiments of the present invention,

[0055] An electronic device is provided, comprising:

[0056] processor;

[0057] a memory for storing processor-executable instructions;

[0058] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0059] A fourth aspect of the embodiments of the present invention is:

[0060] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0061] In this embodiment, through distributed temperature sensors and data optimization, high-precision real-time temperature data of different areas inside the chip can be obtained. This provides a reliable basis for subsequent analysis and control. By using on-chip network transmission and data aggregation compression technology, a large amount of temperature data can be processed without significantly increasing the system burden. The data collection strategy is dynamically adjusted according to the spatiotemporal correlation of temperature changes, which can not only ensure the collection of key information, but also reduce system overhead. Using a pre-trained anomaly detection model, temperature anomalies can be quickly identified and anomaly levels can be given to provide a basis for timely intervention. Taking emergency measures of different intensities according to the anomaly level can effectively control the temperature and avoid the impact of excessive intervention on performance. The global manager comprehensively considers various factors, formulates the optimal chip protection strategy, and realizes coordinated control of the entire chip. By predicting future temperature trends, potential high-temperature areas can be identified in advance, preventive protection can be achieved, and the occurrence of temperature anomalies can be avoided. Through fine temperature management and optimized protection strategies, while ensuring chip reliability, the performance level of the chip is maintained as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic diagram of the process of the chip overheating automatic protection control method according to an embodiment of the present invention;

[0063] Figure 2 It is a schematic diagram of the structure of the chip overheating automatic protection control system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0065] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0066] Figure 1 FIG. 1 is a flow chart of a chip overheating automatic protection control method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0067] S101. Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip, transmit the temperature data through the on-chip interconnection network, and perform data aggregation and compression. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream.

[0068] For example, according to the functional division and thermal distribution characteristics of the chip, temperature sensors are arranged in different areas of the chip, focusing on monitoring high-power cores, hot spots and areas with drastic temperature changes. The temperature sensor uses a digital integrated temperature sensor and communicates with other modules through an on-chip interconnect network. The temperature sensor samples the real-time temperature data inside the chip at a certain frequency, transmits the temperature data through the on-chip interconnect network, sets a data aggregation node in the on-chip interconnect network, compresses and de-noises the temperature data, and reduces the data transmission load. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the data collection frequency and quantization accuracy of sensors in each area are dynamically adjusted to reduce the amount of data while ensuring data quality, thereby generating an optimized temperature data stream for subsequent anomaly detection and chip protection strategy generation.

[0069] In an optional embodiment,

[0070] Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip, including:

[0071] Discretize the chip plane into a set of grid cells, each grid cell represents a possible sensor placement position, and the sensor layout scheme is represented as a binary string, and the sensor layout problem is mathematically modeled and encoded;

[0072] According to the obtained grid cells, a plurality of initial sensor layout schemes are randomly generated as initial particles, where the position and velocity of each particle are represented by the corresponding binary string;

[0073] For the sensor layout scheme represented by each particle, the corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, a comprehensive objective function of each initial sensor layout scheme is constructed to evaluate the fitness of the particle. The prior rules of sensor layout constructed based on the power consumption distribution and hot spot distribution of the chip are used as constraints for the sensor layout problem.

[0074] According to the fitness evaluation results of the particles, the individual optimal position and the global optimal position of each particle are updated. The speed update formula is used to combine the current position, individual optimal position and global optimal position of each particle to update the speed of the particle at the next moment. According to the updated speed, the position of the particle is updated to generate a new sensor layout plan.

[0075] Based on the new sensor layout scheme, the Gaussian mutation operation is introduced, and the non-dominated sorting algorithm is used to screen the particles to obtain the updated particle swarm. The iteration is repeated until the maximum number of iterations is reached, and the sensor layout scheme represented by the global optimal particle is output as the optimal sensor layout scheme.

[0076] The optimal sensor layout scheme is mapped to the chip physical design, and the layout and interconnection topology of the sensor array are automatically generated. According to the obtained layout and interconnection topology of the sensor array, distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip.

[0077] Exemplarily, first, the chip plane is divided into a uniform rectangular grid, and each grid unit represents a possible sensor placement position. Then, the sensor layout scheme is represented by binary coding, where each bit of the binary string corresponds to a grid unit, 1 means that the sensor is placed at this position, and 0 means that it is not placed. In this way, the sensor layout problem is transformed into a binary optimization problem. According to the encoding method of the sensor layout problem, a group of initial particles are randomly generated, and each particle represents a possible sensor layout scheme. The position and speed of the particles are represented by the corresponding binary string. Parameters such as the size of the particle group, the initial speed range and position range of the particles are set.

[0078] For each sensor layout represented by a particle, the corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, a comprehensive objective function is constructed to evaluate the fitness of the particle. The comprehensive objective function considers multiple optimization goals such as the number of sensors, monitoring coverage, and hotspot detection sensitivity, and uses the prior rules constructed by chip power consumption distribution and hotspot distribution as constraints to adjust and penalize the fitness of the particle.

[0079] According to the fitness evaluation results of the particles, the individual optimal position and the global optimal position of each particle are updated. The speed update formula of the binary PSO algorithm is used to combine the current position of the particle, the individual optimal position and the global optimal position to calculate the speed of the particle at the next moment. According to the updated speed, the position of the particle is updated to generate a new sensor layout plan.

[0080] The particle swarm is optimized by evolutionary strategy, and Gaussian mutation and Cauchy mutation are introduced to perturb the position of particles, thereby improving the diversity and exploration ability of the particle swarm. According to the fitness evaluation results, the particle swarm is selected and updated by using methods such as non-dominated sorting and crowding calculation, eliminating particles with poor fitness and retaining excellent individuals.

[0081] Then determine whether the particle swarm meets the termination conditions, such as reaching the maximum number of iterations, fitness convergence, etc. If the termination conditions are met, the sensor layout solution represented by the global optimal particle is output as the optimal solution; otherwise, repeat the above steps to continue iterative optimization. Finally, the optimal sensor layout solution is post-processed, and the layout and interconnection topology of the sensor array are generated according to the layout solution to realize the physical layout and connection of the sensor on the chip.

[0082] In an optional embodiment,

[0083] The corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, the calculation formula for the comprehensive objective function of each initial sensor layout scheme is constructed as follows:

[0084] ;

[0085] Among them, J represents the comprehensive objective function, ω 1 represents the sensor weight, N represents the number of grid cells, and x i represents a binary variable, which determines whether a sensor is placed in the i-th grid cell in the sensor layout scheme. ω 2 represents the monitoring coverage weight, β represents the density coefficient, γ represents the exponential function attenuation parameter of the control distance, d(i, j) represents the distance between the i-th grid cell and the j-th grid cell, ω3 represents the sensitivity weight of hotspot detection, H represents the sample subset, T(i) represents the temperature parameter of grid cell i, λ represents the penalty coefficient, and P(x) represents the degree of violation of the prior rules by the layout scheme.

[0086] In this embodiment, the optimal sensor layout scheme that strikes a balance between coverage, accuracy and cost can be obtained through the particle swarm optimization algorithm and multi-objective optimization. The optimized sensor layout can achieve comprehensive temperature monitoring of key areas of the chip with a minimum number of sensors. By taking the chip power consumption distribution and hot spot distribution as constraints, the sensor layout can better adapt to the characteristics of a specific chip. By adjusting the comprehensive objective function, the accuracy, coverage and implementation cost of temperature monitoring can be flexibly balanced according to the needs of different application scenarios, which not only improves the efficiency and accuracy of chip temperature monitoring, but also provides strong support for the overall thermal management and reliability design of the chip.

[0087] S102. Input the optimized temperature data stream into the pre-trained temperature anomaly detection model, detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area, trigger thermal emergency processing of different intensities according to the temperature anomaly level, and send the temperature and power consumption information of the abnormal area to the global manager.

[0088] Among them, multiple temperature anomaly detection models can be trained offline based on machine learning methods. Each model corresponds to a typical application scenario and power consumption mode. When performing anomaly detection online, the most matching detection model is selected according to the current chip working state. Optionally, the optimized temperature data stream is input into the trained anomaly detection model in real time to monitor the temperature anomalies in various areas of the chip in real time. The anomaly detection model determines whether there is a temperature anomaly in each area based on the changing characteristics of the temperature data, and outputs the temperature anomaly level of the abnormal area. Different intensities of thermal emergency processing are triggered according to the temperature anomaly level, including dynamic migration of functional areas, local power consumption control, etc. The temperature and power consumption information of the abnormal area is sent to the global manager for subsequent chip protection strategy generation.

[0089] In an optional embodiment,

[0090] The optimized temperature data stream is input into the pre-trained temperature anomaly detection model to detect the temperature anomalies in each area of ​​the chip in real time. The steps before that also include:

[0091] A temperature anomaly detection model is constructed based on a long short-term memory neural network, wherein the temperature anomaly detection model includes an encoder and a decoder. The encoder maps the input temperature sequence to a latent space, and the decoder reconstructs the output temperature sequence from the latent space.

[0092] Acquire historical temperature data when the chip is working normally and perform preprocessing to obtain a normal temperature sequence data set, use the normal temperature sequence data set to pre-train the anomaly detection model, and obtain initial model parameters by minimizing the reconstruction error between the input temperature sequence and the reconstructed temperature sequence;

[0093] In each training iteration, a batch of normal samples are sampled from the normal temperature sequence data set, the normal samples are input into the current anomaly detection model, the gradient information of the samples is calculated, and the gradient information is used to add perturbations to the normal samples to obtain adversarial samples;

[0094] The normal samples and adversarial samples are combined to obtain comprehensive training samples, and the adversarial loss function on the comprehensive training samples is calculated. The gradient of the temperature anomaly detection model parameters is calculated according to the adversarial loss function using the stochastic gradient descent method, the initial model parameters are updated, and the iteration is repeated until the preset termination condition is met to obtain the final trained temperature anomaly detection model.

[0095] Exemplarily, a temperature anomaly detection model is constructed based on a long short-term memory neural network, wherein the temperature anomaly detection model includes two parts, an encoder and a decoder, wherein the encoder is constructed by first taking the input temperature sequence as the input of the LSTM neural network, setting the appropriate number of LSTM layers and hidden units to capture the timing information in the temperature sequence, and outputting the encoder's latent space representation as the decoder's input. Furthermore, when constructing the decoder, the encoder's latent space representation is taken as input, and it is mapped back to the form of the original temperature sequence through a reverse operation. The decoder can use an LSTM neural network or other model structures suitable for sequence reconstruction.

[0096] Collect historical temperature data when the chip is working normally, and ensure the accuracy and completeness of the data. Collect historical temperature data when the chip is working normally, and ensure the accuracy and completeness of the data. Use the preprocessed normal temperature sequence data set as training data to train the temperature anomaly detection model. Optimize the model parameters by minimizing the reconstruction error between the input temperature sequence and the reconstructed temperature sequence. The mean square error can be used as the loss function for training.

[0097] Furthermore, a batch of normal samples are randomly sampled from the normal temperature sequence data set as training samples, and these normal samples are input into the current anomaly detection model to calculate the gradient information of the samples, and the obtained gradient information is used to add perturbations to the normal samples to generate adversarial samples. The normal samples and adversarial samples are combined into comprehensive training samples to expand the training data set, and the adversarial loss function is calculated on the comprehensive training samples to measure the difference between normal samples and adversarial samples. Cross entropy loss or other related loss functions can be used. The adversarial loss function is calculated based on the comprehensive training samples, and the gradient of the temperature anomaly detection model parameters is calculated using the stochastic gradient descent method. The model parameters are updated according to the gradient, and the process is iterated repeatedly until the preset termination condition is met. After multiple iterative training, the final trained temperature anomaly detection model is obtained.

[0098] In an optional embodiment,

[0099] The normal sample and the adversarial sample are combined to obtain a comprehensive training sample, and the adversarial loss function on the comprehensive training sample is calculated, including:

[0100] The singular values ​​of the weight matrix are introduced as low-rank constraints, and the classification loss of normal samples and the classification loss of adversarial samples are combined to construct a joint adversarial loss function. The calculation formula is as follows:

[0101] ;

[0102] Among them, L represents the adversarial loss function, E n represents the expected value of normal samples, f(·) represents the discriminator function of the temperature anomaly detection model, and E a represents the expected value of the adversarial sample, x represents the normal sample, and x a represents the adversarial sample, ζ represents the weight coefficient of the low-rank constraint term, G represents the number of neural network layers, m g represents the rank of the weight matrix, σ s represents the sth singular value, W g represents the weight matrix of the g-th layer.

[0103] In this embodiment, by using long short-term memory neural network and adversarial training, the model can capture the complex time series characteristics of the temperature series and improve the accuracy of anomaly detection. Adversarial training enhances the robustness of the model to small disturbances by generating and using adversarial samples, reducing the possibility of false positives and false negatives. The model can learn from historical data of normal working conditions, adapt to the temperature characteristics and working mode of a specific chip, and can identify which specific areas or time points have abnormal temperature data, which helps to quickly locate the problem. It not only improves the accuracy and reliability of temperature anomaly detection, but also provides a powerful tool for dynamic thermal management and fault diagnosis of chips.

[0104] S103. The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, optimizes the initial chip protection strategy based on the prediction results, generates the optimal chip protection strategy, and implements automatic chip overheating protection control based on the optimal chip protection strategy.

[0105] The global manager is responsible for coordinating and managing the working status of the chip, including collecting the temperature and power consumption information reported by each abnormal area, and combining the overall power consumption and temperature distribution of the chip to generate the initial chip protection strategy, predict the future temperature change trend of the chip, and identify potential high temperature abnormal areas. Finally, the initial chip protection strategy is optimized based on the prediction results to generate the optimal chip protection strategy.

[0106] In an optional embodiment,

[0107] The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. The automatic chip overheating protection control is implemented according to the optimal chip protection strategy, including:

[0108] The global manager aggregates the temperature and power consumption information reported by each abnormal area, combines the power consumption and temperature distribution of the entire chip, generates a chip state feature matrix, generates an initial chip protection strategy based on the chip state feature matrix, and inputs the chip state feature matrix into a pre-trained graph neural network model to obtain temperature prediction values ​​for multiple future time steps;

[0109] Based on the obtained temperature prediction value, the potential high temperature abnormal area in the chip is identified by comprehensively considering the abnormal detection index of the temperature prediction value, the temperature change rate and the power consumption factor;

[0110] The initial chip protection strategy and the potential high-temperature abnormal area identification results are combined to model the chip overheating protection problem as a Markov decision process, wherein the state space includes the temperature, power consumption information and task allocation of each abnormal area, the action space includes regional frequency adjustment, power consumption budget allocation and task migration decision, and the reward function comprehensively considers the chip performance, power consumption and temperature indicators;

[0111] Based on the Markov decision process, a hybrid learning architecture combining a value function and a policy gradient is adopted to construct a chip protection strategy optimization model, wherein the input of the chip protection strategy optimization model is a chip state feature matrix, and the output is a value function or a policy function;

[0112] Construct a chip thermal simulation environment, use the finite element method to solve the heat conduction equation, simulate the thermal operation process of the chip, optimize the parameters of the chip protection strategy optimization model through the interaction between the intelligent agent and the chip thermal simulation environment, and introduce a greedy strategy in the training process to select the action that the current strategy considers to be optimal according to the preset probability to generate the optimal chip protection strategy;

[0113] According to the optimal chip protection strategy, the global manager controls the working status of the chip, including issuing frequency and voltage control instructions to each region, coordinating the operating system or runtime system to remap and schedule tasks, and adjusting the speed of the cooling fan or the flow of the liquid cooling pump to achieve automatic protection control of chip overheating.

[0114] Exemplarily, first, the global manager regularly receives the temperature and power consumption data reported by the abnormal area through the communication interface with each abnormal area. At the same time, the global manager also obtains the power consumption and temperature distribution information of the entire chip through the on-chip sensor network. The global manager summarizes the collected temperature and power consumption data of the abnormal area and the power consumption and temperature distribution data of the entire chip, extracts key features, and generates a feature matrix that represents the current chip state. Based on the generated chip state feature matrix, the global manager obtains the initial chip protection strategy through the preset strategy generation rules.

[0115] The global manager inputs the generated chip state feature matrix into the pre-trained graph neural network model. The graph neural network model predicts the temperature change trend of each area of ​​the chip in multiple future time steps by learning and reasoning about the chip state feature matrix, and outputs the future temperature prediction value. The global manager comprehensively considers the temperature prediction value, historical temperature change rate, and power consumption factors, and identifies the areas in the chip that may have high temperature anomalies through the designed anomaly detection indicators, marking them as potential high temperature anomaly areas.

[0116] Furthermore, the global manager combines the initial chip protection strategy with the identified potential high-temperature abnormal areas to establish a Markov decision process model. The state space of the Markov decision process model includes the temperature state, power consumption state and current task allocation of each abnormal area. The action space of the model includes the adjustment of the frequency of abnormal areas, the allocation of power consumption budgets and the decision of task migration. The design of the reward function comprehensively considers the chip's performance, power consumption and temperature indicators, aiming to guide the strategy optimization process to achieve a balance between chip overheating protection and performance.

[0117] Based on the constructed Markov decision process model, a deep reinforcement learning algorithm suitable for chip thermal management is designed to learn the optimal decision strategy through the interaction between the agent and the environment. The global manager adopts a hybrid learning architecture that combines value function and policy gradient to build a chip protection strategy optimization model. The chip protection strategy optimization model takes the chip state feature matrix as input, learns the mapping relationship from state to action through a neural network, and outputs a value function or a policy function.

[0118] The optimization model is trained through the interaction between the agent and the chip thermal simulation environment. The simulation environment uses the finite element method to solve the heat conduction equation and simulate the thermal operation process of the chip. The agent selects actions based on the current state and observes the next state and reward of the environment feedback, and optimizes the strategy through continuous exploration and utilization. A greedy strategy is also introduced in the training process to select the action that the current strategy considers to be the best with a certain probability, thereby improving the exploration efficiency of the strategy. After multiple rounds of training, the optimal chip protection strategy is obtained.

[0119] The global manager converts the optimal chip protection strategy obtained through optimization into specific control instructions and sends them to each area through the on-chip interconnect network. The control instructions include adjustments to regional frequency and voltage, decisions on task migration and remapping, etc. The global manager coordinates the operating system or runtime system to reschedule and map tasks based on task migration decisions. At the same time, the global manager also promotes heat dissipation of the chip by controlling the chip's cooling system, such as adjusting the speed of the cooling fan or the flow of the liquid cooling pump. Through the collaborative approach of software and hardware, the global manager dynamically regulates the working status of the chip according to the optimal chip protection strategy to achieve automatic protection of the chip from overheating.

[0120] In this embodiment, by summarizing the information of each region and combining it with the overall situation, global optimization is achieved in the true sense, avoiding the suboptimal solution that may be caused by local decision-making. The use of graph neural networks for temperature prediction enables the system to identify potential problems in advance and achieve preventive protection rather than passive response. By comprehensively considering the temperature prediction value, rate of change and power consumption factors, the accuracy and comprehensiveness of anomaly detection are improved. By using the thermal simulation environment, the strategy is optimized without affecting the actual chip, reducing the development and debugging costs. Through various means such as frequency adjustment, task migration and heat dissipation control, a flexible and comprehensive temperature management solution is provided. Through pre-trained models and optimized decision-making processes, real-time decisions can be made quickly to meet the needs of high-performance chips, and the power consumption budget can be dynamically adjusted according to the temperature conditions. While ensuring performance, the risk of overheating can be avoided, and the heat dissipation equipment can be accurately controlled to improve the heat dissipation efficiency. At the same time, unnecessary energy consumption is reduced, which not only greatly improves the thermal management capability and overall performance of the chip, but also lays the foundation for realizing a smarter and more efficient next-generation chip design.

[0121] In an optional embodiment,

[0122] The steps before inputting the chip state feature matrix into the pre-trained graph neural network model to obtain the temperature prediction values ​​for multiple future time steps also include:

[0123] The chip is divided into multiple thermal nodes, each thermal node corresponds to an area of ​​the chip, and there is a thermal coupling relationship between different thermal nodes;

[0124] Constructing a chip thermal conduction diagram, wherein the chip thermal conduction diagram has thermal nodes as nodes and thermal coupling relationships between thermal nodes as edges, the characteristics of each node include geometric parameters, material properties and power density properties of the node, and the characteristics of each edge are thermal conductivity between nodes;

[0125] Generate training samples by sampling from physical simulation or measured data, each training sample includes the temperature distribution, power distribution and heat dissipation conditions of each thermal node of the chip at a certain moment;

[0126] According to the training samples, a graph neural network model is trained, wherein the graph neural network model includes a plurality of graph convolutional layers and a fully connected layer, the hidden state of the node is updated through information aggregation and feature transformation, and the temperature is predicted using the updated hidden state of the node;

[0127] The trained graph neural network model is deployed to the chip's thermal management system, and the chip state feature matrix is ​​input to obtain the temperature prediction values ​​for multiple future time steps.

[0128] For example, the chip is divided into multiple thermal nodes according to the physical structure and functional modules of the chip. Each thermal node corresponds to an area on the chip, such as a processor core, memory, I / O interface, etc. There is a thermal coupling relationship between different thermal nodes, that is, the temperature change of one node will affect the temperature of the adjacent node. By dividing the chip into thermal nodes, a discrete model that can reflect the thermal conduction characteristics of the chip can be constructed.

[0129] Based on the division of thermal nodes, a chip thermal conduction graph is constructed. The chip thermal conduction graph is an undirected weighted graph, in which nodes represent thermal nodes and edges represent thermal coupling relationships between thermal nodes. The characteristics of each node include the node's geometric parameters (such as area, thickness), material properties (such as thermal conductivity, specific heat capacity), and power density properties (i.e., the power consumption of the node). The weight of each edge represents the thermal conductivity between adjacent nodes, and the thermal conductivity depends on the material properties and geometric dimensions between the nodes. Through the chip thermal conduction graph, the chip's thermal conduction problem can be transformed into an information transfer and update problem on the graph.

[0130] In order to train the graph neural network model, training samples need to be generated. Training samples can be obtained through physical simulation or measured data sampling. Each training sample represents the thermal state of the chip at a certain moment, including the temperature distribution of each thermal node, power distribution, and current heat dissipation conditions (such as ambient temperature and heat dissipation coefficient). By sampling at different times, a training data set covering different working states and environmental conditions can be obtained.

[0131] The graph neural network model is trained using the generated training samples. The graph neural network model consists of several graph convolutional layers and fully connected layers. The graph convolutional layer performs convolution operations on the chip heat conduction map and updates the hidden state of the node by aggregating the neighborhood information of the node. The fully connected layer maps the updated node hidden state to the temperature prediction value. During the forward propagation process, the model calculates the hidden state of the node based on the node features and edge weights at the current moment, and outputs the temperature prediction value. During the back propagation process, the model parameters are adjusted through optimization algorithms (such as Adam) to minimize the error between the predicted temperature and the actual temperature. After multiple rounds of iterative training, a graph neural network model that can accurately predict the chip temperature distribution is obtained.

[0132] The trained graph neural network model is deployed to the thermal management system of the chip. The thermal management system is responsible for collecting the power consumption and temperature data of the chip in real time and generating the chip state feature matrix. The chip state feature matrix is ​​input into the graph neural network model, and the model obtains the temperature prediction value for multiple future time steps through forward propagation calculation. The temperature prediction value indicates the temperature change trend of each thermal node in the future period of time under the current chip state. Based on the predicted temperature value, the thermal management system determines in advance whether an overheating problem will occur, and takes corresponding measures, such as adjusting power consumption allocation, task migration, etc., to prevent overheating failures.

[0133] In this embodiment, by modeling the chip as a heat conduction graph, the graph neural network can capture complex spatial thermal coupling relationships and achieve high-precision temperature distribution prediction. The representation method of the graph structure enables the model to adapt to various complex chip structures and layouts without redesigning the model architecture. By representing the thermal coupling relationship through edge features, the model can accurately simulate the conduction of heat between different areas of the chip and improve the prediction accuracy. The model can dynamically adjust the prediction results according to the chip state feature matrix input in real time to adapt to changes in the working state of the chip. By analyzing the critical paths in the heat conduction graph, the thermal bottlenecks in the chip can be identified to guide the heat dissipation design. Based on accurate temperature prediction, more sophisticated and dynamic thermal management strategies can be implemented, such as predictive frequency adjustment or task migration. Not only does it greatly improve the accuracy and efficiency of chip temperature prediction, but it also provides a powerful tool for implementing smarter and more sophisticated thermal management strategies.

[0134] Figure 2FIG. 1 is a schematic diagram of the structure of a chip overheating automatic protection control system according to an embodiment of the present invention. Figure 2 As shown, the system comprises:

[0135] The first unit is used to arrange distributed temperature sensors on the chip, obtain real-time temperature data of different areas inside the chip, transmit the temperature data through the on-chip interconnection network, and perform data aggregation and compression. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream;

[0136] The second unit is used to input the optimized temperature data stream into the pre-trained temperature anomaly detection model, detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area, trigger different intensities of thermal emergency processing according to the temperature anomaly level, and send the temperature and power consumption information of the abnormal area to the global manager;

[0137] The third unit is used by the global manager to summarize the temperature and power consumption information reported by each abnormal area, and generate an initial chip protection strategy based on the overall power consumption and temperature distribution of the chip. At the same time, it predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. According to the optimal chip protection strategy, automatic chip overheating protection control is implemented.

[0138] According to a third aspect of the embodiments of the present invention,

[0139] An electronic device is provided, comprising:

[0140] processor;

[0141] a memory for storing processor-executable instructions;

[0142] The processor is configured to call the instructions stored in the memory to execute the aforementioned method.

[0143] A fourth aspect of the embodiments of the present invention is:

[0144] A computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the aforementioned method is implemented.

[0145] The present invention may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present invention.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip overheating automatic protection control method, characterized in that: include: Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip. The temperature data is transmitted through the on-chip interconnection network, and the data is aggregated and compressed. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream. The optimized temperature data stream is input into the pre-trained temperature anomaly detection model to detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area. Different intensity thermal emergency processing is triggered according to the temperature anomaly level, and the temperature and power consumption information of the abnormal area is sent to the global manager. The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. Automatic chip overheating protection control is implemented based on the optimal chip protection strategy.

2. The method according to claim 1, characterized in that Distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip, including: Discretize the chip plane into a set of grid cells, each grid cell represents a possible sensor placement position, and the sensor layout scheme is represented as a binary string, and the sensor layout problem is mathematically modeled and encoded; According to the obtained grid cells, a plurality of initial sensor layout schemes are randomly generated as initial particles, where the position and velocity of each particle are represented by the corresponding binary string; For the sensor layout scheme represented by each particle, the corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, a comprehensive objective function of each initial sensor layout scheme is constructed to evaluate the fitness of the particle. The prior rules of sensor layout constructed based on the power consumption distribution and hot spot distribution of the chip are used as constraints for the sensor layout problem. According to the fitness evaluation results of the particles, the individual optimal position and the global optimal position of each particle are updated. The speed update formula is used to combine the current position, individual optimal position and global optimal position of each particle to update the speed of the particle at the next moment. According to the updated speed, the position of the particle is updated to generate a new sensor layout plan. Based on the new sensor layout scheme, Gaussian mutation operation is introduced, and the non-dominated sorting algorithm is used to screen particles to obtain an updated particle swarm. The iteration is repeated until the maximum number of iterations is reached, and the sensor layout scheme represented by the global optimal particle is output as the optimal sensor layout scheme. The optimal sensor layout scheme is mapped to the chip physical design, and the layout and interconnection topology of the sensor array are automatically generated. According to the obtained layout and interconnection topology of the sensor array, distributed temperature sensors are arranged on the chip to obtain real-time temperature data of different areas inside the chip.

3. The method according to claim 2, characterized in that The corresponding temperature monitoring data is obtained through chip thermal simulation. Based on the temperature monitoring data, the calculation formula for the comprehensive objective function of each initial sensor layout scheme is constructed as follows: ； Among them, J represents the comprehensive objective function, ω 1 represents the sensor weight, N represents the number of grid cells, and x i represents a binary variable, which determines whether a sensor is placed in the i-th grid cell in the sensor layout scheme. ω 2 represents the monitoring coverage weight, β represents the density coefficient, γ represents the exponential function attenuation parameter of the control distance, d(i, j) represents the distance between the i-th grid cell and the j-th grid cell, ω 3 represents the sensitivity weight of hotspot detection, H represents the sample subset, T(i) represents the temperature parameter of grid cell i, λ represents the penalty coefficient, and P(x) represents the degree of violation of the prior rules by the layout scheme.

4. The method according to claim 1, characterized in that: The optimized temperature data stream is input into the pre-trained temperature anomaly detection model to detect the temperature anomalies in each area of ​​the chip in real time. The steps before that also include: A temperature anomaly detection model is constructed based on a long short-term memory neural network, wherein the temperature anomaly detection model includes an encoder and a decoder. The encoder maps the input temperature sequence to a latent space, and the decoder reconstructs the output temperature sequence from the latent space. Acquire historical temperature data when the chip is working normally and perform preprocessing to obtain a normal temperature sequence data set, use the normal temperature sequence data set to pre-train the anomaly detection model, and obtain initial model parameters by minimizing the reconstruction error between the input temperature sequence and the reconstructed temperature sequence; In each training iteration, a batch of normal samples are sampled from the normal temperature sequence data set, the normal samples are input into the current anomaly detection model, the gradient information of the samples is calculated, and the gradient information is used to add perturbations to the normal samples to obtain adversarial samples; The normal samples and adversarial samples are combined to obtain comprehensive training samples, and the adversarial loss function on the comprehensive training samples is calculated. The gradient of the temperature anomaly detection model parameters is calculated according to the adversarial loss function using the stochastic gradient descent method, the initial model parameters are updated, and the iteration is repeated until the preset termination condition is met to obtain the final trained temperature anomaly detection model.

5. The method according to claim 4, characterized in that The normal sample and the adversarial sample are combined to obtain a comprehensive training sample, and the adversarial loss function on the comprehensive training sample is calculated, including: The singular values ​​of the weight matrix are introduced as low-rank constraints, and the classification loss of normal samples and the classification loss of adversarial samples are combined to construct a joint adversarial loss function. The calculation formula is as follows: ； Among them, L represents the adversarial loss function, E n represents the expected value of normal samples, f(·) represents the discriminator function of the temperature anomaly detection model, and E a represents the expected value of the adversarial sample, x represents the normal sample, and x a represents the adversarial sample, ζ represents the weight coefficient of the low-rank constraint term, G represents the number of neural network layers, m g represents the rank of the weight matrix, σ s represents the sth singular value, W g represents the weight matrix of the g-th layer.

6. The method according to claim 1, characterized in that The global manager summarizes the temperature and power consumption information reported by each abnormal area, combines the overall power consumption and temperature distribution of the chip, generates an initial chip protection strategy, and predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. The automatic chip overheating protection control is implemented according to the optimal chip protection strategy, including: The global manager aggregates the temperature and power consumption information reported by each abnormal area, combines the power consumption and temperature distribution of the entire chip, generates a chip state feature matrix, generates an initial chip protection strategy based on the chip state feature matrix, and inputs the chip state feature matrix into a pre-trained graph neural network model to obtain temperature prediction values ​​for multiple future time steps; Based on the obtained temperature prediction value, the potential high temperature abnormal area in the chip is identified by comprehensively considering the abnormal detection index of the temperature prediction value, the temperature change rate and the power consumption factor; The initial chip protection strategy and the potential high-temperature abnormal area identification results are combined to model the chip overheating protection problem as a Markov decision process, wherein the state space includes the temperature, power consumption information and task allocation of each abnormal area, the action space includes regional frequency adjustment, power consumption budget allocation and task migration decision, and the reward function comprehensively considers the chip performance, power consumption and temperature indicators; Based on the Markov decision process, a hybrid learning architecture combining a value function and a policy gradient is adopted to construct a chip protection strategy optimization model, wherein the input of the chip protection strategy optimization model is a chip state feature matrix, and the output is a value function or a policy function; Construct a chip thermal simulation environment, use the finite element method to solve the heat conduction equation, simulate the thermal operation process of the chip, optimize the parameters of the chip protection strategy optimization model through the interaction between the intelligent agent and the chip thermal simulation environment, and introduce a greedy strategy in the training process to select the action that the current strategy considers to be optimal according to the preset probability to generate the optimal chip protection strategy; According to the optimal chip protection strategy, the global manager controls the working status of the chip, including issuing frequency and voltage control instructions to each region, coordinating the operating system or runtime system to remap and schedule tasks, and adjusting the speed of the cooling fan or the flow of the liquid cooling pump to achieve automatic protection control of chip overheating.

7. The method according to claim 6, characterized in that The steps before inputting the chip state feature matrix into the pre-trained graph neural network model to obtain the temperature prediction values ​​for multiple future time steps also include: The chip is divided into multiple thermal nodes, each thermal node corresponds to an area of ​​the chip, and there is a thermal coupling relationship between different thermal nodes; Constructing a chip thermal conduction diagram, wherein the chip thermal conduction diagram has thermal nodes as nodes and thermal coupling relationships between thermal nodes as edges, the characteristics of each node include geometric parameters, material properties and power density properties of the node, and the characteristics of each edge are thermal conductivity between nodes; Generate training samples by sampling from physical simulation or measured data, each training sample includes the temperature distribution, power distribution and heat dissipation conditions of each thermal node of the chip at a certain moment; According to the training samples, a graph neural network model is trained, wherein the graph neural network model includes a plurality of graph convolutional layers and a fully connected layer, the hidden state of the node is updated through information aggregation and feature transformation, and the temperature is predicted using the updated hidden state of the node; The trained graph neural network model is deployed to the chip's thermal management system, and the chip state feature matrix is ​​input to obtain the temperature prediction values ​​for multiple future time steps.

8. A chip overheating automatic protection control system, used to implement the method described in any one of claims 1 to 7, characterized in that: include: The first unit is used to arrange distributed temperature sensors on the chip, obtain real-time temperature data of different areas inside the chip, transmit the temperature data through the on-chip interconnection network, and perform data aggregation and compression. According to the spatiotemporal correlation of temperature changes in different areas inside the chip, the frequency and accuracy of data collection are dynamically adjusted to generate an optimized temperature data stream; The second unit is used to input the optimized temperature data stream into the pre-trained temperature anomaly detection model, detect the temperature anomaly of each area in the chip in real time, and output the temperature anomaly level of the abnormal area, trigger different intensities of thermal emergency processing according to the temperature anomaly level, and send the temperature and power consumption information of the abnormal area to the global manager; The third unit is used by the global manager to summarize the temperature and power consumption information reported by each abnormal area, and generate an initial chip protection strategy based on the overall power consumption and temperature distribution of the chip. At the same time, it predicts the future temperature change trend of the chip, identifies potential high-temperature abnormal areas, and optimizes the initial chip protection strategy based on the prediction results to generate the optimal chip protection strategy. According to the optimal chip protection strategy, automatic chip overheating protection control is implemented.

9. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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