Hybrid metallization surface for integrated circuit package

Abstract

The invention relates to a hybrid metallized surface for integrated circuit package. The IC die package has a hybrid metallization surface. The wiring metallization features have a lower surface roughness to reduce high frequency signal transmission losses, while the IC die attachment metallization features have a higher surface roughness to achieve greater adhesion. The wiring feature and the die attach feature may be formed within the same package metallization level, for example, using a plating process. The insulator material may be formed over the surface of the metallization feature, for example, using a dry film lamination process. Optionally, an interface material may be deposited on at least the wiring feature to enhance adhesion of the insulator material to the low roughness metallized surface. An opening may be formed in the insulator material to expose a surface of the die attachment feature. The exposed surface may be selectively roughened and an IC die attached to the roughened surface.

Description

Background Art

[0001] In electronics manufacturing, integrated circuit (IC) packaging is a stage of manufacturing in which an IC, which has been fabricated on a die or chip comprising semiconductor material, is coupled to a supporting housing or "package" that protects the IC from physical damage and supports electrical contacts suitable for further connection to a host component such as a printed circuit board (PCB).

[0002] Next generation multi-chip packages (MCPs) require greater interconnect density to support evolving decentralized IC system-level packaging and / or bandwidth-intensive applications. In high-bandwidth architectures, for example, multiple IC dies or chips assembled on a package may need to be electrically interconnected by a fine wiring layer, which includes wires (i.e., traces) embedded in the interconnect level of the package at a density of at least 250 traces / mm. Higher speed I / O data transmission is also important for next generation interconnects (e.g., SERDES) that will exceed 28GHz. This interconnection needs to operate with low signal loss. At higher frequencies, signal transmission becomes more sensitive to the surface of interconnect metallization features (e.g., wires or traces), a phenomenon known as the "skin effect", for example, at a 1MHz signal transmission frequency, the skin depth is about 66μm. However, at 28GHz, the skin depth is about 400nm.

[0003] For the package substrate, the demand for greater interconnect trace density coupled with the demand for reduced trace roughness requires new solutions and / or architectures to replace conventional approaches, which have proven to be limited to lower line metallization densities and signal transmission frequencies. For MCP, the IC die can be attached to the package substrate including metallization traces, for example, via a die backside film (DBF). The challenge of reducing trace roughness can conflict with such a die attach process, resulting in an expensive process that can increase the cost of the packaged device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The subject matter described herein is illustrated in the accompanying drawings by way of example, and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. The views referred to as "sections," "profiles," and "plans" correspond to orthogonal planes within a Cartesian coordinate system. Thus, sectional views and profile views are taken in the xz plane, and plan views are taken in the xy plane. Typically, profile views in the xz plane are sectional views. Where appropriate, the drawings are labeled with axes to indicate the orientation of the drawings. In addition, where deemed appropriate, reference numerals are repeated between the drawings to indicate corresponding or similar elements. In the drawings:

[0005] Figure 1 is a flow chart illustrating a method of manufacturing an IC device package including hybrid metallization features having different surface roughnesses according to some embodiments;

[0006] Figure 2A , 3A , 3A, 4A, 5A, and 6A illustrate cross-sectional views through an IC device package when performing selected operations of an IC device package manufacturing process according to some embodiments;

[0007] Figure 2B , 3B , 3B, 4B, 5B, and 6B illustrate cross-sectional views through an IC device package while performing selected operations of an IC device package manufacturing process according to some alternative embodiments;

[0008] Figure 7 A system including an MCP having hybrid metallization features for interconnecting IC dies is shown according to some embodiments;

[0009] Figure 8 A mobile computing platform and a data server machine employing package routing with hybrid metallization surfaces according to an embodiment are shown; and

[0010] Fig. 9 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0011] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the present specification. It will be apparent to those skilled in the relevant art that the techniques and / or arrangements described herein can be employed in a variety of other systems and applications in addition to the systems and applications described in detail herein.

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and illustrate exemplary embodiments. In addition, it should be understood that other embodiments may be utilized and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references (e.g., up, down, top, bottom, etc.) may be used only to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description should not be construed as having a limiting meaning, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0013] In the following description, many details are set forth. However, it will be apparent to those skilled in the art that embodiments may be implemented without these specific details. In some cases, known methods and apparatus are shown in block diagram form rather than in detail to avoid making the embodiments difficult to understand. References throughout this specification to "embodiment" or "one embodiment" or "some embodiments" indicate that specific features, structures, functions or characteristics described in conjunction with the embodiment are included in at least one embodiment. Therefore, the phrases "in an embodiment" or "in an embodiment" or "some embodiments" that appear in various locations throughout this specification do not necessarily refer to the same embodiment. In addition, specific features, structures, functions or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment may be combined with the second embodiment, as long as the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0014] As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that, as used herein, the term "and / or" refers to and encompasses all possible combinations of one or more of the associated listed items.

[0015] The terms "coupled" and "connected" and their derivatives may be used in this article to describe the functional or structural relationship between components. These terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" may be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other intermediate elements between them) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., such as having a causal relationship).

[0016] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer above or below another material or layer may be in direct contact, or may have one or more intervening materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. Conversely, a first material or layer "above" a second material or layer is in direct physical contact with the second material / layer. In the context of component assembly, a similar distinction would be made.

[0017] As used throughout this specification and claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0018] Figure 1 is a flow chart showing a method 100 for manufacturing an IC device package to include metallization features having a mixed surface. According to method 100, within a metallization level, some metallization features (e.g., wiring) have a low surface roughness, while other metallization features (e.g., die attach pads) have a high surface roughness. Metallization features having a low surface roughness (e.g., an average roughness of <30 nm) ensure low insertion loss for transmitting high frequency (e.g., 28 GHz) data signals. Metallization features having a high surface roughness (e.g., an average roughness of >50 nm) ensure strong adhesion, for example, to an IC die attached to the metallization features. As further described below, in some embodiments where a package insulator material (e.g., an organic dielectric material) may suffer from delamination from a metallization feature having a low surface roughness, an interface material (e.g., an inorganic dielectric material) may be formed on the metallization feature having a low surface roughness before forming the package insulator material. In some additional embodiments also described below, interface material may not be present in high surface roughness metallization features where the interface material is unnecessary or detrimental.

[0019] Method 100 utilizes semi-additive processing (SAP) technology. According to some embodiments, the wiring metallization features may include wires or traces that interconnect multiple IC dies assembled together with the package. The wiring metallization features may be electrically insulated from each other and from adjacent die attachment features using one or more insulator materials (e.g., organic dielectric buildup materials). Although such materials generally adhere poorly to metallization features with low surface roughness, adding an intermediate layer of interface material can mitigate the risk of package film delamination. In the case of low surface roughness, the wire metallization portion manufactured according to method 100 can transmit high-frequency data signals with greater integrity. Therefore, IC device package manufacturing method 100 can be advantageous for 2D, 2.5D, and 3D MCP packages.

[0020] The hybrid metallization surface manufactured according to method 100 can include a die attach metallization surface that is treated (e.g., mechanically or chemically) to have a high surface roughness. Advantageously, one or more treatments are selectively performed on the die attach features while protecting the wiring metallization features from the treatments, for example, by an overlying package insulator that can be retained as a permanent packaging film. In the absence of any roughening treatment of the wiring metallization, an interface material suitable for forming a strong bond with the insulator material can be deposited to improve adhesion of the wiring metallization to the package insulator material.

[0021] Method 100 may be repeated any number of times to build up an interconnect structure including any number of levels of metallization features including multiple material layers. Figure 2A-6A A cross-sectional view through a first exemplary IC device package is shown while executing blocks in method 100 in accordance with some embodiments. Figure 2B-6B A cross-sectional view through a second exemplary IC device package is shown while executing blocks in method 100 according to some alternative embodiments. Figure 2A-6A and Figure 2B-6B In the embodiment of the present invention, an exemplary metallization structure is shown on the "die side" of the IC device package. However, the same treatment can be implemented on the "land-side" of the IC device package. Therefore, the treatment can be symmetrical or asymmetrical on both the die side and the land side of the IC device package.

[0022] First reference Figure 1, method 100 begins at input 105, wherein a workpiece including a packaging substrate suitable for SAP is manufactured or received as a preform. The packaging substrate manufactured or received at input 105 can have any architecture, as the embodiments are not limited in this context. Typically, the packaging substrate includes at least some electrically insulating (i.e., insulator) material, and may also include one or more metallization levels embedded in the insulator. Each metallization level may include any number of substantially coplanar metallization features. In some embodiments, the workpiece manufactured or received at input 105 is substantially planar and is made to have specific dimensions in thickness and lateral area to serve as a suitable support to facilitate panelized processing of multiple packages (i.e., WLP) arranged above the substrate. As further described below, the substrate may include one or more material layers. The various material layers of the substrate may be retained in the final singulated package, or separated from the final package as part of a sacrificial carrier.

[0023] The package substrate manufactured or received at input 105 may be "core" or "coreless". In the absence of a core, the package substrate may rely on a sacrificial carrier to mechanically support the package build-up material. Method 100 continues at block 110 where both signal transmission traces and IC die attach features (e.g., "pads") are formed within a single (same) metallization level. The die attach features are used to provide lands to which the IC die will subsequently be attached.

[0024] exist Figure 2A In the example further shown in FIG. 1 , package substrate 200A includes a “core” 201. Core 201 may be any preform comprising any material having sufficient mechanical rigidity and / or stiffness to serve as a platform for stacking package wiring metallization levels. Single-sided stacking may be performed on the front (die) side of core 201, or as Figure 2A As shown by the ellipse in , double-sided build-up can be performed simultaneously on the front (die) side and the back (pad) side of the core 201 .

[0025] The package metallization features are embedded within one or more layers of package insulator material 205. In some exemplary embodiments, the package insulator material 205 comprises an organic dielectric material (e.g., comprising one or more polymers). In some embodiments, the package insulator material 205 comprises an epoxy resin, a phenolic glass or resin film (e.g., a GX-series film commercially available from Ajinomoto Fine-Techno Co., Inc.), which can be advantageously applied as a dry film laminate. Exemplary epoxy resins include acrylates of phenolic resins (e.g., epoxy phenol novolac (EPN) or epoxy cresol novolac (ECN)). In some specific examples, the package insulator material 205 is a bisphenol-A epoxy resin, for example, including epichlorohydrin. In other examples, the package insulator material 205 includes a bisphenol F epoxy resin (with epichlorohydrin). In other examples, encapsulating insulator material 205 includes an aliphatic epoxy resin, which may be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butanediol diglycidyl ether), or have a higher functionality (e.g., trimethylolpropane triglycidyl ether). In other examples, encapsulating insulator material 205 includes a glycidylamine epoxy resin, such as triglycidyl-p-aminophenol (functionality 3) and N,N,N',N'-tetraglycidyl-bis-(4-aminophenyl)-methane (functionality 4). Although such polymeric materials may decompose at high processing temperatures (eg, >400° C.), these materials may offer many of the advantages associated with SAP technology.

[0026] In the package substrate 200A, each metallization level 202, 203 includes a line metallization feature 206. Between the two nearest metallization levels, the routing metallization includes a via metallization feature 208, for example, coupling the line metallization features of different levels. In the upper metallization level 203, the line metallization feature 206 can have any minimum lateral dimension CD L , but in some exemplary embodiments with a line density of at least 250 traces / mm at the line metallization level, CD LThe lower metallization level 202 may have a different (eg, lower) line density than the upper metallization level 202 .

[0027] For highest line density, the line metallization features 206 are advantageously protected from dimensional loss during, for example, seed layer patterning and / or other processing performed in preparation for depositing an insulator material layer on the exposed surfaces of the line metallization features 206. Figure 2A In the expanded view of , the line metallization 206 is shown as having a low average roughness Ra1 at least on the top (die side) surface 215. In an exemplary embodiment, the average roughness Ra1 is less than 100nm, advantageously less than 50nm, and more advantageously less than 30nm. As used herein, the average roughness (or centerline average) is as described in ASME B46.1. The average roughness is the arithmetic mean of the absolute values ​​of the profile height deviation (profile height deviation) relative to the average line recorded for the evaluation length. The average roughness can be measured, for example, using a profiler including a stylus rotating on the surface. For a line metallization 206 having a longitudinal length in a first dimension (e.g., coinciding with the y-axis), the average roughness can be measured at a distance of approximately 60-70% of the longitudinal line length while remaining near the centerline of the transverse width (transverse width) of the line metallization 206, and the transverse width is a dimension substantially orthogonal to the first dimension (e.g., coinciding with the x-axis).

[0028] In some embodiments, all wiring features within the package have substantially the same low surface roughness. In other embodiments, one or more metallization levels within the package have a low surface roughness, while one or more other metallization levels within the package have a higher surface roughness. In the package substrate 200A, for example, within the lower line metallization level 202, the line metallization feature 206 has a higher average surface roughness Ra2. In the case where the line metallization level does not transmit high-frequency (e.g., more than 1 GHz) data signals but includes power wiring, a higher surface roughness is allowable. Although the average surface roughness Ra2 may vary with the implementation, in some examples, it exceeds 50nm and can be 100nm or greater.

[0029] Within the package metallization level 203, in addition to the line metallization features 206, there are IC die attach metallization features 207. The die attach metallization features 207 are substantially coplanar with the line metallization features 206. The die attach metallization features 207 can have substantially the same composition as the line metallization features 206, and are advantageously manufactured simultaneously with the line metallization features within the same metallization level. The die attach metallization features 207 can therefore also have a low surface roughness (e.g., average roughness Ra1). The die attach metallization features 207 can be referred to as die attach "pads" because they typically have a rectangular footprint (e.g., in the xy plane) and have a size significantly larger than the minimum line dimension CD L Minimum horizontal dimension CD DAP Although the die attach metallization feature 207 may have any lateral dimensions sufficient to accommodate any large or small IC die, in an exemplary embodiment, the die attach pad dimension CD DAP At least 1 mm and may be 10 mm or greater. For the die attach pad 207, the die attach pad 207 may be extended in a first dimension (eg, coincident with the y-axis) over a length CD while remaining near the centerline of the width of the die attach pad 207. DAP The average roughness is measured over a distance of approximately 60-70% of the width in a dimension substantially orthogonal to the first dimension (eg, coinciding with the x-axis).

[0030] For example, the line metallization features 206 and the die attach metallization features 207 (and the via metallization features 208) may be formed using an additive or semi-additive process. In some embodiments, the line metallization features 206 and the die attach metallization features 207 include one or more layers that are primarily copper. For example, the line metallization features 206 and the die attach metallization features 207 may include a first Cu layer that may be deposited using a first deposition process (e.g., sputtering, chemical plating, etc.), and a second Cu layer that may be deposited using a second deposition process (e.g., electrolytic plating). Thus, the first Cu layer may act as a seed layer. Since such material layers are primarily Cu, Figure 2A The separated layers are not shown.

[0031] Back to Figure 1 , method 100 proceeds to an optional block where an interface material is deposited over at least the trace or line metallization feature. The interface material may, for example, be formed directly on at least the top surface of the metallization feature. The interface material may have any composition suitable for promoting adhesion of a subsequently deposited encapsulating insulator material; otherwise, the encapsulating insulator material may suffer from low adhesion to the metallization surface of low average roughness.

[0032] In some exemplary embodiments, block 115 includes deposition of an inorganic dielectric material. Such deposition may include one or more of a sputtering (physical vapor deposition) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, etc. For low temperature (e.g., <250° C.) embodiments where the underlying package insulator includes organic materials that may decompose at higher temperatures, which is advantageous, PVD is performed at block 115.

[0033] In other embodiments, block 115 includes nitrogen treating (i.e., nitriding) the metallized feature surface to introduce nitrogen into the exposed surface or into a non-zero surface layer thickness. Through the treatment, the nitrogen can advantageously react with one or more metals present at the surface of the metallized feature to form a metal nitride compound. For example, in some embodiments where the metallized feature primarily comprises copper, a copper nitride compound such as Cu3N is formed on the exposed surface of the metallized feature. In some embodiments, the nitrogen treatment comprises plasma nitridation, wherein a precursor gas comprising nitrogen is energized, for example, using an RF or microwave power source (e.g., a generator, a magnetron, etc.), thereby obtaining a plasma. In an exemplary embodiment, the precursor gas is NH3. Other precursors (e.g., but not limited to N2O or N2) are also possible.

[0034] Figure 2B An exemplary package substrate 200B is shown, which has a package substrate 200A ( Figure 2A ) and add interface material 209. Interface material 209 is in direct contact with at least the top surface 215 of the metallization features within metallization level 203. Interface material 209 may, for example, only be present within the metallization level of the package that includes metallization features with low surface roughness. Figure 2B 2, the interface material 209 is not present in the metallization level 202. The interface material 209 is in direct contact with the surface of the package insulator material 205. In the example shown, the interface material 209 spans the space between the wire metallization feature 206 and the die attach metallization feature 207. The presence of the interface material 209 on the underlying insulator material 205 indicates that the interface material 209 has been deposited, for example, by PVD, as opposed to being a product of a chemical reaction with the metallization features 206, 207 (in which case the interface material 209 is present only where the underlying metallization is present).

[0035] exist Figure 2BIn the example of , the interface material 209 is asymmetrically deposited on one side of the core 201. However, in alternative embodiments, the interface material 209 may also be deposited on both sides of the core 201. As shown, the interface material 209 is located on both the top surface 215 and the sidewall surface 216 of the line metallization feature 206 and the tube die attachment metallization feature 207. The interface material 209 has a non-zero thickness T1, which is advantageously less than 1μm, more advantageously less than 100nm, and may be as thin as 2-10nm. It is worth noting that the interface material 209 need not be a continuous film as shown, but can be discontinuous, for example having islands and / or pinholes of material that have not been fully coalesced into a continuous film layer. In Figure 2B In one embodiment, the interface material 209 is substantially conformal, wherein the thickness T1 is substantially the same between the top surface 215 and the sidewall surface 216. Alternatively, the interface material 209 may alternatively be non-conformal, wherein the thickness T1 on the top surface 215 is significantly greater than the thickness T1 on the sidewall surface 216 (e.g., as measured in a direction perpendicular to the sidewall surface 216).

[0036] In an exemplary embodiment, the interface material 209 is an inorganic dielectric material, although organic dielectrics are also possible. In some embodiments, the interface material 209 is an inorganic dielectric material that includes nitrogen. In other embodiments, the interface material 209 also includes silicon, and can be, for example, primarily silicon and nitrogen (e.g., SiN). In other embodiments where the interface material 209 is a reaction product of metallization features, the interface material 209 can again include nitrogen and one or more metals (e.g., Cu) present within the in-line metallization features 206 and the die attach metallization features 207. In addition to nitrogen, the interface material 209 can also include other components, such as oxygen and / or carbon. In some embodiments, the interface material 209 is SiON, SiO, or SiCN, which can be deposited, for example, by PVD.

[0037] return Figure 1 , method 100 continues at box 120, where a packaging insulator material is formed over the metallization features and openings are formed in the insulator to expose the die attach features. In an exemplary embodiment, an organic dielectric material (e.g., any of the materials described above as suitable packaging insulator materials) can be applied by liquid dispensing followed by a curing process, or applied, for example, as a dry film laminate. Additional metallization levels and insulator materials can be formed before forming openings or cavities to expose the die attach features below. Then, openings or cavities are formed through one or more layers of insulator material to expose the die attach metallization in preparation for IC die assembly. Depending on the composition of the insulator material and the size of the cavity to be formed, the packaging insulator material can be mechanically drilled, laser ablated, or etched using a wet or dry (plasma) etching process.

[0038] exist Figure 3A In the embodiment further shown in FIG. 1 , a die cavity 305 has been formed within the insulator material 205, for example using a laser ablation process. The cavity 305 is made to have specific dimensions to accommodate the subsequent attachment of the IC die to the die attach metallization feature 207, with a central portion 315 exposed at the bottom of the cavity 305. In the exemplary embodiment, the cavity 305 has a lateral minimum dimension CD C , the minimum horizontal dimension CD C Small enough to be smaller than the horizontal pad size CD DAP to ensure that the insulator material 205 remains over the peripheral portion 316 of the die attach metallization feature 307 surrounding the central portion 315 .

[0039] Figure 3B Exemplary embodiments including interface material 209 are shown, which are advantageous in situations where without the interface material the insulator material 205 would have poor adhesion to the metallization line features 206 and / or the die attach metallization features 207. Where the insulator material 205 is in contact with the interface material 209, greater chemical bonding may occur at the interface of the two materials. Figure 3B As further shown in FIG. 3 , the interface material 209 may be removed during the formation of the cavity 305 such that no interface material 209 remains on the central die attach metallization portion 315. For example, the laser ablation process may be non-selective to the interface material 209, and / or the interface material 209 may not have a sufficient thickness to withstand any process employed in the formation of the cavity 305. Removing the interface material 209 from within the cavity 305 may be advantageous, for example, in instances where the interface material 209 is not suitable for die attach. For embodiments where the interface material 209 would be suitable for die attach, the removal of the interface material 209 may simply be an incidental artifact of forming the cavity 305.

[0040] return Figure 1 , method 100 continues at block 125, where the exposed surface of the die attach metallization feature is roughened by one or more chemical and / or mechanical processes. In some exemplary embodiments, a wet chemical etch is performed at block 125. For example, where the die attach metallization feature is primarily Cu, a Cu etchant solution may be introduced to the exposed surface. The etchant solution increases the surface roughness, for example, by a factor of 2-5 or more. In alternative embodiments, an ion milling or sputtering process may be implemented to similarly increase the surface roughness.

[0041] exist Figure 4AIn the example shown, the central portion 315 of the die attach metallization feature 207 exposed in the cavity 305 is roughened to have a surface roughness (e.g., average roughness Ra3) that is greater than the surface roughness of the peripheral portion 316 and the surface roughness of the line metallization feature 206, and the peripheral portion 316 and the line metallization feature 206 both retain their initial surface roughness (e.g., average roughness Ra1). In an exemplary embodiment, the average roughness Ra3 is greater than 50nm, advantageously greater than 100nm, and can be 200nm or greater. Therefore, in some specific embodiments, when the average roughness Ra1 is less than 50nm (e.g., 30nm or less), the average roughness Ra3 is greater than 50nm (e.g., 70nm or more).

[0042] exist Figure 4B In the example shown, the central portion 315 of the die attach metallization feature 207 exposed within the cavity 305 has been similarly roughened to a surface roughness (e.g., average roughness Ra3) greater than the surface roughness of the peripheral portion 316, which retains the initial surface roughness and remains covered by the interface material 209. Therefore, the average roughness Ra3 is also greater than the average roughness Ra1 of the line metallization feature 206.

[0043] Method 100( Figure 1 ) continues at block 130, where one or more IC dies are attached to one or more die attach features. The IC dies may be attached one-to-one to corresponding die attach features, or may be attached in a many-to-one architecture, as the embodiments are not limited in this context. The die attach performed at block 130 may require any technique known to be suitable. In some exemplary embodiments, block 130 includes attaching an IC die having a die attach film (DAF) adhered to a surface of the IC die. The DAF is used to provide an adhesive bond to the surface of the die attach metallization feature of the package substrate.

[0044] exist Figure 5A and Figure 5B In the example shown, the DAF 503 is adhered to the back side of the IC die 501 and can therefore be referred to as a DBF. The device (front) side 502 of the IC die 501 faces the opposite package substrate 200A, 200B. The IC die 501 is positioned within the cavity 305, and the DAF 503 is in direct contact with the central portion 315 of the die attach metallization feature 207 exposed within the cavity 305. The DAF 503 can be any adhesive film known to be suitable for IC die attach.

[0045] In some exemplary embodiments, IC die 501 is a "passive" die and does not have any FETs fabricated within the device layers near device side 502. Such a passive die may include only interconnect wiring levels. These interconnect wiring levels may, for example, transmit electrical communication signals between other IC dies, and are therefore referred to as "bridge" dies.

[0046] Alternatively, IC die 501 may be an "active" die that includes FETs fabricated within a device layer near device side 502. For either passive or active embodiments, IC die 501 may include devices such as resistors, capacitors, or inductors (not shown). IC die 501 may be a full-featured ASIC, or may be a chiplet or tile with more limited functionality that supplements the functionality of one or more other IC dies within a multi-chip package. The chiplet or tile may be, for example, any of a radio circuit, a microprocessor core, an electronic memory circuit, a floating point gate array (FPGA), a power management and / or power supply circuit, or include a MEMS device. For active embodiments, IC die 501 may include any of a microprocessor circuit unit, a graphics processing circuit unit, or a heterogeneous processing circuit unit, etc. The microprocessor circuit unit may be operable, for example, to execute a real-time operating system (RTOS). In some further embodiments, IC die 501 is operable to execute one or more layers of a software stack that controls radio (wireless) functions. In other embodiments, IC die 501 includes electronic memory circuitry such as, but not limited to, dynamic random access memory (DRAM).

[0047] Back to Figure 1 , method 100 continues at box 135, where additional packaging insulator material is applied over one or more IC dies attached at box 130 and over adjacent portions of the packaging substrate. The insulator material can then be planarized, and any number of additional metallization levels can be stacked to complete the packaging structure at output 190. Any of the above-described processes and materials can be deposited or otherwise applied to further stack the packaging substrate to prepare for assembly of one or more IC dies. For an exemplary multi-chip package embodiment, one or more additional IC dies are attached to the packaging substrate to complete the packaging structure. The additional IC dies can be interconnected to other IC dies, for example, via wiring metallization of the packaging substrate. The first side of the completed packaging metallization structure can be interconnected to any number of IC dies. The second side of the packaging substrate can be interconnected to any suitable host component.

[0048] Fig. 6A and Figure 6BIC device package structures 600A and 600B are shown, respectively. The package insulator material 205 has been planarized over the front side IC die surface 502, and surface via metallization features 601 contact the interconnect interface of the IC die 501. Other surface via metallization features 601 are coupled to package wiring metallization that can, for example, carry power and / or data signals to the opposite (landing pad) side of the package structures 600A, 600B.

[0049] IC die 610 and IC die 611 are attached to surface via metallization features 601, for example, by direct bonding or solder interconnection (not shown). IC die 610 and 611 are shown in a flip-chip configuration, wherein device side 602 faces package substrate 200A, 200B. However, IC die 610 and 611 may alternatively be in a back-to-back orientation, wherein through-die vias (not shown) are coupled to surface via metallization features 601. Each of IC die 610 and IC die 611 may be a passive die or an active die, the active die including a FET fabricated within a device layer proximate device side 602. For active IC die embodiments, IC die 610, 611 may each be a fully functional ASIC, or may each be a die or chip with more limited functionality that supplements the functionality of one or more other IC dies within a multi-chip package. For active IC die embodiments, each of IC die 610, 611 may include any of a microprocessor circuit unit, a graphics processing circuit unit, or a heterogeneous processing circuit unit, etc. In some exemplary embodiments, IC die 501 is a bridge die having routing metallization that electrically interconnects the I / O of IC die 610 to the I / O of IC die 611. For some such embodiments, IC die 610 is operable to execute one or more layers of a software stack that controls radio (wireless) functions, while IC die 611 includes electronic memory circuit units, such as, but not limited to, DRAM.

[0050] Figure 7A system 700 is shown according to some embodiments, which includes an IC device package structure 600B that interconnects two IC dies 610 and 611 (chips or core particles) to each other through a third IC die 501. The system 700 may similarly include an IC device package structure 600A. The package structure 600B is coupled to a host component 740. The host component 740 can be a PCB or an interposer attached to a package metallization portion by any suitable interconnect 745 (e.g., solder). In some exemplary embodiments, the connection pad side of the host component 740 opposite the package structure 600B is further processed to receive a second-level interconnect 720 (e.g., solder). The system 700 may also include one or more of an overmold (not shown), a heat sink (not shown), and / or an active cooling structure (not shown).

[0051] Figure 8 A mobile computing platform and a data server machine are shown that employ an IC package with a hybrid metallized surface, for example, as described elsewhere herein. The server machine 806 can be any commercial server, for example, including any number of high-performance computing platforms that are arranged in a rack and networked together for electronic data processing, and in an exemplary embodiment, the server machine 806 includes an MCP. The mobile computing platform 805 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. For example, the mobile computing platform 805 can be any of a tablet computer, a smart phone, a laptop computer, etc., and can include a display screen (e.g., a capacitive, inductive, resistive, or optical touch screen), a chip-level or package-level integrated system 810, and a battery 815.

[0052] As a system component within a server machine 806, the package structure 700 includes a memory IC (e.g., RAM) die 802 and a processor IC (e.g., a microprocessor, a multi-core microprocessor, a baseband processor, etc.) die 801, which are interconnected by package wiring 830, which has a mixture of high surface roughness and low surface roughness in one metallization level, such as substantially as described elsewhere herein. One or more other IC dies may also be assembled with the package structure 700. For example, an RF (wireless) integrated circuit (RFIC) 825 including a broadband RF (wireless) transmitter and / or receiver (TX / RX) may be further interconnected to the package structure 700. Functionally, the RFIC 825 can have an output coupled to an antenna to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher generations.

[0053] Fig. 9 is a block diagram of a cryogenically cooled computing device 900 according to some embodiments. For example, one or more components of computing device 900 may include any of the devices or structures discussed elsewhere herein. Fig. 9 900, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some of the components included in the computing device 900 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various of these components may be fabricated onto a single system-on-chip (SoC) die, or may be implemented as multiple chips or slices that are broken out and packaged together. Additionally, in various embodiments, the computing device 900 may not include a processor or a processor. Fig. 9 , but the computing device 900 may include an interface circuit unit for coupling to one or more components. For example, the computing device 900 may not include the display device 903, but may include a display device interface circuit unit (e.g., a connector and a driver circuit unit) to which the display device 903 can be coupled.

[0054] The computing device 900 may include a processing device 901 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may indicate a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 901 may include a memory 921, a communication device 922, a refrigeration / active cooling device 923, a battery / power conditioning device 924, a logic unit 925, an interconnect 926, a thermal conditioning device 927, and a hardware security device 928.

[0055] Processing device 901 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices.

[0056] The computing device 900 may include a memory 902, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the processing device 901 shares a package with the memory 902. The memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0057] The computing device 900 may include a thermal conditioning / cooling device 906. The thermal conditioning / cooling device 906 may maintain the processing device 901 (and / or other components of the computing device 900) at a predetermined low temperature during operation. The predetermined low temperature may be any temperature discussed elsewhere herein.

[0058] In some embodiments, the computing device 900 may include a communication chip 907 (e.g., one or more communication chips). For example, the communication chip 907 may be configured to manage wireless communications to transmit data to and from the computing device 900. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data by using modulated electromagnetic radiation through a non-solid medium.

[0059] The communication chip 907 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 revision)), Long Term Evolution (LTE) project and any revisions, updates and / or amendments (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband wireless access (BWA) networks compatible with IEEE 802.16 are generally referred to as WiMAX networks, which is an acronym standing for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the conformance and interoperability tests of the IEEE 802.16 standard. The communication chip 907 can operate according to the Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 907 can operate according to Enhanced Data Rates for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 907 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivatives, and any other wireless protocols named 3G, 4G, 5G and higher generations. In other embodiments, the communication chip 907 can operate according to other wireless protocols. The computing device 900 may include an antenna 913 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0060] In some embodiments, the communication chip 907 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 907 can include multiple communication chips. For example, the first communication chip 907 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and the second communication chip 907 can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 907 can be dedicated to wireless communications, and the second communication chip 907 can be dedicated to wired communications.

[0061] The computing device 900 may include a battery / power supply circuit unit 908. The battery / power supply circuit unit 908 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit units for coupling components of the computing device 900 to an energy source separate from the computing device 900 (e.g., AC line power).

[0062] Computing device 900 may include display device 903 (or corresponding interface circuitry, as described above). Display device 903 may include any visual indicator, such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0063] Computing device 900 may include audio output device 904 (or corresponding interface circuitry, as described above). Audio output device 904 may include any device that generates audible indications, such as, for example, a speaker, headphones, or earbuds.

[0064] Computing device 900 may include audio input device 910 (or corresponding interface circuitry, as described above). Audio input device 910 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0065] Computing device 900 may include a global positioning system (GPS) device 909 (or corresponding interface circuitry, as described above). GPS device 909 may communicate with a satellite-based system and may receive the location of computing device 900, as is known in the art.

[0066] The computing device 900 may include another output device 905 (or corresponding interface circuitry, as described above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to another device, or an additional storage device.

[0067] The computing device 900 may include another input device 911 (or a corresponding interface circuit unit, as described above). Examples may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0068] Computing device 900 may include security interface device 912. Security interface device 912 may include any device that provides security measures for computing device 900, such as intrusion detection, biometric authentication, security encoding or decoding, management access lists, malware detection, or spyware detection.

[0069] The computing device 900 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0070] Although certain features set forth herein have been described with reference to various embodiments, this description is not intended to be interpreted as having a limiting meaning. Therefore, various modifications and other embodiments of the embodiments described herein that are obvious to those skilled in the art to which the present disclosure belongs are considered to fall within the spirit and scope of the present disclosure.

[0071] In a first example, an integrated circuit (IC) device package includes a substrate including one or more metallization levels. One of the metallization levels includes a metallization line having a top surface with a first roughness and a metallization pad having a top surface with a second roughness greater than the first roughness. An IC die is coupled to the top surface of the metallization pad, and an insulator material is above the top surface of the metallization line.

[0072] In a second example, for any of the first examples, a top surface of the metallization line has an average roughness below 100 nm, and a top surface of the metallization pad has an average roughness at least twice the average roughness of the top surface of the metallization line.

[0073] In a third example, for any of the first to second examples, the average roughness is the arithmetic mean of the absolute values ​​of the profile height deviations from the average line recorded for the evaluation length of the top surface.

[0074] In a fourth example, for any of the third examples, the metallization line has a longitudinal length in a first dimension, and the average roughness is measured over a distance of at least 60% of the longitudinal length.

[0075] In a fifth example, for any of the first to fourth examples, the insulator material is above a perimeter of the metallization pad and laterally adjacent to a top surface having the second roughness, and the perimeter of the metallization pad includes a top surface less than the second roughness.

[0076] In a sixth example, for any of the fifth examples, a top surface of a perimeter of the metallization pad has the first roughness.

[0077] In a seventh example, for any of the first to sixth examples, the insulator material is an organic dielectric material comprising one or more organic polymers, and the IC device package further comprises an interface material layer between the top surface of the metallization line and the organic dielectric material, and wherein the interface material layer is not present between the metallization pad and the IC die.

[0078] In an eighth example, for any of the seventh examples, the interface material layer is an inorganic dielectric material.

[0079] In a ninth example, for any of the eighth examples, the metallization line and the metallization pad include primarily Cu, the inorganic dielectric material includes nitrogen, and the inorganic dielectric material is in direct contact with the metallization line.

[0080] In a tenth example, for any of the seventh to ninth examples, the organic dielectric material is above a perimeter of the metallization pad and adjacent to the top surface having the second roughness. The interface material layer is in contact with the perimeter of the metallization pad.

[0081] In an eleventh example, a system includes a first integrated circuit (IC) die, a second IC die, and a third IC die, the third IC die being below at least one of the first IC die or the second IC die and including a first side interconnected to both the first IC die and the second IC die. The third IC die includes a second side opposite the first side, the second side being attached to a top surface of a metallization pad. The metallization pad is substantially coplanar with an adjacent metallization line, the top surface of the metallization line having a first roughness, and the top surface of the metallization pad having a second roughness greater than the first roughness.

[0082] In a twelfth example, for any of the eleventh examples, a top surface of the metallization line has an average roughness below 30 nm, and a top surface of the metallization pad has an average roughness above 50 nm.

[0083] In a thirteenth example, for any of the eleventh to twelfth examples, the third IC die electrically interconnects the first IC die to the second IC die, and an organic dielectric material is between a top surface of the metallization line and at least one of the first IC die or the second IC die.

[0084] In a fourteenth example, for any of the thirteenth examples, the organic dielectric material is above the perimeter of the metallization pad and adjacent to the top surface having the second roughness; and wherein the perimeter of the metallization pad includes the top surface having the first roughness.

[0085] In a fifteenth example, for any of the thirteenth to fourteenth examples, the system further includes an interface material layer between a top surface of the metallization line and the organic dielectric material, wherein the interface material layer is not present between the metallization pad and the IC die.

[0086] In a sixteenth example, for any of the fifteenth examples, the interface material layer consists essentially of silicon and nitrogen.

[0087] In a seventeenth example, a method of manufacturing an integrated circuit (IC) device package, the method comprising receiving a substrate comprising a metallization level, the metallization level comprising a metallization pad having a first top surface having a first roughness and a metallization line having a second top surface having substantially the first roughness laterally adjacent to the metallization pad. The method comprises depositing an insulator material over the metallization level. The method comprises exposing a portion of the first top surface by forming an opening through the insulator material while maintaining the insulator material over the second top surface. The method comprises roughening the portion of the first top surface to a second roughness, and attaching an IC die to the portion of the first top surface after the roughening.

[0088] In an eighteenth example, for any of the seventeenth examples, a side of the IC die is in contact with a die attach film (DAF), and attaching the IC die includes contacting the DAF with the portion of the first top surface.

[0089] In a nineteenth example, for any of the seventeenth to eighteenth examples, the insulator material is an organic dielectric material including one or more organic polymers. The method further includes depositing an interface material layer over the metallization level before depositing the organic dielectric material.

[0090] In a twentieth example, for any of the nineteenth examples, depositing the interface material layer includes physical vapor deposition of an inorganic dielectric material including nitrogen.

[0091] It should be recognized that the principles of the present disclosure are not limited to the embodiments described above, but can be implemented through modification and change without departing from the scope of the appended claims. The above-mentioned embodiments may include only a subset of these features, a different order of these features, a different combination of these features, and / or additional features other than those explicitly listed. Therefore, the scope of the embodiments should be determined by reference to the appended claims and the full scope of equivalents to which these claims are entitled.

Claims

1. An integrated circuit (IC) device package, comprising: A substrate comprising one or more metallization levels, wherein one of the metallization levels comprises: a metallization line having a top surface with a first roughness; and a metallized pad having a top surface having a second roughness greater than the first roughness; an IC die coupled to the top surface of the metallization pad; and An insulator material is above the top surface of the metallization line.

2. The IC device package according to claim 1, wherein: The top surface of the metallization line has an average roughness below 100 nm; and The top surface of the metallization pad has an average roughness that is at least twice the average roughness of the top surface of the metallization line.

3. The IC device package according to claim 2, wherein: The mean roughness is the arithmetic mean of the absolute values ​​of the profile height deviations from the mean line recorded for the evaluation length of the top surface.

4. The IC device package according to any one of claims 2 to 3, wherein: The metallization line has a longitudinal length in a first dimension; and The average roughness is measured over a distance of at least 60% of said longitudinal length.

5. The IC device package according to any one of claims 1 to 3, wherein: the insulator material being over a perimeter of the metallization pad and laterally adjacent the top surface having the second roughness; and The perimeter of the metallization pad includes a top surface that is less than the second roughness.

6. The IC device package according to claim 5, wherein: The top surface of the perimeter of the metallization pad has the first roughness.

7. The IC device package according to any one of claims 1 to 3, wherein: The insulator material is an organic dielectric material including one or more organic polymers, and the IC device package also includes an interface material layer between the top surface of the metallization line and the organic dielectric material, and wherein the interface material layer does not exist between the metallization pad and the IC die.

8. The IC device package according to claim 7, wherein: The interface material layer is an inorganic dielectric material.

9. The IC device package according to claim 8, wherein: The metallization line and the metallization pad each mainly include Cu, the inorganic dielectric material includes nitrogen, and the inorganic dielectric material is in direct contact with the metallization line.

10. The IC device package according to any one of claims 7 to 9, wherein: the organic dielectric material being over a perimeter of the metallization pad and adjacent the top surface having the second roughness; And wherein the interface material layer contacts the periphery of the metallization pad.

11. A system comprising: a first integrated circuit (IC) die; A second IC die; as well as a third IC die below at least one of the first IC die or the second IC die and including a first side interconnected to both the first IC die and the second IC die, and a second side opposite the first side, the second side attached to a top surface of a metallized pad, wherein: The metallization pad is substantially coplanar with an adjacent metallization line, the top surface of the metallization line having a first roughness; and The top surface of the metallization pad has a second roughness greater than the first roughness.

12. The system of claim 11, wherein: The top surface of the metallization line has an average roughness below 30 nm; and The top surface of the metallization pad has an average roughness exceeding 50 nm.

13. The system according to any one of claims 11-12, wherein: The third IC die electrically interconnects the first IC die to the second IC die; and An organic dielectric material is between the top surface of the metallization line and at least one of the first IC die or the second IC die.

14. The system according to claim 13, wherein: The organic dielectric material is over a perimeter of the metallization pad and adjacent to the top surface having the second roughness; and wherein the perimeter of the metallization pad includes a top surface having the first roughness.

15. The system of claim 13, further comprising a layer of interface material between the top surface of the metallization line and the organic dielectric material, wherein The interface material layer is not present between the metallization pads and the IC die.

16. The system of claim 15, wherein: The interface material layer mainly includes silicon and nitrogen.

17. A method of manufacturing an integrated circuit (IC) device package, the method comprising: receiving a substrate including a metallization level including a metallization pad having a first top surface having a first roughness and a metallization line laterally adjacent to the metallization pad having a second top surface having substantially the first roughness; depositing an insulator material over the metallization level; exposing a portion of the first top surface by forming an opening through the insulator material while maintaining the insulator material above the second top surface; roughening the portion of the first top surface to a second roughness; as well as An IC die is attached to the portion of the first top surface after the roughening.

18. The method according to claim 17, wherein: A side of the IC die is in contact with a die attach film (DAF), and attaching the IC die includes contacting the DAF with the portion of the first top surface.

19. The method according to any one of claims 17-18, wherein: The insulator material is an organic dielectric material comprising one or more organic polymers, and wherein the method further comprises depositing an interface material layer over the metallization level prior to depositing the organic dielectric material.

20. The method according to claim 19, wherein: Depositing the interface material layer includes physical vapor deposition of an inorganic dielectric material including nitrogen.

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