Image sensor and manufacturing method thereof

Abstract

The invention discloses an image sensor and a manufacturing method thereof. The image sensor comprises a substrate, a global shutter assembly, a grounding doped region and a shading layer. The substrate is at least provided with a pixel array area and a boundary area which are adjacent. The global shutter component is located in the pixel array region, wherein the global shutter component comprises a storage node. The grounding doped region is located in the boundary region. The light shielding layer is located on the pixel array area and the boundary area and electrically connected to the grounding doping area, the light shielding layer comprises a first light shielding layer and a second light shielding layer, the first light shielding layer is located on the pixel array area and covers the storage node, and the second light shielding layer is located on the boundary area and surrounds the global shutter assembly.

Description

Technical Field

[0001] The present invention relates to a sensor and a manufacturing method thereof, and in particular to an image sensor and a manufacturing method thereof. Background Art

[0002] The rolling shutter image sensor commonly used at present uses a method of sequentially reading signals. Therefore, the time difference in reading the signals can easily cause image deformation, such as blur, distortion and shaking, and thus image distortion occurs. Therefore, global shutter image sensing technology is gradually being used to replace it.

[0003] Furthermore, the global shutter image sensor has a storage node that can be used as a signal temporary storage area to reduce the image distortion caused by the aforementioned time difference. However, since the storage node is more easily affected by light and has a high parasitic light sensitivity problem, how to improve the aforementioned problem is indeed a challenge. Summary of the invention

[0004] The invention provides an image sensor and a manufacturing method thereof, which can effectively reduce the parasitic light sensitivity of the image sensor.

[0005] The image sensor of the present invention comprises a substrate, a global shutter component, a ground doped region and a light shielding layer. The substrate has at least an adjacent pixel array region and a boundary region. The global shutter component is located in the pixel array region, wherein the global shutter component includes a storage node. The ground doped region is located in the boundary region. The light shielding layer is located on the pixel array region and the boundary region and is electrically connected to the ground doped region, wherein the light shielding layer comprises a first light shielding layer and a second light shielding layer, wherein the first light shielding layer is on the pixel array region and covers the storage node, and the second light shielding layer is on the boundary region and surrounds the global shutter component.

[0006] The image sensor of the present invention comprises at least the following steps: providing a substrate, wherein the substrate has at least adjacent pixel array regions and boundary regions; forming a global shutter component in the pixel array region, wherein the global shutter component comprises a storage node; forming a grounding doping region in the boundary region; forming an annular groove in the boundary region to surround the global shutter component, wherein the annular groove exposes the grounding doping region; and forming a light shielding layer in the pixel array region and the boundary region and electrically connected to the grounding doping region, wherein the light shielding layer comprises a first light shielding layer and a second light shielding layer, wherein the first light shielding layer covers the storage node, and at least a portion of the second light shielding layer fills the annular groove.

[0007] Based on the above, the light shielding layer on the pixel array area of ​​the image sensor of the present invention blocks the light coming from above, and the light shielding layer on the boundary area blocks the stray light coming from the side. In this way, the light incident on the storage node area can be significantly reduced, and the parasitic light sensitivity caused by it can be effectively reduced.

[0008] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a partial top view schematic diagram of an image sensor according to an embodiment of the present invention;

[0010] Figure 2 yes Figure 1 A partial three-dimensional schematic diagram of an image sensor according to an embodiment of the present invention, showing an intermediate structure formed to a light shielding layer;

[0011] Figures 3A to 3G The present invention is Figure 1 A partial cross-sectional schematic diagram of a manufacturing step of an embodiment of a section line AA';

[0012] 4A to 4H The present invention is Figure 1 A partial cross-sectional schematic diagram of another embodiment of the manufacturing steps along the section line AA';

[0013] Figure 5 FIG. 4 is a schematic diagram of a partial manufacturing process of an image sensor according to an embodiment of the present invention.

[0014] Explanation of symbols

[0015] 10: Solid frame line

[0016] 20: Dashed line

[0017] 101: Gap wall

[0018] 102: Etching stop layer

[0019] 103, 104: dielectric layer

[0020] 103t, 104t, 160t1, 160t2, 170t, 260t1, 260t2, 270t: top surface

[0021] 105, 106, 107, 108: patterned photoresist

[0022] 100, 200: Image sensor

[0023] 110: Base

[0024] 120: Global shutter assembly

[0025] 121: Photoelectric components

[0026] 121a, 123a: N-type doping region

[0027] 122, 124, 126, 142: Gate

[0028] 123: Storage Node

[0029] 125: Dynamic diffusion zone

[0030] 127, 141: doping area

[0031] 130: ground doping region

[0032] 140: Peripheral circuit components

[0033] 150, 170, 270: Contacts

[0034] 160a, 160b: light shielding material

[0035] 180:Internal connection structure

[0036] LS, 160, 260: light shielding layer

[0037] C1, C2: annular groove

[0038] D1: Depth direction

[0039] D2: Width direction

[0040] L / E: Light incident / electrical connection part

[0041] M1, M2: circuit layer

[0042] MV: Interconnect Layer

[0043] RA: Pixel Array Area

[0044] RB: Border zone

[0045] RC: Surrounding area

[0046] S100, S200, S300, S400, S500: Steps

[0047] SL: Stray Light

[0048] V11, V21, V22: contact through-hole DETAILED DESCRIPTION

[0049] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the accompanying drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one.

[0050] The directional terms used herein (eg, up, down, right, left, front, back, top, bottom) are used only with reference to the drawings shown and are not intended to imply an absolute orientation.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

[0052] Figure 1 FIG. 4 is a partial top view of an image sensor according to an embodiment of the present invention. Figure 2 yes Figure 1 A partial three-dimensional schematic diagram of an image sensor according to an embodiment of the present invention shows an intermediate structure formed to a light shielding layer. Figures 3A to 3G The present invention is Figure 1 A partial cross-sectional schematic diagram of a manufacturing step of an embodiment of the section line AA'. 4A to 4H The present invention is Figure 1 A partial cross-sectional schematic diagram of the manufacturing steps of another embodiment of the section line AA'.

[0053] It should be noted that Figure 2 The intermediate structure of the image sensor can have at least two implementation modes in the vertical cross section, such as Figure 3E The intermediate structure of the image sensor 100 or Figure 4C The intermediate structure of the image sensor 200 is shown in FIG. 1 , and the manufacturing steps of the image sensor 100 will be described first, and then the manufacturing steps of the image sensor 200 will be described. The structures and manufacturing methods of the image sensor 100 and the image sensor 200 described in this document all belong to the protection scope of the present invention.

[0054] Please refer to Figure 1 and Figure 3A , providing a substrate 110, wherein the substrate 110, for example, has a pixel array region RA, a boundary region RB, and a peripheral region RP. Further, the pixel array region RA is adjacent to the boundary region RB, and the boundary region RB is between the pixel array region RA and the peripheral region RP, and the pixel array region RA, the boundary region RB, and the peripheral region RP can be arranged in sequence from the center of the substrate 110 toward the outside, but the present invention is not limited thereto.

[0055] Next, a global shutter assembly 120 is formed in the pixel array region RA, a ground doping region 130 is formed in the boundary region RB, and a peripheral circuit element 140 is formed in the peripheral region RP. Here, the present invention does not limit the order of forming the components in the above-mentioned regions, and the order of forming the components in the above-mentioned regions can be determined according to actual design requirements.

[0056] In the present embodiment, the global shutter element 120 includes a photodiode 121, a gate 122, a storage node 123, a gate 124 and a floating diffusion region 125, wherein the aforementioned components are arranged in sequence toward the boundary region RB, so that the gate 122 is located between the photodiode 121 and the storage node 123, and the gate 124 is located between the storage node 123 and the floating diffusion region 125, so as to achieve the operations of collecting photons through the photodiode 121, opening the channel (as a transfer gate) through the gate 122, so that the photons are transmitted to the storage node 123, and when necessary, the gate 124 is used to open the channel (as a transfer gate) so that the signal is transmitted to the floating diffusion region 125, etc. Here, the photodiode 121, the storage node 123 and the floating diffusion region 125 can be located in the substrate 110, and the gates 122 and 124 can be located on the surface of the substrate 110.

[0057] In this embodiment, the global shutter assembly 120 further includes: Figure 3A The gate 126 and the doped region 127 configured in the solid frame line 10 provide functions such as transistors. Therefore, after the corresponding potential changes with the amount of signal absorbed by the floating diffusion region 125, it can be connected to the metal oxide semiconductor field effect transistor (MOSFET) composed of the gate 126 and the doped region 127 to read the corresponding signal, thereby allowing the global shutter component 120 to operate effectively.

[0058] It should be noted that the components in the solid frame 10 are optional configurations, and other suitable components and configurations may be used according to actual design requirements, and the circuit layers thereon (such as Figure 3G The arrangement of the circuit layers M1, M2, etc.) can also be adjusted according to the actual design requirements. In addition, the drawings of the present invention only schematically illustrate the global shutter assembly 120 at the edge of the pixel array area RA, that is, Figure 1 A plurality of groups of global shutter components 120 may be arranged on the pixel array area RA, and each group of global shutter components 120 may be regarded as a pixel.

[0059] In addition, the peripheral circuit element 140 of the peripheral region RP may include a doped region 141 (such as serving as a source / drain) and a gate 142 within the substrate 110, and a plurality of isolation structures 110a may be formed within the substrate 110 to define a plurality of active (active) regions on the substrate 110, such as defining an active region of the global shutter component 120, an active region of the ground doped region 130, and an active region of the peripheral circuit element 140, wherein the isolation structure 110a is, for example, a shallow trench isolation (STI) structure, and the peripheral circuit element 140 may be a logic circuit or other suitable peripheral circuit element, which is not limited by the present invention.

[0060] In some embodiments, the substrate 110 is a semiconductor substrate (such as a silicon substrate) and may have a doping type different from that of the photoelectric element 121, the storage node 123, the floating diffusion 125, the doping regions 127, 141 and the ground doping region 130 to form corresponding components. For example, the substrate 110 is a P-type doped substrate 110, the photoelectric element 121 may be a photodiode formed by the N-type doping region 121a and the P-type doped substrate 110, the storage node 123 may be a PN diode formed by the N-type doping region 123a and the P-type doping substrate 110, and the floating diffusion 125 is an N-type doping region. On the other hand, the doping region 127, the ground doping region 130 and the doping region 141 may also be N-type doping regions, but the present invention is not limited thereto. Here, the above-mentioned doping regions are formed by, for example, using an ion implantation method with suitable dopants, and may be selectively heavily doped regions (P+ or N+).

[0061] In some embodiments, the gates 122, 124, 126, 142 may be made by doping polysilicon or the like using a chemical vapor deposition process, a physical vapor deposition process or the like), a photolithography process, and an etching process, but the present invention is not limited thereto. The gates 122, 124, 126, 142 may also be formed using other suitable materials and processes.

[0062] Please continue to refer to Figure 3A After forming the gates 122, 124, 126, 142, a spacer 101 may be formed on the sidewalls of the gates 122, 124, 126, 142, wherein in the present embodiment, the spacer 101 may be a single-layer structure, but the present invention is not limited thereto, and in an embodiment not shown, the spacer may also be a multi-layer structure. Here, the material of the spacer 101 is, for example, silicon oxide, silicon nitride, or a combination thereof, and the formation method thereof may be to conformally form a spacer material layer (not shown) on the gate, and then perform a manufacturing process such as etching the spacer material layer, but the present invention is not limited thereto.

[0063] In addition, after forming the spacer 101, an etch stop layer (CESL) 102 may be formed on the entire substrate 110. For example, the etch stop layer 102 may be formed on the pixel array region RA, the boundary region RB, and the peripheral region RP and cover the top surfaces of the gates 122, 124, 126, 142 and the spacer 101. The etch stop layer 102 of the present embodiment may be a single-layer structure formed using, for example, silicon nitride. However, the present invention is not limited thereto. The etch stop layer 102 may also be a multi-layer structure in which silicon oxide and silicon nitride are sequentially deposited on the substrate 110.

[0064] Next, a dielectric layer 103 is formed on the substrate 110. For example, the dielectric layer 103 can be directly formed on the etching stop layer 102 in the pixel array region RA, the boundary region RB, and the peripheral region RP. The material of the dielectric layer 103 can include silicon oxide or a similar dielectric material and can be formed by deposition or a similar manufacturing process. Here, the dielectric layer 103 can be referred to as a first dielectric layer.

[0065] Then, using the patterned photoresist as a mask (not shown), a portion of the dielectric layer 103 on the optoelectronic device 121 is removed (for example, by an etching process) to form a plurality of contact holes V11, wherein the contact holes V11 may expose the etching stop layer 102, that is, the bottom surface of the contact holes V11 may be coplanar with the top surface of the etching stop layer 102, but the present invention is not limited thereto. In an embodiment not shown, the contact holes may be formed in the dielectric layer without exposing the top surface of the etching stop layer, that is, the bottom surface of the contact holes may be higher than the top surface of the etching stop layer 102. Here, the etching stop layer 102 may prevent the surface of the substrate 110 from being damaged in the process of forming the contact holes V11 by the etching process, and the aforementioned patterned photoresist may be referred to as a first patterned photoresist, and the contact holes V11 may be referred to as first contact holes.

[0066] Please refer to Figure 3A and Figure 3B , a light shielding material 160a is deposited in the contact hole V11 and extends to the top surface 103t of the dielectric layer 103 to form a plurality of contacts 150 in the contact hole V11, and a partial light shielding layer 160 (such as Figure 3B ), wherein the light shielding material 160a on the pixel array region RA may cover the storage node 123 to block light incident from above to the storage node 123. Here, tungsten (W) or other suitable light shielding materials may be formed by deposition or other suitable manufacturing processes, and the light shielding material 160a may be referred to as a first light shielding material, and the contact 150 may be referred to as a first contact.

[0067] In some embodiments, the light shielding material 160a may be first filled into the contact through hole V11 and formed completely on the substrate 110, and then a photolithography patterning process is used to form a plurality of openings, wherein the plurality of openings may correspond to Figure 2 The light incident / electrical connection portion L / E on the pixel array area RA, for example, the light incident portion of the light incident / electrical connection portion L / E may correspond to the photoelectric element 121, and the electrical connection portion of the light incident / electrical connection portion L / E may correspond to the gates 122, 124, 126, 142, but the present invention is not limited thereto. It should be noted that, Figure 2 The light incident / electrical connection portion L / E is only shown schematically and is not based on Figure 3B Draw it according to the size of the opening.

[0068] In this embodiment, part of the shading material 160a can be extended from the top surface 103t of the dielectric layer 103 in the pixel array area RA to the top surface 103t of the dielectric layer 103 in the boundary area RB, and the contact 150 can be physically connected to the shading material 160a. On the other hand, at this stage, since the ground doping area 130 is not exposed, the shading material 160a will not directly contact the ground doping area 130.

[0069] Please refer to Figure 3C , a dielectric layer 104 is formed on the substrate 110 in its entirety. For example, the dielectric layer 104 can be formed on the substrate 110 in the pixel array region RA, the boundary region RB, and the peripheral region RP of the substrate 100 and cover the light shielding material 160a. Here, the material of the dielectric layer 104 can include silicon oxide or a similar dielectric material and can be formed by deposition or a similar manufacturing process. The materials of the dielectric layer 103 and the dielectric layer 104 can be the same or different, and the dielectric layer 104 can be referred to as a second dielectric layer.

[0070] In some embodiments, after the dielectric layer 104 is formed, a planarization process, such as a chemical mechanical polishing (CMP) process, may be further performed to improve the surface flatness of the dielectric layer 104 , but the present invention is not limited thereto.

[0071] Please refer to Figure 3D , using the patterned photoresist 105 as a mask, a portion of the dielectric layer 103 and a portion of the dielectric layer 104 on the ground doping region 130 are removed (for example, by an etching process) to form an annular groove C1, wherein the annular groove C1 surrounds the global shutter element 120 and exposes the ground doping region 130 for subsequent electrical connection. Here, the patterned photoresist 105 can be referred to as a second patterned photoresist.

[0072] In the present embodiment, the annular groove C1 may penetrate the dielectric layer 103 and the dielectric layer 104 in the depth direction D1, and have a gradient size (e.g., wide at the top and narrow at the bottom) in the width direction D2 to expose a portion of the light shielding material 160a, so that a shared contact structure can be formed later. On the other hand, the patterned photoresist 105 can be used as a mask to remove a portion of the dielectric layer 103 and a portion of the dielectric layer 104 on the gates 122, 124, 126, 142 and the doped regions 127, 141 (e.g., by an etching process) to form a plurality of contact holes V21 exposing the gates 122, 124, 126, 142 and the doped regions 127, 141. In other words, the annular groove C1 and the contact holes V21 can be formed by the same patterned photoresist 105 in the same process. In this way, the amount of photoresist used can be saved, and the manufacturing cost can be effectively reduced, but the present invention is not limited thereto. Here, the contact through hole V21 on the pixel array area RA may be referred to as a second contact through hole.

[0073] Please refer to Figure 3E For example, after removing the patterned photoresist 105 through an ashing process, a light shielding material 160b is deposited to fill the annular groove C1 and the contact through hole V21 to form a contact 170 and another portion of the light shielding layer 160, wherein the light shielding material 160a and the light shielding material 160b can together constitute the light shielding layer 160, the light shielding layer 160 on the pixel array area RA covers the storage node 123, and the light shielding layer 160 on the boundary area RB surrounds the global shutter assembly 120. Here, the light shielding material 160b can be referred to as a second light shielding material, the contact 170 can be referred to as a second contact, the light shielding layer 160 on the pixel array area RA can be referred to as a first light shielding layer, and the light shielding layer 160 on the boundary area RB can be referred to as a second light shielding layer. On the other hand, the light shielding layer 160 can be electrically connected to the electrically doped region 130 to form a ground, so that the light shielding layer 160 is not in a floating state to avoid electrical problems.

[0074] Accordingly, in the image sensor 100 of the present embodiment, the light shielding layer 160 on the pixel array area RA blocks light coming from above, and the light shielding layer 160 on the boundary area RB blocks stray light coming from the side. In this way, the light incident on the storage node 123 area can be significantly reduced, and the parasitic light sensitivity caused by it can be effectively reduced.

[0075] Furthermore, Figure 2 The specific form of the dotted frame line 20 can correspond to Figure 3E The dashed line 20, and Figure 2 The light shielding layer LS can correspond to Figure 3EThe light shielding layer 160, therefore, the light shielding layer LS (light shielding layer 160) can surround multiple surfaces (such as the top surface and the side surfaces) of the pixel array area RA to form a structure like a continuous wall, thereby greatly reducing the adverse effects of the stray light SL on the storage node 123. The adverse effects are, for example, due to the stray light SL interfering with the signal stored in the storage node 123, causing the electrons generated in the substrate 110 to diffuse into the storage node 123 and become a source of signal pollution, but the present invention is not limited to this.

[0076] In some embodiments, Figure 2 As shown, the light shielding layer LS (light shielding layer 160) only exposes the light incident / electrical connection part L / E of the pixel array area RA, wherein the light incident part corresponds to the photoelectric element 121, and the electrical connection part corresponds to the gates 122, 124, 126, 142, but the present invention is not limited thereto.

[0077] In the present embodiment, since the light shielding material 160b is filled into the annular groove C1 and the contact through hole V21 together, the contact member 170 in the contact through hole V21 can be formed together with the light shielding layer 160 on the boundary area RB, and part of the light shielding material 160b can be deposited on the light shielding material 160a. In addition, after the light shielding material 160b is deposited, the surfaces of the dielectric layer 104 and the light shielding material 160b can be further planarized by a process such as a CMP process, depending on the actual design requirements. In this way, the top surface 104t of the dielectric layer 104, the top surface 160t1 of the light shielding layer 160 on the boundary area RB, and the top surface 1700t of the contact member 170 can be coplanar, and the top surface 160t1 of the light shielding layer 160 on the boundary area RB is higher than the top surface 160t2 of the light shielding layer 160 on the pixel array area RA, but the present invention is not limited thereto. Here, the contact 170 is electrically connected to the gates 122 , 124 , 126 , 142 .

[0078] In some embodiments, the contact 150 is physically connected to the light shielding layer 160 on the pixel array area RA, and the width of the contact 150 may be smaller than the width of the light shielding layer 160 thereon, but the present invention is not limited thereto.

[0079] In this embodiment, since the light shielding layer 160 is a shared contact formed by the light shielding material 160a and the light shielding material 160b, it can have a stepped profile, such as Figure 3E As shown, the present invention is not limited thereto.

[0080] In some embodiments, the light shielding layer 160 on the boundary region RB blocks the global shutter element 120 in the pixel array region RA from the peripheral circuit elements 140 in the peripheral region RP, but the present invention is not limited thereto.

[0081] Please refer to Figure 3F, a circuit layer M1 is formed on the light shielding layer 160, wherein the circuit layer M1 can be formed by forming a conductive material (such as aluminum or copper) on the substrate 110 through a suitable deposition process, and then forming the required circuit part through a photolithography patterning process, but the present invention is not limited to this.

[0082] Please refer to Figure 3G , an interconnection layer MV, a circuit layer M2 and a dielectric layer D are formed on the circuit layer M1, wherein the circuit layer M1 is electrically connected to the circuit layer M2 through the interconnection layer MV, the circuit layer M2 is similar to the circuit layer M1, and the interconnection layer MV is formed by a suitable through-hole manufacturing process, and the circuit layers M1, M2 and the interconnection layer MV are all buried in the dielectric layer D to form an inner connection structure 180. The manufacturing of the image sensor 100 of this embodiment can be substantially completed through the above manufacturing. Here, the present invention does not limit the number, material and manufacturing process of the circuit layers and dielectric layers in the inner connection structure, which can be determined according to the actual design requirements.

[0083] In this embodiment, the boundary region RB may not have the circuit layer M1 and the interconnection layer MV, but the present invention is not limited thereto. In an embodiment not shown, the circuit layer M1 and the interconnection layer MV may also be formed between the circuit layer M2 and the light shielding layer 160 .

[0084] It must be noted here that the following embodiments continue to use the component numbers and some contents of the above-mentioned embodiments, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, please refer to the above-mentioned embodiments, and the following embodiments will not be repeated.

[0085] Please refer to Figure 4A , similar to Figure 3A , the difference is that after forming the dielectric layer 103, the patterned photoresist 106 is first used as a mask to remove part of the dielectric layer 103 on the ground doping region 130 (for example, by an etching process) to form an annular groove C2 in the boundary region RB, wherein the annular groove C2 surrounds the global shutter element 120 and exposes the ground doping region 130. Here, the patterned photoresist 106 can be referred to as a third patterned photoresist.

[0086] Please refer to FIG. 4A to FIG. 4B For example, after removing the patterned photoresist 106 by an ashing process, the patterned photoresist 107 is used as a mask to remove part of the dielectric layer 103 on the optoelectronic device 121 (for example, by an etching process) to form a plurality of contact holes V11, that is, the annular groove C2 is formed before the contact holes V11 and is formed using a different patterned photoresist. Here, the patterned photoresist 107 may also be referred to as a first patterned photoresist.

[0087] Please refer to FIG. 4B to FIG. 4C and Figure 2 For example, after removing the patterned photoresist 107 through an ashing process, a light shielding material 260 is deposited in the contact hole V11 and the annular groove C2 and extends to the top surface 103t of the dielectric layer 103, so as to form a plurality of contacts 150 in the contact hole V11 and a light shielding layer 260 is formed on the top surface 103t of the dielectric layer 103 and in the annular groove C2, wherein the light shielding layer 260 on the pixel array area RA covers the storage node 123, and the light shielding layer 260 on the boundary area RB surrounds the global shutter element 120. Here, the light shielding layer 260 on the pixel array area RA can be referred to as a first light shielding layer, and the light shielding layer 260 on the boundary area RB can be referred to as a second light shielding layer. On the other hand, the light shielding layer 260 can be electrically connected to the electrically doped region 130 to form a ground, so that the light shielding layer 260 is not in a floating state. Here, the details of depositing the light shielding material 260 can be similar to the details of depositing the light shielding material 160a to form a plurality of openings corresponding to Figure 2 The light incident / electrical connection portion L / E on the middle pixel array area RA will not be described in detail here.

[0088] Accordingly, the light shielding layer 260 of the image sensor 200 of the present embodiment blocks light from above on the pixel array area RA, and blocks stray light from the side on the boundary area RB. In this way, the light incident on the storage node 123 area can be significantly reduced, and the parasitic light sensitivity caused by it can be effectively reduced.

[0089] Furthermore, Figure 2 The specific form of the dotted frame line 20 can correspond to Figure 4C The dashed line 20, and Figure 2 The light shielding layer LS can correspond to Figure 4C The light shielding layer 260 is formed so that the light shielding layer LS (light shielding layer 260) can surround multiple surfaces (such as the top surface and the side surface) of the pixel array area RA to form a structure like a continuous wall, thereby greatly reducing the adverse effects of stray light SL on the storage node 123, but the present invention is not limited thereto. Here, the light shielding layer 260 can be made of tungsten (W) or other suitable light shielding materials by a deposition process or other suitable manufacturing process.

[0090] In this embodiment, since the light shielding layer 260 is completed by only one manufacturing process, it does not have a stepped profile, but the present invention is not limited thereto.

[0091] Please refer to Figure 4D, a dielectric layer 104 is formed entirely on the substrate 110. For example, the dielectric layer 104 can be formed on the substrate 110 in the pixel array region RA, the boundary region RB and the peripheral region RP of the substrate 100 and cover the light shielding layer 260, but the present invention is not limited thereto.

[0092] In some embodiments, after the dielectric layer 104 is formed, a planarization process, such as a CMP process, may be further performed to improve the surface flatness of the dielectric layer 104 , but the present invention is not limited thereto.

[0093] Please refer to FIG. 4E to FIG. 4F , using the patterned photoresist 108 as a mask, removing portions of the dielectric layer 103 and portions of the dielectric layer 104 on the gates 122, 124, 126, 142 and the doped regions 127, 141 (e.g., by an etching process) to form a plurality of contact holes V22 exposing the gates 122, 124, 126, 142 and the doped regions 127, 141, and then, after removing the patterned photoresist 108, for example, by an ashing process, forming a plurality of contacts 270 in the contact holes V22, wherein since the patterned photoresist 108 does not expose the light shielding layer 260 on the boundary region RB, the conductive material forming the contacts 270 will not directly contact the light shielding layer 260, and the material of the contacts 270 can be the same as or different from the material of the light shielding layer 260, such as both can be tungsten (W). Here, the patterned photoresist 108 can be referred to as a fourth patterned photoresist.

[0094] In the present embodiment, the top surface 104t of the dielectric layer 104 and the top surface 270t of the contact member 270 may be higher than the top surface 260t1 of the light shading layer 260 on the boundary area RB and the top surface 260t2 of the light shading layer 260 on the pixel array area RA, and the top surface 260t1 of the light shading layer 260 on the boundary area RB and the top surface 260t2 of the light shading layer 260 on the pixel array area RA are coplanar, but the present invention is not limited to this.

[0095] In some embodiments, after the contact 270 is formed, a planarization process, such as a CMP process, may be further performed to improve the surface flatness of the contact 270 , but the present invention is not limited thereto.

[0096] Please refer to Figure 4G and Figure 4H , a circuit layer M1, an interconnection layer MV, a circuit layer M2 and a dielectric layer D are formed on the contact element 270, wherein the circuit layer M1 is electrically connected to the circuit layer M2 through the interconnection layer MV, and the circuit layer M1, the circuit layer M2 and the interconnection layer MV are buried in the dielectric layer D to form an inner connection structure 180. The above-mentioned manufacturing can substantially complete the manufacturing of the image sensor 200 of this embodiment.

[0097] Figure 5 The flowchart is a partial schematic diagram of an image sensor according to an embodiment of the present invention. The main manufacturing steps of the image sensor according to the present invention are described below through the flowchart.

[0098] First, a substrate is provided, wherein the substrate has at least adjacent pixel array regions and boundary regions (step S100). Next, a global shutter component is formed in the pixel array region, wherein the global shutter component includes a storage node (step S200), and a ground doping region is also formed in the boundary region (step S300). Then, an annular groove is formed in the boundary region to surround the global shutter component, wherein the annular groove exposes the ground doping region (step S400), and a light shielding layer is formed in the pixel array region and the boundary region and electrically connected to the ground doping region, wherein a first light shielding layer of the light shielding layer covers the storage node, and at least a portion of a second light shielding layer of the light shielding layer fills the annular groove (step S500).

[0099] In summary, the light shielding layer on the pixel array region of the image sensor of the present invention blocks light from above, and the light shielding layer on the boundary region blocks stray light from the side. In this way, the light incident on the storage node region can be significantly reduced, and the parasitic light sensitivity caused by it can be effectively reduced.

[0100] Although the present invention is disclosed in conjunction with the above embodiments, they are not intended to limit the present invention. Any ordinary technician in the technical field may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the definition of the attached claims.

Claims

1. An image sensor, comprising: A substrate having at least an adjacent pixel array region and a boundary region; A global shutter component is located in the pixel array area, wherein the global shutter component includes a storage node; a grounding doped region located in the boundary region; and A light-shielding layer is located on the pixel array area and the boundary area and is electrically connected to the ground doped area, wherein the light-shielding layer includes a first light-shielding layer and a second light-shielding layer, the first light-shielding layer is on the pixel array area and covers the storage node, and the second light-shielding layer is on the boundary area and surrounds the global shutter component. 2 . The image sensor as claimed in claim 1 , further comprising a plurality of first contacts located in the pixel array region, wherein the plurality of first contacts are physically connected to the light shielding layer.

3. The image sensor as claimed in claim 1, wherein the light shielding layer only exposes the light incident / electrical connection portion of the pixel array area, wherein the light incident portion of the light incident / electrical connection portion corresponds to the photodiode in the global shutter component, and the electrical connection portion of the light incident / electrical connection portion corresponds to a plurality of gates in the global shutter component.

4. The image sensor as claimed in claim 1, wherein the substrate further comprises a peripheral region, the boundary region is located between the pixel array region and the peripheral region, and the second light shielding layer separates the global shutter component in the pixel array region from peripheral circuit elements in the peripheral region. 5 . The image sensor as claimed in claim 1 , wherein a top surface of the second light shielding layer is higher than a top surface of the first light shielding layer.

6. The image sensor as described in claim 5 further includes a plurality of second contacts located in the pixel array area, wherein the plurality of second contacts are electrically connected to the global shutter assembly, and top surfaces of the plurality of second contacts are coplanar with the top surface of the second light shielding layer. 7 . The image sensor as claimed in claim 5 , wherein the second light shielding layer has a stepped profile. 8 . The image sensor of claim 1 , wherein a top surface of the first light shielding layer is coplanar with a top surface of the second light shielding layer.

9. The image sensor as described in claim 8 further includes a plurality of second contacts located in the pixel array area, wherein the plurality of second contacts are electrically connected to the global shutter assembly, and the top surfaces of the plurality of second contacts are higher than the top surface of the first light-shielding layer and the top surface of the second light-shielding layer. 10 . The image sensor as claimed in claim 8 , wherein the second light shielding layer does not have a stepped profile.

11. A method for manufacturing an image sensor, comprising: Providing a substrate, wherein the substrate at least has an adjacent pixel array region and a boundary region; forming a global shutter component in the pixel array region, wherein the global shutter component includes a storage node; forming a grounding doped region in the boundary region; forming an annular groove in the boundary region to surround the global shutter assembly, wherein the annular groove exposes the ground doping region; as well as A light shielding layer is formed in the pixel array region and the boundary region and electrically connected to the ground doping region, wherein the light shielding layer includes a first light shielding layer and a second light shielding layer, the first light shielding layer covers the storage node, and at least a portion of the second light shielding layer fills the annular groove.

12. The method for manufacturing an image sensor according to claim 11, further comprising: forming a first dielectric layer on the substrate; Using the first patterned photoresist as a mask, removing a portion of the first dielectric layer on the photodiode in the global shutter assembly to form a plurality of first contact holes; as well as A first light shielding material is deposited on the first contact holes and extends to the top surface of the first dielectric layer to form a plurality of first contacts, the first light shielding layer and at least a portion of the second light shielding layer.

13. The method for manufacturing an image sensor as claimed in claim 12, wherein after depositing the first light shielding material, the method further comprises: forming a second dielectric layer on the substrate; Using a second patterned photoresist as a mask, removing a portion of the first dielectric layer and a portion of the second dielectric layer on the grounding doped region in the boundary region to form the annular groove; as well as A second light shielding material is deposited to fill the annular groove, wherein the second light shielding layer is composed of a portion of the first light shielding material and a portion of the second light shielding material. 14 . The method for manufacturing an image sensor as claimed in claim 13 , wherein the annular groove exposes a portion of the first light shielding material. 15 . The method for manufacturing an image sensor as claimed in claim 13 , wherein a portion of the second light shielding material is deposited on the first light shielding material.

16. The method for manufacturing an image sensor according to claim 13, further comprising: Using the second patterned photoresist as a mask, removing a portion of the first dielectric layer and a portion of the second dielectric layer on a plurality of gates in the global shutter assembly in the pixel array region to form a plurality of second contact holes exposing the plurality of gates in the global shutter assembly; as well as Part of the second light shielding material is filled into the plurality of second contact through holes to form a plurality of second contact members. 17 . The method for manufacturing an image sensor as claimed in claim 13 , wherein after depositing the second light shielding material, a planarization process is performed on the second dielectric layer and the second light shielding material.

18. The method for manufacturing an image sensor according to claim 12, further comprising: Before forming the plurality of first contact holes, using the third patterned photoresist as a mask, removing a portion of the first dielectric layer on the grounding doped region in the boundary region to form the annular groove; as well as The first light-shielding material is filled into the annular groove to form the second light-shielding layer.

19. The method for manufacturing an image sensor according to claim 18, further comprising: After depositing the first light-shielding material, a second dielectric layer is formed on the substrate; Using the fourth patterned photoresist as a mask, removing a portion of the first dielectric layer and a portion of the second dielectric layer on a plurality of gates in the global shutter assembly in the pixel array region to form a plurality of second contact holes exposing the plurality of gates in the global shutter assembly; as well as A plurality of second contact members are formed in the plurality of second contact through holes. 20 . The method for manufacturing an image sensor as claimed in claim 19 , wherein the fourth patterned photoresist does not expose the first light shielding material on the boundary region.

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