Array substrate and photoelectric detector

Abstract

The array substrate comprises a photodiode, the photodiode comprises a first semiconductor layer, an intrinsic semiconductor layer and a second semiconductor layer which are sequentially arranged in a stacked mode, and the surface of the side, away from the intrinsic semiconductor layer, of the first semiconductor layer is a light inlet face; wherein a leakage current blocking layer is arranged between the first semiconductor layer and the intrinsic semiconductor layer, and / or between the second semiconductor layer and the intrinsic semiconductor layer, and a heterojunction is formed between the leakage current blocking layer and the intrinsic semiconductor layer. Through the above mode, the problem of current leakage can be reduced, the signal-to-noise ratio of the photoelectric detector is reduced, and the image output definition is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to an array substrate and a photodetector. Background Art

[0002] X-ray photodetectors made with flexible active matrix display technology are widely used in the field of medical diagnosis, and are also popular in safety imaging and non-destructive testing for integrity analysis. The photodetector converts X-rays into visible light through a scintillator, which is received by the PIN photodiode array on the array substrate. The PIN photocurrent signal generated by it is read by the thin film transistor TFT to form a high-resolution image.

[0003] How to improve the leakage current of existing photodetectors is a crucial issue that needs to be solved urgently. Summary of the invention

[0004] The present application provides an array substrate and a photodetector, which can reduce the problem of leakage current, reduce the signal-to-noise ratio of the photodetector, and improve the clarity of image output.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide an array substrate, including a photodiode, wherein the photodiode includes a first semiconductor layer, an intrinsic semiconductor layer and a second semiconductor layer which are stacked in sequence, and a surface of the first semiconductor layer facing away from the intrinsic semiconductor layer is a light-incoming surface; wherein a leakage current blocking layer is arranged between the first semiconductor layer and the intrinsic semiconductor layer, and / or between the second semiconductor layer and the intrinsic semiconductor layer, and a heterojunction is formed between the leakage current blocking layer and the intrinsic semiconductor layer.

[0006] Preferably, the leakage current blocking layer includes a first leakage current blocking layer and a second leakage current blocking layer, the first leakage current blocking layer is located between the first semiconductor layer and the intrinsic semiconductor layer, and the second leakage current blocking layer is located between the second semiconductor layer and the intrinsic semiconductor layer, wherein the first leakage current blocking layer and the second leakage current blocking layer are made of the same material, and / or the first leakage current blocking layer and the second leakage current blocking layer are of the same thickness.

[0007] Preferably, the material of the intrinsic semiconductor layer includes amorphous silicon, and the material of the leakage current blocking layer includes nanocrystalline silicon or amorphous silicon, wherein the crystallinity of the amorphous silicon of the leakage current blocking layer is greater than that of the amorphous silicon of the intrinsic semiconductor layer.

[0008] Preferably, the thickness of the leakage current blocking layer is in the range of 3-7 nm;

[0009] Preferably, the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer.

[0010] Preferably, the orthographic projection of the leakage current blocking layer on the intrinsic semiconductor layer covers the intrinsic semiconductor layer.

[0011] Preferably, the intrinsic semiconductor layer and the leakage current blocking layer are both formed by plasma enhanced chemical vapor deposition.

[0012] Preferably, the deposition pressure of the leakage current blocking layer is 350±30 MPa, and the deposition temperature is 250±20°C; or, the deposition pressure of the leakage current blocking layer is 200±80 MPa, and the deposition temperature is 300±20°C.

[0013] Preferably, the photodiode further comprises: a light shielding block, which is at least arranged on a side of the first semiconductor layer away from the intrinsic semiconductor layer and at an edge of the first semiconductor layer, and has a transmittance lower than a transmittance of the first semiconductor layer.

[0014] Preferably, the shading block is in a ring structure.

[0015] Preferably, the first semiconductor layer further includes a side surface connected to the light incident surface, and the light shielding block further extends to cover at least a portion of the side surface.

[0016] Preferably, the shading block covers all of the side surfaces.

[0017] Preferably, the thickness of the light shielding block is in the range of 3-7 nm; and / or the width of the light shielding block in the extension direction of the light incident surface is in the range of 18-22 nm.

[0018] Preferably, the material of the light shielding block includes metal.

[0019] Preferably, the light shielding block includes a molybdenum layer, or the light shielding block includes a first titanium layer, an aluminum layer and a second titanium layer which are stacked in sequence.

[0020] In order to solve the above technical problems, another technical solution adopted in the present application is: to provide a photodetector, comprising the array substrate and the scintillator described in any embodiment, the array substrate also comprising a first electrode, a second electrode and a thin film transistor, the first electrode is arranged on the side of the first semiconductor layer away from the intrinsic semiconductor layer, the second electrode is arranged on the side of the second semiconductor layer away from the intrinsic semiconductor layer, and the thin film transistor is electrically connected to the second electrode; the scintillator is located on the light incident side of the array substrate.

[0021] Different from the prior art, the beneficial effect of the present application is that a leakage current blocking layer is provided between the first semiconductor layer and the intrinsic semiconductor layer, and / or between the second semiconductor layer and the intrinsic semiconductor layer in the photodiode of the array substrate provided by the present application, and a heterojunction is formed between the leakage current blocking layer and the intrinsic semiconductor layer. The formation of the heterojunction regulates the band gap distribution in the photodiode, forms a potential barrier to prevent the movement of carriers, thereby preventing the transmission of leakage current, reducing the leakage effect generated by the intrinsic semiconductor layer during the operation of the photodetector, thereby reducing the signal-to-noise ratio of the photodetector, and improving the clarity of the image output by the photodetector. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0023] Figure 1 This is a schematic structural diagram of an implementation scheme of a photodiode in an array substrate of the present application;

[0024] Figure 2 This is a schematic structural diagram of another embodiment of a photodiode in an array substrate of the present application;

[0025] Figure 3 This is a schematic structural diagram of another embodiment of a photodiode in an array substrate of the present application;

[0026] Figure 4 for Figure 3 A top view of

[0027] Figure 5 This is a schematic structural diagram of another embodiment of a photodiode in an array substrate of the present application;

[0028] Figure 6 This is a schematic structural diagram of an embodiment of a photoelectric detector of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0030] See also Figure 1 , Figure 1The schematic diagram of the structure of an embodiment of a photodiode in the array substrate of the present application. The array substrate 100 includes a photodiode 10, which includes a first semiconductor layer 11, an intrinsic semiconductor layer 12, and a second semiconductor layer 13 stacked in sequence, and the surface of the first semiconductor layer 11 facing away from the intrinsic semiconductor layer 12 is a light-entering surface 11a. Specifically, the photodiode 10 is a PIN photodiode, the first semiconductor layer 11 is a P-type semiconductor layer, the intrinsic semiconductor layer 12 is an I-layer, and the second semiconductor layer 13 is an N-type semiconductor layer. Incident light enters the photodiode 10 from the light-entering surface 11a on the side of the first semiconductor layer 11.

[0031] However, the inventors discovered that due to the presence of a large number of interface defects and impurity defects in the PIN photodiode device, a higher leakage current will be generated in the intrinsic semiconductor layer 12 of the PIN photodiode, wherein holes move in the direction from the second semiconductor layer 13 to the first semiconductor layer 11, and electrons move in the direction from the first semiconductor layer 11 to the second semiconductor layer 13, resulting in the detector using the PIN photodiode having a high signal-to-noise ratio, unclear output image and other problems.

[0032] In view of this, a leakage current blocking layer 14 is provided between the first semiconductor layer 11 and the intrinsic semiconductor layer 12, and / or between the second semiconductor layer 13 and the intrinsic semiconductor layer 12 in the photodiode 10 of the present application, and a heterojunction is formed between the leakage current blocking layer 14 and the intrinsic semiconductor layer 12. The formation of the heterojunction regulates the band gap distribution in the photodiode 10, forms a potential barrier to prevent the movement of carriers, and thus prevents the transmission of leakage current.

[0033] In such Figure 1 In a specific embodiment shown, the leakage current blocking layer 14 is simultaneously arranged on both sides of the intrinsic semiconductor layer 12 facing the first semiconductor layer 11 and the second semiconductor layer 13, and the leakage current blocking layer 14 includes a first leakage current blocking layer 141 and a second leakage current blocking layer 142. The first leakage current blocking layer 141 is located between the first semiconductor layer 11 and the intrinsic semiconductor layer 12, and the second leakage current blocking layer 142 is located between the second semiconductor layer 13 and the intrinsic semiconductor layer 12. In this embodiment, the leakage current blocking layer 14 is directly in contact with the first semiconductor layer 11 and the second semiconductor layer 13, and the first leakage current blocking layer 141 and the second leakage current blocking layer 142 respectively form heterojunctions on the upper and lower sides of the intrinsic semiconductor layer 12, thereby being able to simultaneously prevent the movement of electrons and holes in two directions, further preventing the transmission of leakage current. In other embodiments, the leakage current blocking layer 14 may be disposed only on the side of the intrinsic semiconductor layer 12 facing the first semiconductor layer 11 to prevent the movement of holes, or may be disposed only on the side of the intrinsic semiconductor layer 12 facing the second semiconductor layer 13 to prevent the movement of electrons.

[0034] Optionally, continue to Figure 1 The leakage current blocking layer 14 covers the intrinsic semiconductor layer 12 on the positive projection of the intrinsic semiconductor layer 12 to ensure the blocking capability of the carriers.

[0035] In such Figure 2 In another specific embodiment shown, the leakage current blocking layer 14 may not be in direct contact with the first semiconductor layer 11 and the second semiconductor layer 13. Specifically, the leakage current blocking layer 14 includes a first leakage current blocking layer 141 and a second leakage current blocking layer 142, and the photodiode 10 includes a first semiconductor layer 11, an intrinsic semiconductor layer 12, a first leakage current blocking layer 141, an intrinsic semiconductor layer 12, a second leakage current blocking layer 142, an intrinsic semiconductor layer 12, and a second semiconductor layer 13 stacked in sequence. In this embodiment, there are intrinsic semiconductor layers 12 on both sides of the leakage current blocking layer 14, and each leakage current blocking layer 14 can form a heterojunction on both sides in the thickness direction, forming a double barrier to further prevent the transmission of leakage current.

[0036] Optionally, continue to Figure 1 The first leakage current blocking layer 141 and the second leakage current blocking layer 142 are made of the same material, and the first leakage current blocking layer 141 and the second leakage current blocking layer 142 are the same in thickness.

[0037] Alternatively, in other embodiments, the thickness of the second leakage current blocking layer 142 may be greater than the thickness of the first leakage current blocking layer 141. Since the movement speed of electrons in the intrinsic semiconductor layer 12 is generally higher than that of holes, the thicker second leakage current blocking layer 142 makes the blocking ability of the second leakage current blocking layer 142 greater than that of the first leakage current blocking layer 141, so as to further reduce the probability of leakage current.

[0038] Specifically, the material of the intrinsic semiconductor layer 12 includes amorphous silicon, and the material of the leakage current blocking layer 14 includes nanocrystalline silicon or amorphous silicon, wherein the crystallinity of the amorphous silicon of the leakage current blocking layer 14 is greater than the crystallinity of the amorphous silicon of the intrinsic semiconductor layer 12. Specifically, the thickness of the leakage current blocking layer 14 is in the range of 3-7 nm (e.g., 4 nm, 5 nm, 6 nm, etc.).

[0039] Optionally, both the intrinsic semiconductor layer 12 and the leakage current blocking layer 14 are formed by plasma enhanced chemical vapor deposition. Specifically, the deposition pressure of the leakage current blocking layer 14 is 350±30MPa, and the deposition temperature is 250±20°C; or, the deposition pressure of the leakage current blocking layer 14 is 200±80MPa, and the deposition temperature is 300±20°C. Since the intrinsic semiconductor layer 12 and the leakage current blocking layer 14 are deposited in sequence, the phase change of the film layer can be achieved by simply changing the deposition parameters. When the material of the leakage current blocking layer 14 is nanocrystalline silicon, the conversion from the amorphous silicon of the intrinsic semiconductor layer 12 to the nanocrystalline silicon of the leakage current blocking layer 14 can be achieved by increasing the deposition pressure. When the material of the leakage current blocking layer 14 is amorphous silicon, the crystallinity of the amorphous silicon of the leakage current blocking layer 14 can be made greater than the crystallinity of the amorphous silicon of the intrinsic semiconductor layer 12 by increasing the deposition temperature, thereby realizing the preparation of different types of film layers without changing the film layer material, improving the preparation efficiency, and reducing the preparation cost.

[0040] by Figure 1 Taking the structure shown as an example, in a specific implementation, the photodiode 10 of the present application can be prepared by the following steps:

[0041] Step 1: Form the second semiconductor layer 13 by plasma enhanced chemical vapor deposition (PECVD). Since the second semiconductor layer 13 is an N-type semiconductor layer, its material can be N-type amorphous silicon (n-aSi) doped with PH3, and the growth thickness is 40nm.

[0042] Step 2: Form the second leakage current blocking layer 142 by plasma enhanced chemical vapor deposition (PECVD). At this time, the deposition pressure is 350 MPa and the deposition temperature is 250° C. to form a hydrogenated nanocrystalline silicon (nc-Si:H) phase film layer with a growth thickness of 5 nm.

[0043] Step 3: Form an intrinsic semiconductor layer 12 by plasma enhanced chemical vapor deposition (PECVD), keep the deposition temperature unchanged, reduce the deposition pressure to 210MPa, realize the transition from hydrogenated nanocrystalline silicon (nc-Si:H) phase to hydrogenated amorphous silicon (a-Si:H) phase, and form an intrinsic semiconductor layer 12 of hydrogenated amorphous silicon with a growth thickness of 900nm.

[0044] Step 4: Similar to step 2, a first leakage current blocking layer 141 is formed, and the thickness of the first leakage current blocking layer 141 may be the same as or different from that of the second leakage current blocking layer 142 .

[0045] Step 5: Form the first semiconductor layer 11 by plasma enhanced chemical vapor deposition (PECVD). Since the first semiconductor layer 11 is a P-type semiconductor layer, its material can be P-type amorphous silicon (p-aSi) doped with B2H6, and the growth thickness is 25nm.

[0046] In the preparation method shown in this embodiment, each film layer in the photodiode 10 is formed by plasma enhanced chemical vapor deposition, and the first leakage current blocking layer 141, the intrinsic semiconductor layer 12 and the second leakage current blocking layer 142 are made of the same material. The transition between different phases can be achieved by simply changing the deposition parameters, and the preparation efficiency is high.

[0047] Optionally, in Figure 3 In another specific embodiment of the photodiode 10 shown, the photodiode 10 further includes a light shielding block 17, which is at least arranged on the side of the first semiconductor layer 11 away from the intrinsic semiconductor layer 12 and at the edge of the first semiconductor layer 11, and the transmittance of the light shielding block 17 is less than the transmittance of the first semiconductor layer 11. The inventors found that since there are more defects such as Si dangling bonds and impurities at the edge of the PIN photodiode, more noise signals are generated, so the light shielding block 17 is arranged at the edge to reduce the amount of light entering the edge of the photodiode 10, reduce the absorption of photons, and reduce the generation of noise signals. At the same time, the light shielding block 17 reduces the interference of the external environment on the edge area of ​​the photodiode 10, and suppresses the reduction of the resistance value of the area, so that the carriers (holes and electrons) will encounter a larger resistance when passing through the intrinsic semiconductor layer 12, so that the leakage current in the edge area is relatively small. Since the leakage current in the edge area accounts for more than half of the total leakage current of the photodiode 10, the leakage current problem of the photodiode 10 can be greatly improved. In addition, since the light shielding block 17 is located at the edge of the light incident surface 11 a of the photodiode 10 , the influence on the light incident effect can be reduced, thereby ensuring the test accuracy.

[0048] Optionally, see Figure 4 , Figure 4 yes Figure 3 The light shielding block 17 has a ring structure, which can reduce the leakage current of the sidewalls in all directions of the photodiode 10. In other embodiments, the light shielding block 17 can also be arranged only on one side or multiple side edges of the first semiconductor layer 11. Alternatively, the light shielding block 17 may include a plurality of light shielding sub-blocks arranged at intervals, and the light shielding sub-blocks are arranged along the edge of the first semiconductor layer 11. To ensure sufficient light intake.

[0049] Optionally, the shape of the light shielding block 17 is consistent with the edge shape of the first semiconductor layer 11. In this embodiment, the first semiconductor layer 11 is square and the light shielding block 17 is square ring-shaped, so that the light shielding block 17 minimizes the effect of light entering. In other embodiments, the light shielding block 17 can also be circular ring-shaped.

[0050] Optionally, in Figure 5In another specific embodiment of the photodiode 10 shown, the first semiconductor layer 11 further includes a side surface 11b connected to the light-incoming surface 11a, and the light shielding block 17 further extends to cover the entire side surface 11b. Since the incident light may enter the photodiode 10 from the side surface of the first semiconductor layer 11 after reflection, the light shielding block 17 is arranged on the side surface 11b, which can further reduce the amount of light entering the edge of the first semiconductor layer 11 and reduce the impact of leakage current. In other embodiments, the light shielding block 17 can also cover part of the side surface 11b.

[0051] Specifically, the thickness of the shading block 17 is in the range of 3-7nm (for example, 4nm, 5nm, 6nm, etc.). The width of the shading block 17 in the extension direction of the light-entering surface 11a is 18-22nm (for example, 19nm, 20nm, 21nm, etc.). Specifically, the material of the shading block 17 includes metal to ensure the conductivity. The specific material of the shading block 17 can be molybdenum or titanium. The specific structure of the shading block 17 can be a single-layer film layer or a multi-layer structure. For example, the shading block 17 includes a first titanium layer, an aluminum layer, and a second titanium layer stacked in sequence. The shading block 17 of the above material has a low transmittance and can be formed by magnetron sputtering (PVD). The thickness can be 5nm and the width can be 20nm.

[0052] See also Figure 6 , Figure 6A schematic diagram of the structure of an embodiment of a photodetector of the present application includes an array substrate 100 and a scintillator (not shown) of any of the above embodiments, wherein the array substrate 100 specifically includes a stacked substrate 20, a buffer layer 30, a thin film transistor 40, a second electrode 102, a photodiode 10 and a first electrode 101, wherein the first electrode 101 is arranged on a side of the first semiconductor layer 11 away from the intrinsic semiconductor layer 12, the second electrode 102 is arranged on a side of the second semiconductor layer 13 away from the intrinsic semiconductor layer 12, the thin film transistor is electrically connected to the second electrode, wherein the thin film transistor includes a gate 41, an active layer 42, a source 43 and a drain 44, and the gate 41 is arranged The active layer 42 is arranged on the side of the buffer layer 30 away from the substrate 20, the gate 41 is provided with a gate insulating layer 50 on the side away from the substrate 20, the active layer 42 is arranged on the side of the gate insulating layer 50 away from the substrate 20, the active layer 42 is provided with a first insulating layer 60 and a second insulating layer 70 in sequence on the side away from the substrate 20, the source 43 and the drain 44 are arranged on the side of the second insulating layer 70 away from the substrate 20, the source 43 and the drain 44 are electrically connected to the active layer 42, the side of the source 43 and the drain 44 away from the substrate 20 is provided with a passivation layer 80, the second electrode 102 is arranged on the side of the passivation layer 80 away from the substrate 20, and is electrically connected to the drain 44 or the source 43 through the passivation layer 80. The light shielding block 17 can be arranged on the side of the first electrode 101 away from the first semiconductor layer 11, or can be arranged between the first electrode 101 and the first semiconductor layer 11. The scintillator is located on the light-incoming surface 11a side of the array substrate 100. The photoelectric detector of the present application has a lower signal-to-noise ratio and higher output image clarity.

[0053] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An array substrate, characterized in that: A photodiode is included, wherein the photodiode includes a first semiconductor layer, an intrinsic semiconductor layer, and a second semiconductor layer which are stacked in sequence, and a surface of the first semiconductor layer which is away from the intrinsic semiconductor layer is a light-incoming surface; A leakage current blocking layer is provided between the first semiconductor layer and the intrinsic semiconductor layer, and / or between the second semiconductor layer and the intrinsic semiconductor layer, and a heterojunction is formed between the leakage current blocking layer and the intrinsic semiconductor layer.

2. The array substrate according to claim 1, characterized in that: The leakage current blocking layer includes a first leakage current blocking layer and a second leakage current blocking layer, the first leakage current blocking layer is located between the first semiconductor layer and the intrinsic semiconductor layer, and the second leakage current blocking layer is located between the second semiconductor layer and the intrinsic semiconductor layer, wherein the first leakage current blocking layer and the second leakage current blocking layer are made of the same material, and / or the first leakage current blocking layer and the second leakage current blocking layer have the same thickness.

3. The array substrate according to claim 1, characterized in that: The material of the intrinsic semiconductor layer includes amorphous silicon, and the material of the leakage current blocking layer includes nanocrystalline silicon or amorphous silicon, wherein the crystallinity of the amorphous silicon of the leakage current blocking layer is greater than the crystallinity of the amorphous silicon of the intrinsic semiconductor layer.

4. The array substrate according to claim 1, characterized in that: The thickness of the leakage current blocking layer is in the range of 3-7 nm; Preferably, the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer; Preferably, the orthographic projection of the leakage current blocking layer on the intrinsic semiconductor layer covers the intrinsic semiconductor layer.

5. The array substrate according to claim 3, characterized in that: The intrinsic semiconductor layer and the leakage current blocking layer are both formed by plasma enhanced chemical vapor deposition; Preferably, the deposition pressure of the leakage current blocking layer is 350±30 MPa, and the deposition temperature is 250±20°C; or, the deposition pressure of the leakage current blocking layer is 200±80 MPa, and the deposition temperature is 300±20°C.

6. The array substrate according to claim 1, characterized in that: The photodiode further comprises: A light shielding block is at least arranged on a side of the first semiconductor layer away from the intrinsic semiconductor layer and at an edge of the first semiconductor layer, and the transmittance of the light shielding block is less than the transmittance of the first semiconductor layer; Preferably, the shading block is in a ring structure.

7. The array substrate according to claim 6, characterized in that: The first semiconductor layer further includes a side surface connected to the light-incoming surface, and the light shielding block further extends to cover at least a portion of the side surface; Preferably, the shading block covers all of the side surfaces.

8. The array substrate according to claim 6, characterized in that: The thickness of the light shielding block is in the range of 3-7 nm; and / or, The width of the light shielding block in the extending direction of the light incident surface is 18-22 nm.

9. The array substrate according to claim 6, characterized in that: The material of the light shielding block includes metal; Preferably, the light shielding block comprises a molybdenum layer, or, The light shielding block includes a first titanium layer, an aluminum layer, and a second titanium layer which are stacked in sequence.

10. A photoelectric detector, characterized in that: include: The array substrate according to any one of claims 1 to 9; The scintillator is located on the light incident side of the array substrate.

Images