Negative capacitance transistor with kappa-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and preparation method thereof

Abstract

The invention discloses a negative capacitance transistor with a kappa-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a preparation method of the negative capacitance transistor. The negative capacitance transistor comprises a substrate, a GaN buffer layer, a UID-GaN channel layer, an Al < 0.25 > Ga < 0.75 > N barrier layer, a source electrode, a drain electrode and a grid electrode which are arranged on the Al < 0.25 > Ga < 0.75 > N barrier layer, and a kappa-Ga < 2 > O < 3 > / Al < 2 > O < 3 > composite iron dielectric layer which is arranged between the grid electrode and the Al < 0.25 > Ga < 0.75 > N barrier layer, wherein the substrate, the GaN buffer layer, the UID-GaN channel layer and the Al < 0.25 > Ga < 0.75 > N barrier layer are sequentially arranged from bottom to top. The negative capacitance transistor provided by the invention can realize the combination of volatile storage and non-volatile storage, so that the stability of a system and the reliability of data storage after power failure are improved while the high-speed data processing capability is ensured, and efficient data management support is provided for the application of a full reserve pool.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a preparation method thereof. Background Art

[0002] With the continuous evolution of semiconductor technology, transistor size continues to shrink, approaching physical limits. However, as device integration density increases, power consumption becomes increasingly prominent. Although performance can be improved to a certain extent by adopting high-dielectric-constant materials, increasing current drive capability, and optimizing device structure, these technical approaches still cannot effectively address the problem of excessive power consumption. This is because the subthreshold swing (SS) of traditional metal-oxide-semiconductor field-effect transistors is limited by Boltzmann statistics and can only reach a minimum of 60 mV / dec, which greatly limits the device's switching speed and energy efficiency. Therefore, how to overcome this bottleneck and develop new, low-power devices with even lower SS has become a key technical challenge in achieving higher-performance and lower-power integrated circuits, and is also an important research direction for the future semiconductor industry.

[0003] The negative capacitance effect generated by ferroelectric materials during polarization reversal can amplify the surface potential of the channel material, effectively reducing the device's subthreshold swing (SS) and breaking the Boltzmann limit. This makes them an ideal choice for building low-power transistors in the post-Moore era. However, in traditional fabrication methods, the ferroelectric dielectric layer and the channel layer are not epitaxial, resulting in a large number of interface states at the interface. This is due to the large number of dangling bonds generated at the interface due to non-epitaxial growth. These defects, when used as transistors, can increase leakage current and reduce electron mobility, ultimately affecting the overall performance of the device.

[0004] In order to overcome the above problems and realize the construction of low-power negative capacitance transistors, the present invention adopts the epitaxial growth of κ-Ga2O3 material on the substrate to significantly reduce the interface state density. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer and a method for preparing the same. The present invention forms a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer with high interface quality by epitaxially growing a ferroelectric dielectric material film and combining it with oxygen interface compensation, thereby improving device performance. In the negative capacitance transistor of the present invention, the composite ferroelectric dielectric layer produces a negative capacitance effect during the polarization reversal process, thereby reducing device power consumption and enabling the transistor to break through the subthreshold swing limit. Oxygen plasma compensation can effectively improve the interface quality between the ferroelectric layer and the channel material and between the ferroelectric layer and alumina, reducing the impact of defect capture on ferroelectric performance, thereby further improving the stability and overall performance of the transistor. The present invention solves the problem in the prior art of using ferroelectric dielectric materials to prepare negative capacitance transistors, in which large defects are captured due to the ferroelectric hysteresis effect and low interface quality of the ferroelectric material, thereby affecting device performance.

[0006] To achieve the above purpose, the technical solution designed by the present invention is as follows: The present invention provides a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, wherein the negative capacitance transistor comprises a substrate, a GaN buffer layer, a UID-GaN channel layer, an Al 0.25 Ga 0.75 N barrier layer, and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer, and the source electrode arranged in the source electrode region, the drain electrode arranged in the drain electrode region and the gate arranged in the gate region; the UID-GaN channel layer and the Al 0.25 Ga 0.75 The contact surface of the N barrier layer forms a two-dimensional electron gas channel 2DEG; The negative capacitance transistor further includes a gate and an Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer between the N barrier layers; the κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer includes a plurality of layers arranged in the Al 0.25 Ga 0.75 A κ-Ga2O3 ferroelectric layer and an Al2O3 insulating layer are provided on the surface of the N barrier layer. The material of the κ-Ga2O3 ferroelectric layer is κ-Ga2O3, and the material of the Al2O3 insulating layer is Al2O3.

[0007] Furthermore, the negative capacitance transistor further comprises SiN x Insulating layer, the SiN x The insulating layer is arranged on the surface of the negative capacitance transistor except the gate region.

[0008] Furthermore, the Al 0.25 Ga 0.75 The interface between the N barrier layer and the κ-Ga2O3 ferroelectric layer is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer and the Al2O3 insulating layer is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.9×10 13 ~2.5×10 13 cm -2 .

[0009] Furthermore, the thickness of the κ-Ga2O3 ferroelectric layer is 50-100 nm, and the thickness of the Al2O3 insulating layer is 30-50 nm; The substrate is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate, the thickness of the GaN buffer layer is 4-4.5 μm, the thickness of the UID-GaN channel layer is 300-350 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer is 200~250 nm, and the SiN x The thickness of the insulating layer is 100~150 nm.

[0010] Furthermore, the thickness of the κ-Ga2O3 ferroelectric layer is 50 nm, and the thickness of the Al2O3 insulating layer is 30 nm; The substrate is a silicon substrate, the thickness of the GaN buffer layer is 4 μm, the thickness of the UID-GaN channel layer is 300 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer is 200 nm, and the SiN x The thickness of the insulating layer is 100 nm.

[0011] Furthermore, the source electrode and drain electrode are both Ti / Al / Ni / Au alloys, and the thicknesses of Ti, Al, Ni and Au are 20~30, 120~150, 50~60 and 80~100 nm, respectively; the gate is a Ni / Au alloy, and the thicknesses of Ni and Au are 50~60 and 80~100 nm, respectively; the distance between the gate and the source electrode is 6~12 μm, and the distance between the gate and the drain electrode is 6~12 μm.

[0012] The present invention also provides a method for preparing the negative capacitance transistor, comprising the following steps: (1) Clean the substrate; deposit the GaN buffer layer, UID-GaN channel layer and Al 0.25 Ga 0.75 N barrier layer; (2) Using photolithography technology on Al 0.25Ga 0.75 The source electrode region and the drain electrode region are defined on the surface of the N barrier layer. The source electrode and the drain electrode are formed by depositing Ti, Al, Ni, and Au metal layers by electron beam evaporation. The source electrode and the drain electrode are connected to the Al 0.25 Ga 0.75 The N barrier layer forms an ohmic contact; (3) Plasma enhanced chemical vapor deposition technology is used to deposit SiN on the surface of the epitaxial wafer x Insulation layer; (4) Using photolithography technology on SiN x The gate region is defined on the surface of the insulating layer, and SiN is etched vertically downward in the gate region. x Insulation layer until Al leaks out 0.25 Ga 0.75 The surface of the N barrier layer; (5) Sequentially growing a κ-Ga2O3 ferroelectric layer and an Al2O3 insulating layer on the surface of the epitaxial wafer; (6) Use plasma enhanced etching process to etch the Al2O3 insulating layer and κ-Ga2O3 ferroelectric layer outside the gate area until reaching the SiN x The surface of the insulation layer; (7) The Al2O3 insulating layer in the gate area is photolithographically processed and developed to form a gate window. Ni and Au metal layers are deposited in the gate window to form a gate, thereby obtaining a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer.

[0013] Furthermore, in the step (4), after defining the gate region, oxygen plasma treatment is used to remove residual glue; In the step (5), after depositing the κ-Ga2O3 ferroelectric layer, the κ-Ga2O3 ferroelectric layer is treated with oxygen plasma; The conditions of the oxygen plasma treatment are: radio frequency power of 100-500 W, and treatment time of 60 s.

[0014] Furthermore, the method further includes a side etching step, which is provided between step (2) and step (3). Specifically, the side etching step includes defining a non-effective working area at the outer edges of the source electrode and the drain electrode, respectively, and etching downward 200 nm along the non-effective working area to form a step notch structure. In the step (3), SiN is deposited on the surface of the epitaxial wafer and in the step-notch structure by using plasma enhanced chemical vapor deposition technology. x Insulation layer.

[0015] Furthermore, it also includes a needle window step, which is set after step (7). The needle window step is specifically to form a needle window by photolithography and development on the surface of the source electrode and the drain electrode respectively, and etching SiN in the needle window on the surface of the source electrode. x The insulating layer forms the source electrode pinning area, and SiN is etched in the pinning window on the drain electrode surface. x The insulating layer forms a drain electrode pinning region.

[0016] Principle of the present invention: 1. The present invention adopts a method of epitaxially growing κ-Ga2O3 material on an epitaxial wafer to significantly reduce the interface state density. The reasons for using κ-Ga2O3 as the ferroelectric layer are as follows: (1) κ-Ga2O3 has excellent remanent polarization strength. The theoretical remanent polarization strength of κ-Ga2O3 is 23 μC / cm², and the experimentally measured remanent polarization strength is 2 μC / cm², which is significantly higher than that of general two-dimensional slip ferroelectric materials (such as Cd3Cl6, which has a remanent polarization strength of 0.3~0.4 μC / cm² at room temperature); (2) κ-Ga2O3 also has a relatively small coercive electric field. Its theoretical coercive electric field is 2.27 MV / cm, while the coercive electric field of perovskite materials such as AlScN is 5 MV / cm. Therefore, the required voltage and power consumption are much lower than those of materials such as AlScN. Therefore, in comparison, κ-Ga2O3 has significant advantages in reducing device power consumption and improving switching performance due to its excellent coercive electric field and residual polarization strength, making it an ideal choice in the field of negative capacitance transistors. (3) κ-Ga2O3 has a band gap of 4.85 eV and a high dielectric constant of 32. It exhibits excellent radiation resistance, good thermal stability and excellent ultraviolet absorption ability. It has become the preferred material in the field of solar-blind ultraviolet detection and is widely used in various application scenarios such as space communications, fire monitoring, meteorological monitoring and environmental pollution monitoring.

[0017] 2. The reasons for choosing aluminum oxide as the material for forming the composite ferroelectric layer with gallium oxide are: Aluminum oxide has a high dielectric constant and low leakage current density, which can effectively reduce charge leakage in the dielectric layer and provide a reliable insulating environment for the device. In addition, aluminum oxide has good chemical stability and good chemical compatibility with gallium oxide, which can form a stable transition layer at the interface and reduce interface defects. Furthermore, the thermal expansion coefficient of aluminum oxide is close to that of gallium oxide, which helps maintain the stability of the interface structure under high-temperature process conditions and reduce interface defects caused by thermal stress. Finally, aluminum oxide has a large band gap of 8.8 eV, which can form a deep barrier in the composite ferroelectric dielectric layer, effectively blocking carriers from crossing and improving device performance.

[0018] Beneficial effects of the present invention: 1. Compared with traditional field-effect transistors, the negative capacitance transistor prepared by the present invention can achieve a subthreshold swing lower than the theoretical limit of 60 mV / dec. When the voltage scan rate is reduced to 0.003 V / s, the measured subthreshold swing is as low as 11 mV / dec. Therefore, the subthreshold swing is related to the voltage scan rate.

[0019] 2. In the present invention, oxygen plasma compensates the oxide surface, which can further effectively compensate the interface state and more fully reflect the regulation of the ferroelectric layer on the channel electrons. This process will not cause damage to the surface of the channel material.

[0020] 3. The method of reducing leakage of the present invention is applicable to any planar structure transistor, SiN x Can effectively isolate the gate through Al 0.25 Ga 0.75 The N barrier layer directly transmits the current to the source electrode, effectively reducing gate leakage, while aluminum oxide has a good effect in alleviating the leakage phenomenon caused by the crystal structure of the multi-rotation domain of κ-Ga2O3.

[0021] 4. The ferroelectric dielectric material κ-Ga2O3 in the negative capacitance transistor of the present invention is used to produce a negative capacitance effect when the polarization is reversed, thereby enabling the transistor device to break through the subthreshold swing limit. Compared with other non-epitaxially grown ferroelectric dielectric layers, the epitaxially grown κ-Ga2O3 has less interface state density, thereby promoting the electrons in the ferroelectric polarization control channel.

[0022] 5. The κ-Ga2O3 prepared by the present invention can be prepared on a variety of substrates to achieve diversified detection forms and meet different detection needs. The device prepared on the sapphire substrate works in the Rayleigh mode with a resonant frequency of 1.96 GHZ and a phase velocity of υ p is 3138 m / s, and the electromechanical coupling coefficient k eff 2 The device fabricated on a silicon carbide substrate operates in Cecilia mode with a resonant frequency of 3.31 GHz. p is 6640 m / s.

[0023] 6. The negative capacitance transistor prepared by the present invention has multiple modulation modes for electrical signals and dual resiliency (both long-term and short-term plasticity). Due to the wide bandgap characteristics and ferroelectric polarization effect of κ-Ga2O3, the transistor has multiple modulation modes for electrical signals and good radiation resistance to short-wavelength light. The transistor of the present invention can achieve a combination of volatile and non-volatile storage, thereby ensuring high-speed data processing capabilities while improving system stability and data preservation reliability after power failures. It provides efficient data management support for full-reserve pool applications, reduces migration delays and power consumption, and enhances its robustness in extreme environments. Therefore, the device can provide efficient data management support for full-reserve pool applications and is expected to be widely used in aerospace AI systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic structural diagram of a negative capacitance transistor of the present invention; In the figure, 1, substrate; 2, GaN buffer layer; 3, UID-GaN channel layer; 4, Al 0.25 Ga 0.75 N barrier layer; 5. Source electrode; 6. Drain electrode; 7. Gate electrode; 8. Composite ferroelectric dielectric layer; 9. κ-Ga2O3 ferroelectric layer; 10. Al2O3 insulating layer; 11. SiN x Insulation layer; Figure 2 To deposit GaN buffer layer, UID-GaN channel layer and Al 0.25 Ga 0.75 N barrier layer step diagram; Figure 3 Diagram of steps for preparing source and drain electrodes; Figure 4 Figure 2 is a side etching step diagram; Figure 5 For depositing SiN x Insulation layer step diagram; Figure 6 A diagram showing the steps for defining the gate region; Figure 7 Diagram of the steps for epitaxial growth of κ-Ga2O3 ferroelectric layer and Al2O3 insulating layer; Figure 8 A diagram showing the steps of etching the composite ferrodielectric layer outside the gate region; Figure 9 A diagram showing the steps for preparing the gate; Figure 10 This is a step-by-step diagram for the acupuncture window; Figure 11 An optical microscope image of a negative capacitance transistor device of the present invention; Figure 12This is the X-ray diffraction (XRD) result of the κ-Ga2O3 ferroelectric layer; Figure 13 This is the atomic force microscopy (AFM) result of the κ-Ga2O3 ferroelectric layer; Figure 14 This is the piezoelectric force microscopy (PFM) result of the κ-Ga2O3 ferroelectric layer; Figure 15 This is the polarization intensity result diagram of the κ-Ga2O3 ferroelectric layer under the PUND test; Figure 16 A transfer curve diagram of the oxide dielectric layer of the negative capacitance transistor of the present invention before being treated with oxygen plasma; Figure 17 is a transfer curve diagram of the negative capacitance transistor of the present invention after the oxide dielectric layer is treated by oxygen plasma; Figure 18 This is a graph showing the transfer characteristics of the negative capacitance transistor of the present invention; Figure 19 This is a graph showing the subthreshold swing results of the negative capacitance transistor of the present invention; Figure 20 is an output characteristic curve diagram of the negative capacitance transistor of the present invention; Figure 21 This is a graph showing the effects of small pulses and large pulses on the conductivity plasticity of the negative capacitance transistor of the present invention. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to specific embodiments so that those skilled in the art can understand.

[0026] Example 1 This embodiment provides a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric layer, combined with Figure 1 As shown, the negative capacitance transistor includes a substrate 1, a GaN buffer layer 2, a UID-GaN channel layer 3, an Al 0.25 Ga 0.75 N barrier layer 4, and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer 4, the source electrode 5 arranged in the source electrode region, the drain electrode 6 arranged in the drain electrode region and the gate 7 arranged in the gate region, and the gate 7 and Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer 8 between the N barrier layers 4 and the SiN layer on the surface of the epitaxial wafer except the gate region x The insulating layer 11, the κ-Ga2O3 / Al2O3 composite ferroelectric layer 8 is included in the Al0.25 Ga 0.75 A κ-Ga2O3 ferroelectric layer 9 and an Al2O3 insulating layer 10 are sequentially arranged on the surface of the N barrier layer 4 from bottom to top.

[0027] UID-GaN channel layer 3 and Al 0.25 Ga 0.75 The contact surface of the N barrier layer 4 forms a two-dimensional electron gas channel 2DEG; Al 0.25 Ga 0.75 The interface between the N barrier layer 4 and the κ-Ga2O3 ferroelectric layer 9 is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer 9 and the Al2O3 insulating layer 10 is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.90×10 13 cm -2 .

[0028] In the negative capacitance transistor with the κ-Ga2O3 / Al2O3 composite ferroelectric layer of this embodiment: (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 50-100 nm, and the thickness of the Al2O3 insulating layer 10 is 30-50 nm; Preferably, the thickness of the κ-Ga2O3 ferroelectric layer 9 is 50 nm, and the thickness of the Al2O3 insulating layer 10 is 30 nm; (2) The substrate 1 is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate; Preferably, the substrate 1 is a silicon substrate; (3) The thickness of the GaN buffer layer 2 is 4~4.5 μm, the thickness of the UID-GaN channel layer 3 is 300~350 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 200~250 nm, SiN x The thickness of the insulating layer 11 is 100-150 nm; Preferably, the thickness of the GaN buffer layer 2 is 4 μm, the thickness of the UID-GaN channel layer 3 is 300 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 200 nm, and the SiN x The thickness of the insulating layer 11 is 100 nm; (4) The source electrode 5 and the drain electrode 6 are both made of Ti / Al / Ni / Au alloy, with the thicknesses of Ti, Al, Ni, and Au being 20-30, 120-150, 50-60, and 80-100 nm, respectively; the gate 7 is made of Ni / Au alloy, with the thicknesses of Ni and Au being 50-60 and 80-100 nm, respectively; the distance between the gate 7 and the source electrode 5 is 6-12 μm, and the distance between the gate 7 and the drain electrode 6 is 6-12 μm; Preferably, in the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni and Au are 20, 120, 50 and 100 nm respectively; in the gate 7, the thicknesses of Ni and Au are 50 and 100 nm respectively; the distance between the gate 7 and the source electrode 5 is 6 μm, and the distance between the gate 7 and the drain electrode 6 is 10 μm.

[0029] Example 2 This embodiment provides a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric layer. The negative capacitance transistor of this embodiment is the same as that of embodiment 1 except that the transistor of this embodiment lacks SiN x Insulating layer 11.

[0030] Al 0.25 Ga 0.75 The interface between the N barrier layer 4 and the κ-Ga2O3 ferroelectric layer 9 is the first oxygen compensation interface, and the interface between the κ-Ga2O3 ferroelectric layer 9 and the Al2O3 insulating layer 10 is the second oxygen compensation interface. The defect density of the first oxygen compensation interface and the second oxygen compensation interface is 2.5×10 13 cm -2 .

[0031] Example 3 This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, combined with Figures 2 to 10 As shown, the specific steps include: 1. If Figure 2 As shown, the substrate 1 is cleaned; a GaN buffer layer 2, a UID-GaN channel layer 3 and an Al 0.25 Ga 0.75 N barrier layer 4, the specific steps are as follows: (1) Select a silicon substrate 1 with a (111) crystal plane (a silicon carbide substrate or a sapphire substrate may also be selected) to reduce the lattice mismatch with GaN, and use Piranha solution (H2SO4 + H2O2) or HF acid to clean the silicon substrate 1.

[0032] (2) A GaN buffer layer 2 was prepared on a silicon substrate 1. The GaN buffer layer 2 was deposited at 1050°C using ammonia (NH3) as a nitrogen source and triethylgallium (TEGa) as a gallium source under hydrogen or nitrogen protection using metal organic chemical vapor deposition (MOCVD) technology to a deposition thickness of 4 μm.

[0033] (3) A UID-GaN channel layer 3 is prepared on the GaN buffer layer 2. The UID-GaN channel layer 3 is grown by MOCVD. The MOCVD technology is also used for deposition. The growth temperature is 1050°C~1100°C and the deposition thickness is 300 nm.

[0034] (4) Preparation of Al on UID-GaN channel layer 3 0.25 Ga 0.75 The N barrier layer 4 is grown by MOCVD at 1050°C using triethylaluminum (TEAl) and triethylgallium (TEGa) as metal sources and NH3 as nitrogen source. 0.25 Ga 0.75 The N barrier layer 4 is deposited to a thickness of 200 nm.

[0035] 2. If Figure 3 As shown, in Al 0.25 Ga 0.75 Photolithography is performed on the N barrier layer 4 to define the source electrode region and the drain electrode region. After exposure, oxygen plasma is used to remove the residual glue. Subsequently, Ti, Al, Ni, and Au metal layers are deposited in sequence by electron beam evaporation with thicknesses of 20 nm, 120 nm, 50 nm, and 100 nm, respectively, to form the source electrode 5 and the drain electrode 6. After the metal deposition is completed, annealing is performed at 840°C in a nitrogen atmosphere for 1 min. The source electrode 5 and the drain electrode 6 are bonded to the Al 0.25 Ga 0.75 The N barrier layer 4 forms a high-quality ohmic contact.

[0036] 3. If Figure 4 As shown in FIG, the outer edges of the source electrode 5 and the drain electrode 6 define the inactive working area and the active working area respectively. Using photolithography technology, the photoresist covers the active working area, and the photoresist in the inactive working area is peeled off after exposure. Subsequently, the plasma enhanced etching (RIE) process is used to etch the Al2O3 layer down along the inactive working area. 0.25 Ga 0.75 The N barrier layer 4 material is 200 nm thick. Because the active working area is protected by photoresist, the active working area remains intact, while the material in the inactive working area is partially etched away. This method effectively isolates the devices from each other, forming a step-gap structure and successfully preventing current crosstalk between devices.

[0037] 4. If Figure 5As shown, the plasma enhanced chemical vapor deposition (PECVD) method is then used to deposit 100 nm of SiN on the surface of the epitaxial wafer through radio frequency plasma reaction in an atmosphere of silane (SiH4) and ammonia (NH3). x Thin film, forming SiN x Insulating layer 11.

[0038] 5. If Figure 6 As shown, the SiN x The gate region is defined on the surface of the insulating layer 11, and oxygen plasma is used to remove the residual glue (the conditions of oxygen plasma treatment are: the RF power range is 100~500W, and the duration of plasma treatment is fixed at 60s). Subsequently, a plasma enhanced etching (RIE) process is used to etch the SiN in the gate region in a mixed atmosphere of fluorine-based gas (such as SF6 or CHF3) and oxygen. x The insulating layer 11 is anisotropically etched until the Al 0.25 Ga 0.75 The surface of the N barrier layer 4 is cleaned with acetone to remove the remaining photoresist.

[0039] 6. If Figure 7 As shown, a 50 nm κ-Ga2O3 thin film is epitaxially grown on the surface of the epitaxial wafer using the Mist-CVD method (PLD or MOCVD can also be used). The temperature is set to 700°C. A precursor solution is prepared by dissolving gallium chloride (GaCl3) in deionized water or an alcohol solution (such as methanol or ethanol). The epitaxial growth is completed in an oxygen atmosphere to form a κ-Ga2O3 ferroelectric layer 9. The κ-Ga2O3 ferroelectric layer 9 is treated with oxygen plasma (the conditions for oxygen plasma treatment are: the RF power range is 100-500 W, and the duration of plasma treatment is fixed at 60 s). Subsequently, an atomic layer deposition (ALD) process is used to alternately introduce trimethylaluminum (TMA) and water vapor to react on the surface of the κ-Ga2O3 ferroelectric layer 9, and a 30 nm Al2O3 thin film is deposited layer by layer to form an Al2O3 insulating layer 10.

[0040] 7. If Figure 8 As shown, the region outside the gate region is subjected to photolithography, which is then exposed and developed to reveal the κ-Ga2O3 ferroelectric layer 9, the Al2O3 insulating layer 10, and the SiN x The insulating layer 11 is then removed with oxygen plasma to remove the residual glue, and then the Al2O3 insulating layer 10 and the κ-Ga2O3 ferroelectric layer 9 are etched away using the RIE process, leaving the SiN x Insulating layer 11.

[0041] 8. If Figure 9As shown, a gate 7 window is formed on the Al2O3 insulating layer 10 through photolithography and development, and then oxygen plasma is used to remove residual resist. Subsequently, Ni and Au electrodes with thicknesses of 50 nm and 100 nm, respectively, are deposited within the gate 7 window by electron beam evaporation, forming the gate 7. After preparation, metal stripping is performed using acetone solution to remove excess metal, completing the fabrication of the gate 7 (the distance between the gate 7 and the source electrode 5 is 6 μm, and the distance between the gate 7 and the drain electrode 6 is 10 μm).

[0042] 9. If Figure 10 As shown, the surface of the source electrode 5 and the surface of the drain electrode 6 are photolithographically etched and developed to form a pinning window, and then oxygen plasma is used to remove the residual glue. Subsequently, SiN is etched in the pinning window on the surface of the source electrode 5 by RIE etching. x The insulating layer 11 forms the source electrode 5 pinning area, and the pinning window on the drain electrode 6 surface is etched with SiN x The insulating layer 11 forms the puncture area of ​​the drain electrode 6, and a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer can be obtained. The minimum subthreshold swing of the transistor is 11 mV / dec.

[0043] Example 4 This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer. The preparation steps are the same as those in Example 3, except that: (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 100 nm, and the thickness of the Al2O3 insulating layer 10 is 50 nm; (2) The thickness of the GaN buffer layer 2 is 4.5 μm, the thickness of the UID-GaN channel layer 3 is 350 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 250 nm, and the SiN x The thickness of the insulating layer 11 is 150 nm; (3) In the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni, and Au are 30, 150, 60, and 80 nm, respectively; in the gate 7, the thicknesses of Ni and Au are 60 and 80 nm, respectively; the distance between the gate 7 and the source electrode 5 is 12 μm, and the distance between the gate 7 and the drain electrode 6 is 6 μm.

[0044] Example 5 This embodiment provides a method for preparing a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer. The preparation steps are the same as those in Example 3, except that: (1) The thickness of the κ-Ga2O3 ferroelectric layer 9 is 80 nm, and the thickness of the Al2O3 insulating layer 10 is 40 nm; (2) The thickness of the GaN buffer layer 2 is 4.2 μm, the thickness of the UID-GaN channel layer 3 is 320 nm, and the thickness of the Al 0.25 Ga 0.75 The thickness of the N barrier layer 4 is 230 nm, and the SiN x The thickness of the insulating layer 11 is 120 nm; (3) In the source electrode 5 and the drain electrode 6, the thicknesses of Ti, Al, Ni, and Au are 25, 130, 55, and 90 nm, respectively; in the gate 7, the thicknesses of Ni and Au are 55 and 90 nm, respectively; the distance between the gate 7 and the source electrode 5 is 10 μm, and the distance between the gate 7 and the drain electrode 6 is 12 μm.

[0045] Example 6 Performance testing of negative capacitance transistors with κ-Ga2O3 / Al2O3 composite ferroelectric layers Figure 11 This is an optical microscope image of the negative capacitance transistor device of Example 1, which has a top-gate structure.

[0046] Figure 12 This is the XRD pattern of the 50 nm κ-Ga2O3 ferroelectric layer prepared in Example 1. It can be seen that the prepared κ-Ga2O3 is a single phase. Figure 13 This is an AFM image of the 50 nm κ-Ga2O3 ferroelectric layer prepared in Example 1. The κ-Ga2O3 film has a flat and uniform surface with a roughness of 9.1 nm, and the growth mode is island growth.

[0047] Figure 14 This is a piezoelectric force microscopy image of a 50 nm κ-Ga2O3 ferroelectric layer. The results show that the film exhibits a significant phase inversion phenomenon and a certain amplitude response.

[0048] Figure 15 The polarization intensity of the 50 nm κ-Ga2O3 ferroelectric layer was measured by PUND. The results show that the material has a polarization intensity of 2 μC / cm 2 The residual polarization intensity.

[0049] Example 7 Effect of oxygen plasma treatment on the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention Figure 16 This is a transfer curve diagram of the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention before being treated with oxygen plasma. Figure 17The transfer curve of the oxide dielectric layer (Ga2O3 ferroelectric layer) of the negative capacitance transistor of the present invention after being treated with oxygen plasma is shown. The results show that the hysteresis of the transfer curve before treatment is clockwise, representing a defect capture mechanism, while the hysteresis of the transfer curve after treatment is counterclockwise, representing an iron-deficient electric polarization reversal mechanism. After the oxide dielectric layer of the negative capacitance transistor of the present invention is treated with oxygen plasma, the concentration of the acceptor interface state is reduced, and the potential barrier near the semiconductor surface will be further lowered. Therefore, the defect capture mechanism will become a secondary factor, and the ferroelectric polarization-induced channel formation will become the primary factor, making the performance of the negative capacitance transistor even better.

[0050] Example 8 Subthreshold swing detection of negative capacitance transistors with κ-Ga2O3 / Al2O3 composite ferroelectric layers Figure 18 is a transfer characteristic result diagram of the negative capacitance transistor of Example 1, Figure 19 This graph shows the subthreshold swing results for the negative capacitance transistor of Example 1. The results show that the transfer curve of this transistor exhibits counterclockwise hysteresis, and the subthreshold swing exceeds the Boltzmann limit, decreasing to below 60 mV / dec. Furthermore, the subthreshold swing is also affected by the voltage scan rate. Specifically, at a scan rate of 0.003 V / s, the minimum subthreshold swing measured is 11 mV / dec.

[0051] Figure 20 : is an output characteristic curve of the negative capacitance transistor of Example 1. From the output curve, it can be seen that the ferroelectric polarization reversal of κ-Ga2O3 has a significant modulation effect on the channel conductance.

[0052] Figure 21 The effects of small and large pulses on the conductivity plasticity of the negative capacitance transistor of Example 1 are demonstrated. When the pulse voltage is close to the coercive voltage of κ-Ga2O3, the transistor maintains its conductivity after the pulse is removed, exhibiting non-volatile memory characteristics. However, when the pulse voltage is far below the coercive voltage, the transistor "forgets" its conductivity after the pulse is removed, exhibiting volatile memory characteristics.

[0053] Although the above embodiments have been described in detail, they are only a part of the embodiments of the present invention, not all of them. People can also obtain other embodiments based on this embodiment without inventiveness, and these embodiments all fall within the scope of protection of the present invention.

Claims

1. A negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer, the negative capacitance transistor comprising a substrate (1), a GaN buffer layer (2), a UID-GaN channel layer (3), an Al 0.25 Ga 0.75 N barrier layer (4), and delineated in Al 0.25 Ga 0.75 The source electrode region, drain electrode region and gate region on the surface of the N barrier layer (4), and the source electrode (5) arranged in the source electrode region, the drain electrode (6) arranged in the drain electrode region and the gate (7) arranged in the gate region; the UID-GaN channel layer (3) and the Al 0.25 Ga 0.75 The contact surface of the N barrier layer (4) forms a two-dimensional electron gas channel 2DEG; Features: The negative capacitance transistor further includes a gate (7) and an Al 0.25 Ga 0.75 The κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer (8) is disposed between the N barrier layers (4); the κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer (8) comprises: 0.25 Ga 0.75 A κ-Ga2O3 ferroelectric layer (9) and an Al2O3 insulating layer (10) are provided on the surface of an N barrier layer (4), wherein the material of the κ-Ga2O3 ferroelectric layer (9) is κ-Ga2O3, and the material of the Al2O3 insulating layer (10) is Al2O3.

2. The negative capacitance transistor according to claim 1, characterized in that: The negative capacitance transistor further comprises SiN x The insulating layer (11), the SiN x An insulating layer (11) is arranged on the surface of the negative capacitance transistor except the gate region.

3. The negative capacitance transistor according to claim 1, characterized in that: The Al 0.25 Ga 0.75 The interface where the N barrier layer (4) and the κ-Ga2O3 ferroelectric layer (9) are in contact is a first oxygen compensation interface, and the interface where the κ-Ga2O3 ferroelectric layer (9) and the Al2O3 insulating layer (10) are in contact is a second oxygen compensation interface, and the defect density of the first oxygen compensation interface and the second oxygen compensation interface is 1.9×10 13 ~2.5×10 13 cm -2 .

4. The negative capacitance transistor according to claim 2, characterized in that: The κ-Ga2O3 ferroelectric layer (9) has a thickness of 50-100 nm, and the Al2O3 insulating layer (10) has a thickness of 30-50 nm; The substrate (1) is any one of a silicon substrate, a silicon carbide substrate and a sapphire substrate, the thickness of the GaN buffer layer (2) is 4-4.5 μm, the thickness of the UID-GaN channel layer (3) is 300-350 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer (4) is 200~250 nm, and the SiN x The thickness of the insulating layer (11) is 100-150 nm.

5. The negative capacitance transistor according to claim 4, characterized in that: The κ-Ga2O3 ferroelectric layer (9) has a thickness of 50 nm, and the Al2O3 insulating layer (10) has a thickness of 30 nm; The substrate (1) is a silicon substrate, the GaN buffer layer (2) has a thickness of 4 μm, the UID-GaN channel layer (3) has a thickness of 300 nm, and the Al 0.25 Ga 0.75 The thickness of the N barrier layer (4) is 200 nm, and the SiN x The thickness of the insulating layer (11) is 100 nm.

6. The negative capacitance transistor according to claim 1, characterized in that: The source electrode (5) and the drain electrode (6) are both Ti / Al / Ni / Au alloys, with the thicknesses of Ti, Al, Ni and Au being 20-30, 120-150, 50-60 and 80-100 nm respectively; the gate (7) is a Ni / Au alloy, with the thicknesses of Ni and Au being 50-60 and 80-100 nm respectively; the distance between the gate (7) and the source electrode (5) is 6-12 μm, and the distance between the gate (7) and the drain electrode (6) is 6-12 μm.

7. A method for preparing a negative capacitance transistor according to any one of claims 2 to 6, characterized in that: The following steps are involved: 1) cleaning the substrate (1); depositing a GaN buffer layer (2), a UID-GaN channel layer (3) and an Al 0.25 Ga 0.75 N barrier layer (4); 2) Using photolithography technology on Al 0.25 Ga 0.75 The surface of the N barrier layer (4) defines a source electrode region and a drain electrode region. Ti, Al, Ni, and Au metal layers are deposited by electron beam evaporation to form a source electrode (5) and a drain electrode (6). The source electrode (5) and the drain electrode (6) are connected to Al 0.25 Ga 0.75 The N barrier layer (4) forms an ohmic contact; 3) Plasma enhanced chemical vapor deposition technology is used to deposit SiN on the surface of the epitaxial wafer x Insulating layer (11); 4) Using photolithography technology on SiN x The surface of the insulating layer (11) defines a gate region, and SiN is etched vertically downward in the gate region. x Insulation layer (11) until Al leaks out 0.25 Ga 0.75 a surface of the N barrier layer (4); 5) sequentially growing a κ-Ga2O3 ferroelectric layer (9) and an Al2O3 insulating layer (10) on the surface of the epitaxial wafer; 6) Use plasma enhanced etching process to etch the Al2O3 insulating layer (10) and the κ-Ga2O3 ferroelectric layer (9) outside the gate area until reaching the SiN x a surface of the insulating layer (11); 7) Photolithography and development are performed on the Al2O3 insulating layer (10) in the gate region to form a gate (7) window, and Ni and Au metal layers are deposited in the gate (7) window to form a gate (7), thereby obtaining a negative capacitance transistor having a κ-Ga2O3 / Al2O3 composite ferroelectric dielectric layer.

8. The preparation method according to claim 7, characterized in that: In the step 4), after defining the gate region, oxygen plasma treatment is used to remove residual glue; In the step 5), after depositing the κ-Ga2O3 ferroelectric layer (9), the κ-Ga2O3 ferroelectric layer (9) is treated with oxygen plasma; The conditions of the oxygen plasma treatment are: radio frequency power of 100-500 W and treatment time of 60 s.

9. The preparation method according to claim 7, characterized in that: The method further comprises a side etching step, wherein the side etching step is arranged between step 2) and step 3), and the side etching step specifically comprises defining a non-effective working area at the outer edges of the source electrode (5) and the drain electrode (6), respectively, and etching downwards by 200 nm along the non-effective working area to form a step notch structure; In the step 3), SiN is deposited on the surface of the epitaxial wafer and in the step-notch structure by plasma enhanced chemical vapor deposition technology. x Insulating layer (11).

10. The preparation method according to claim 7, characterized in that: The invention also includes a needle-piercing window step, which is arranged after step 7). Specifically, the needle-piercing window step comprises: photolithography and development are respectively performed on the surface of the source electrode (5) and the surface of the drain electrode (6) to form a needle-piercing window, and SiN is etched in the needle-piercing window on the surface of the source electrode (5). x The insulating layer (11) forms a pinning area for the source electrode (5), and SiN is etched in the pinning window on the surface of the drain electrode (6). x The insulating layer (11) forms a drain electrode (6) puncture area.

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