GaN-based transistor and preparation method thereof, power amplifier and communication equipment
By introducing P-type element doping into the barrier layer of the GaN-based transistor, the Schottky barrier height between the gate and barrier layer is improved, and the problem of high gate leakage current of the existing GaN-based transistor is solved, and the improvement of the Its reliability and efficiency.
Patent Information
- Application Number
- CN202310802330.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-30
- Publication Date
- 2024-12-31
AI Technical Summary
Due to the high gate leakage of the existing GaN-based transistor, its reliability is reduced and its efficiency is affected, and it is difficult for the existing structure to effectively suppress gate leakage.
By introducing P-type element doping into the barrier layer, a first doping region is formed, so that the Schottky barrier height of the contact region between the gate and the barrier layer is increased, thereby reducing the gate leakage current.
It effectively reduces the gate leakage current of GaN-based transistors, and improves its reliability and efficiency.
Smart Images
Figure CN119230617A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of electronic components, and in particular to a GaN-based transistor and a preparation method thereof, a power amplifier, and a communication device. Background Art
[0002] GaN-based transistors are mainly used in power amplifier modules in high-frequency and high-power communication systems. Current GaN-based transistors mainly use the Schottky barrier height formed by metal-semiconductor contact to adjust the control gate leakage, and most use Ni / Au or W / Au as the gate metal. The disadvantage of this structure is that the barrier height formed between the Ni metal and the non-intentionally doped AlGaN barrier layer is still relatively low and fixed, making it difficult to significantly suppress gate leakage.
[0003] Higher gate leakage reduces the reliability of GaN power amplifiers and also has a certain impact on the efficiency of GaN power amplifiers. In addition, there are three paths for gate leakage: leakage in the two-dimensional electron gas channel after passing through the barrier layer, leakage through the surface state between the gate and the source, and leakage through the surface state between the gate and the drain. Therefore, higher gate leakage also puts forward higher requirements for the preparation of the passivation layer. Summary of the invention
[0004] An embodiment of the present disclosure provides a GaN-based transistor, which includes a substrate, a barrier layer arranged on the substrate, and a gate arranged on the side of the barrier layer away from the substrate; the gate contacts the barrier layer to form a Schottky layer; it is characterized in that the barrier layer has a first doped region, the orthographic projection of the gate on the substrate is located within the orthographic projection of the first doped region of the barrier layer on the substrate; wherein the first doped region of the barrier layer is doped with a P-type element.
[0005] In some embodiments, an orthographic projection of the gate on the substrate completely overlaps with an orthographic projection of the first doped region of the barrier layer on the substrate.
[0006] In some embodiments, the GaN-based transistor also includes a buffer layer and a channel layer sequentially arranged on a side of the substrate close to the barrier layer, and a source and a drain arranged on a side of the channel layer away from the substrate; wherein the source and the drain are electrically connected to the source contact area and the drain contact area of the channel layer, respectively, and the orthographic projections of the source and the drain on the substrate have no overlap with the orthographic projections of the first doped region on the substrate.
[0007] In some embodiments, the GaN-based transistor further includes a nucleation layer disposed between the buffer layer and the substrate.
[0008] In some embodiments, the GaN-based transistor further includes a passivation layer disposed on a side of the layer where the gate, the source, and the drain are located away from the substrate.
[0009] In some embodiments, the P-type element includes any one of Mg, Be, Zn, C, and Cd.
[0010] In some embodiments, the material of the barrier layer is selected from any one of AlGaN, AlInN, AlN, InAlGaN, and AlScN.
[0011] In some embodiments, the material of the channel layer includes any one of GaN, InGaN, and AlGaN with low aluminum content.
[0012] An embodiment of the present disclosure provides a method for preparing a GaN-based transistor, which includes providing a substrate, sequentially forming barrier layers on the substrate, and forming a gate on a side of the barrier layer away from the substrate; the gate contacts the barrier layer to form a Schottky; characterized in that the preparation method also includes: doping a first doped region of the barrier layer with a P-type element, and the orthographic projection of the gate on the substrate is located within the orthographic projection of the first doped region of the barrier layer on the substrate.
[0013] In some embodiments, the step of doping the first doped region of the barrier layer with a P-type element comprises:
[0014] The re-growth of the P-type element is completed in the first doping region of the barrier layer by using a re-growth method based on a vapor phase epitaxial growth MOCVD system, and high temperature annealing is performed to activate the P-type element.
[0015] In some embodiments, the step of using a regrowth method based on a vapor phase epitaxial growth MOCVD system to complete the regrowth of a P-type element in the first doping region of the barrier layer, and performing high temperature annealing to activate the P-type element includes:
[0016] Forming a sacrificial layer on a side of the barrier layer away from the substrate, and forming a first opening at a position of the sacrificial layer corresponding to the first doping region through a patterning process;
[0017] removing the barrier layer material at the position of the first doping region of the barrier layer;
[0018] The regrowth of the barrier layer material doped with the P-type element is completed in the first doping region of the barrier layer by using a regrowth method based on an MOCVD system, and high temperature annealing is performed to activate the P-type element;
[0019] The remaining sacrificial layer material is removed.
[0020] In some embodiments, the step of doping the first doped region of the barrier layer with a P-type element comprises:
[0021] A high energy particle implantation device is used to perform P-type element doping in the first doping region of the barrier layer.
[0022] In some embodiments, before forming the buffer layer, the method further includes: forming a nucleation layer on the substrate.
[0023] In some embodiments, the method for preparing the GaN-based transistor further includes forming a passivation layer on a side of the gate, the source, and the drain facing away from the substrate.
[0024] In some embodiments, the P-type element includes any one of Mg, Be, Zn, C, and Cd.
[0025] An embodiment of the present disclosure provides a power amplifier, characterized by comprising any of the above-mentioned GaN-based transistors.
[0026] An embodiment of the present disclosure provides a communication device, which includes the above-mentioned power amplifier.
[0027] In the GaN-based transistor in the disclosed embodiment, the first doped region of the barrier layer only corresponds to the position of the gate. By doping the first doped region with P-type elements, although the band gap width of the first doped region of the barrier layer is the same as that of the other regions, the overall energy level of the barrier layer is pulled upward, the bottom of the conduction band is farther from the Fermi level, and the top of the valence band is closer to the Fermi level. Doping the first doped region with P-type elements obviously leads to an increase in the height of the gate Schottky barrier, which increases the difficulty for electrons in the gate to jump from the barrier height to the barrier layer, thereby effectively reducing the gate leakage current of the GaN-based transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a cross-sectional view of a GaN power amplifier transistor according to an embodiment of the present disclosure;
[0029] Figure 2 is a gate energy band diagram of a GaN power amplifier transistor in an embodiment of the present disclosure;
[0030] Figure 3 is a cross-sectional view of another GaN power amplifier transistor according to an embodiment of the present disclosure;
[0031] Figure 4 is a cross-sectional view of an intermediate product formed in step S11 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0032] Figure 5is a cross-sectional view of an intermediate product formed in step S12 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0033] Figure 6 is a cross-sectional view of an intermediate product formed in step S13 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0034] Figure 7 is a cross-sectional view of an intermediate product formed in step S14 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0035] Figure 8 is a cross-sectional view of an intermediate product formed in step S15 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0036] Fig. 9 is a cross-sectional view of an intermediate product formed in step S16 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0037] Fig.10 is a cross-sectional view of an intermediate product formed in step S17 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0038] Fig.11 is a cross-sectional view of an intermediate product formed in step S18 of the method for manufacturing a GaN power amplifier transistor according to the present embodiment;
[0039] Fig.12 It is a cross-sectional view of an intermediate product formed in step S19 of the method for manufacturing the GaN power amplifier transistor of the present embodiment. DETAILED DESCRIPTION
[0040] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0041] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0042] Before describing the GaN-based transistor of the disclosed embodiment, it should be noted that the material of the channel layer of the GaN-based transistor can be all N-group alloy materials, including but not limited to GaN, InGaN, AlGaN with low aluminum components and other GaN-based materials. In the disclosed embodiment, only GaN is used as the material of the channel layer for illustration, but it should be understood that this does not constitute a limitation on the scope of protection of the disclosed embodiment. When GaN is used as the material of the channel layer, the GaN-based transistor can specifically be a GaN power amplifier transistor. The GaN power amplifier transistor and its preparation method in the disclosed embodiment are described in detail below.
[0043] Figure 1 is a cross-sectional view of a GaN power amplifier transistor according to an embodiment of the present disclosure; Figure 1 As shown, the embodiment of the present disclosure provides a GaN power amplifier transistor, which includes a substrate 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 arranged on the substrate 1 in sequence, and a gate 5, a source 6, and a drain 7 arranged on the side of the barrier layer 4 away from the substrate 1. The source 6 and the drain 7 are electrically connected to the source contact area and the drain contact area of the channel layer 3, respectively, that is, the source 6 and the drain 7 form ohmic contacts with the source contact area and the drain contact area of the channel layer 3, respectively. The gate 5 contacts the barrier layer 4 to form a Schottky. In the embodiment of the present disclosure, the barrier layer 4 has a first doped region 41, and the orthographic projection of the gate 5 on the substrate 1 is located within the orthographic projection of the first doped region 41 of the barrier layer 4 on the substrate 1, and the orthographic projections of the source 6 and the drain 7 on the substrate 1 do not overlap with the orthographic projections of the first doped region 41 of the barrier layer 4 on the substrate 1; wherein, the first doped region 41 of the barrier layer 4 is doped with a P-type element.
[0044] In the disclosed embodiment, the first doped region 41 of the barrier layer 4 only corresponds to the position where the gate 5 is located. By doping the first doped region 41 with a P-type element, the gate 5 forms a Schottky with the first doped region 41 doped with the P-type element. At this time, although the bandgap width of the first doped region 41 of the barrier layer 4 is the same as that of the other regions, the overall energy level of the barrier layer 4 is pulled upward, the bottom of the conduction band is farther from the Fermi level, and the top of the valence band is closer to the Fermi level. Figure 2 As shown by the middle dotted line, the doping of the first doped region 41 with P-type elements obviously increases the Schottky barrier height of the gate 5, making it more difficult for electrons in the gate 5 to transition from the barrier height to the barrier layer 4, thereby effectively reducing the gate 5 leakage current of the GaN power amplifier transistor.
[0045] In some examples, continue to refer to Figure 1 The orthographic projection of the gate 5 of the GaN power amplifier transistor on the substrate 1 completely overlaps with the orthographic projection of the first doped region 41 of the barrier layer 4 on the substrate 1, that is, the gate 5 of the GaN power amplifier transistor completely corresponds to the first doped region 41 of the barrier layer 4. At this time, the Schottky barrier height of the gate 5 can be maximized, making it more difficult for electrons in the gate 5 to transition from the barrier height to the barrier layer 4, thereby effectively reducing the gate 5 leakage current of the GaN power amplifier transistor.
[0046] In some examples, Figure 3 is a cross-sectional view of another GaN power amplifier transistor according to an embodiment of the present disclosure; Figure 3 As shown, the GaN power amplifier transistor not only includes the above structure, but also includes a nucleation layer 9 arranged between the buffer layer 2 and the substrate 1. The nucleation layer 9 provides nucleation seeds for the subsequent growth of GaN crystals, reduces the lattice structure difference between the substrate and the subsequent crystals, and modulates the stress and defect density of the subsequent crystals.
[0047] Furthermore, the material of the nucleation layer 9 can be selected from GaN or AlGaN.
[0048] In some examples, the buffer layer 2 in the embodiments of the present disclosure may be made of the same material as the nucleation layer 9 , that is, GaN or AlGaN may also be used.
[0049] In some examples, the source 6 of the GaN power amplifier transistor can be electrically connected to the source contact area of the channel layer 3 through a first connection via, and the drain 7 can be electrically connected to the drain contact area of the channel layer 3 through a second connection via. The first connection via and the second connection via both penetrate the barrier layer 4. That is, the source 6 and the drain 7 of the GaN power amplifier transistor can be electrically connected to the channel layer 3 by forming the first connection via and the second connection via through the barrier layer 4.
[0050] In some examples, the barrier layer 4 of the GaN power amplifier transistor includes not only the first doping region 41, but also the second doping region and the second doping region respectively arranged on both sides of the first doping region 41, wherein the second doping region at least partially overlaps with the orthographic projection of the source contact region of the channel layer 3 on the substrate 1, and the third doping region at least partially overlaps with the orthographic projection of the drain contact region of the channel layer 3 on the substrate 1. In this case, by ion implantation of the second doping region and the second doping region of the barrier layer 4, the ohmic contact region of the source 6 and the ohmic contact region of the drain 7 are formed, at which time the source 6 can be electrically connected to the source contact region of the channel layer 3 through the ohmic contact region of the source 6, and the drain 7 can be electrically connected to the drain contact region of the channel layer 3 through the ohmic contact region of the drain 7.
[0051] In some examples, continue to refer to Figure 3 The GaN power amplifier transistor in the embodiment of the present disclosure not only includes the above structure, but also includes a passivation layer 8 disposed on the side of the gate 5, source 6 and drain 7 away from the substrate 1. In the embodiment of the present disclosure, the passivation layer 8 disposed on the surface of the gate 5, source 6 and drain 7, and the barrier layer 4 away from the substrate 1 can not only protect the tube core, isolate water vapor, etc., but also suppress the influence of the semiconductor surface state. Among them, the material of the passivation layer 8 includes but is not limited to silicon nitride SiN.
[0052] In some examples, the source 6 and drain 7 of the GaN power amplifier transistor of the embodiment of the present disclosure can both adopt a single film layer structure composed of metal materials, or a composite film layer structure composed of metal materials. For example, the materials of the source 6 and drain 7 include but are not limited to a metal combination of Ti / Al / Ni / Au or Ti / Al / Mo / Au.
[0053] In some examples, the gate 5 of the GaN power amplifier transistor of the embodiment of the present disclosure may adopt a single film layer structure composed of metal materials, or a composite film layer structure composed of metal materials. For example, the material of the gate 5 includes but is not limited to a high work function metal combination such as Ni / Au.
[0054] In some examples, the source 6 is closer to the gate 5 than the drain 7. The reason for this arrangement is that the voltage applied to the drain 7 during application is relatively large, which will cause leakage between the side wall of the gate 5 and the drain 7. By increasing the distance between the drain 7 and the gate 5, the occurrence of this problem can be alleviated.
[0055] In some examples, the material of the barrier layer 4 of the embodiment of the present disclosure is selected from all N-group alloy barrier materials, specifically including but not limited to GaN-based barrier materials such as AlGaN, AlInN, AlN, InAlGaN, and AlScN. In the embodiment of the present disclosure, only AlGaN is used as the material of the barrier layer 4 as an example, but it should be understood that this does not constitute a limitation on the protection scope of the embodiment of the present disclosure.
[0056] In some examples, the material of the substrate 1 of the embodiments of the present disclosure includes, but is not limited to, sapphire, silicon carbide, silicon, or gallium nitride bulk material.
[0057] In some examples, the P-type element doped in the first doping region 41 of the barrier layer 4 of the embodiment of the present disclosure includes, but is not limited to, Mg, Be, Zn, C, Cd, etc. Regardless of any of the aforementioned elements doped in the first doping region 41 of the barrier layer 4, the potential barrier of the gate 5 can be improved and the leakage current of the gate 5 can be reduced. In the following preparation method of the embodiment of the present disclosure, only Mg is used as an example of the P-type element doped in the barrier layer 4.
[0058] The present disclosure provides a method for preparing a GaN power amplifier transistor, which can be used to prepare the above-mentioned GaN power amplifier transistor. The method for preparing the GaN power amplifier transistor of the present disclosure embodiment includes providing a substrate 1, sequentially forming a buffer layer 2, a channel layer 3, and a barrier layer 4 on the substrate 1, and forming a gate 5, a source 6, and a drain 7 on the side of the barrier layer 4 away from the substrate 1; the gate 5 contacts the barrier layer 4 to form a Schottky; the source 6 and the drain 7 are electrically connected to the source contact area and the drain contact area of the channel layer 3, respectively. In particular, the method for preparing the GaN power amplifier transistor of the present disclosure embodiment also includes: doping the first doped region 41 of the barrier layer 4 with a P-type element. Among them, the orthographic projection of the gate 5 on the substrate 1 is located within the orthographic projection of the first doped region 41 of the barrier layer 4 on the substrate 1, and the orthographic projections of the source 6 and the drain 7 on the substrate 1 do not overlap with the orthographic projections of the first doped region 41 of the barrier layer 4 on the substrate 1.
[0059] In the disclosed embodiment, the first doped region 41 of the barrier layer 4 only corresponds to the position where the gate 5 is located. In the preparation method of the GaN power amplifier transistor, by doping the first doped region 41 with a P-type element, although the band gap width of the first doped region 41 of the barrier layer 4 is the same as that of the remaining regions, the overall energy level of the barrier layer 4 is pulled upward, the bottom of the conduction band is farther from the Fermi level, and the top of the valence band is closer to the Fermi level, such as Figure 2 As shown by the middle dotted line, the doping of the first doped region 41 with P-type elements obviously increases the Schottky barrier height of the gate 5, making it more difficult for electrons in the gate 5 to transition from the barrier height to the barrier layer 4, thereby effectively reducing the gate 5 leakage current of the GaN power amplifier transistor.
[0060] In some examples, the preparation method in the embodiment of the present disclosure not only includes the above steps, but also includes forming a nucleation layer 9 on the substrate 1 before forming the buffer layer 2. By forming the nucleation layer 9 on the substrate 1, a nucleation seed is provided for the subsequent growth of GaN crystals, and the lattice structure difference between the substrate and the subsequent grown crystals is reduced, and the stress and defect density of the subsequent crystals are modulated.
[0061] In some examples, the preparation method in the embodiment of the present disclosure not only includes the above steps, but also includes forming a passivation layer 8 after forming the gate 5, the source 6 and the drain 7. By forming the passivation layer 8, not only can the die be protected, moisture can be isolated, etc., but also the influence of the semiconductor surface state can be suppressed.
[0062] In order to make the preparation method of the GaN power amplifier transistor of the embodiment of the present disclosure clearer, the preparation method of the embodiment of the present disclosure is described below with reference to specific examples.
[0063] First example: Take the case where the barrier layer 4 in the GaN power amplifier transistor is AlGaN and the P-type element doped in the first doping region 41 of the barrier layer 4 is Mg as an example. The preparation method of the GaN power amplifier transistor in the first example specifically includes the following steps:
[0064] S11, providing a substrate 1, depositing a nucleation layer 9, a buffer layer 2, a channel layer 3 and a barrier layer 4 in sequence on the substrate 1 to form an epitaxial substrate, and cleaning the epitaxial substrate. Figure 4 is a cross-sectional view of an intermediate product formed in step S11 of the method for preparing the GaN power amplifier transistor of the present embodiment; Figure 4 shown.
[0065] S12 , forming a sacrificial layer 10 on the side of the barrier layer 4 facing away from the substrate 1 . Figure 5 is a cross-sectional view of an intermediate product formed in step S12 of the method for preparing the GaN power amplifier transistor of the present embodiment; Figure 5 shown.
[0066] In some examples, the sacrificial layer 10 may be made of a passivation dielectric material, for example, the material of the sacrificial layer 10 includes but is not limited to SiN. In this case, step S12 may specifically include forming a passivation dielectric material as the sacrificial layer 10 by using a low pressure chemical vapor deposition (LPCVD) method or a metal-organic chemical vapor deposition (MOCVD) method.
[0067] S13, applying photoresist on the side of the sacrificial layer 10 away from the substrate 1, and selectively exposing the photoresist to remove the photoresist corresponding to the first doped region 41 of the barrier layer 4 (the position where the gate 5 is to be formed), and retaining the photoresist at the remaining positions. Figure 6 is a cross-sectional view of an intermediate product formed in step S13 of the method for preparing the GaN power amplifier transistor of the present embodiment; Figure 6 shown.
[0068] S14 , removing the material of the sacrificial layer 10 at the position without the photoresist, that is, forming a first opening in the sacrificial layer 10 . Figure 7 is a cross-sectional view of an intermediate product formed in step S14 of the method for preparing the GaN power amplifier transistor of the present embodiment; Figure 7 shown.
[0069] S15 , removing the remaining photoresist by organic cleaning, and removing the barrier layer 4 material in the first doped region 41 of the barrier layer 4 by an ICP dry etching system. Figure 8 is a cross-sectional view of an intermediate product formed in step S15 of the method for preparing the GaN power amplifier transistor of the present embodiment; Figure 8 shown.
[0070] S16, using organic cleaning and inorganic cleaning to remove etching residues, and after cleaning, using a regrowth method to complete the regrowth of the barrier layer 4 material (AlGaN material) doped with Mg element in the first doping region 41 of the barrier layer 4 based on the MOCVD system, and performing high-temperature annealing to activate Mg ions. Fig. 9 is a cross-sectional view of an intermediate product formed in step S16 of the method for preparing the GaN power amplifier transistor of the present embodiment; Fig. 9 shown.
[0071] S17, removing the sacrificial layer 10 by inorganic cleaning. Fig.10 is a cross-sectional view of an intermediate product formed in step S17 of the method for preparing the GaN power amplifier transistor of the present embodiment; Fig.10 shown.
[0072] S18 , forming a source electrode 6 and a drain electrode 7 , so that the source electrode 6 and the drain electrode 7 are electrically connected to the source contact region and the drain contact region of the channel layer 3 , respectively. Fig.11 is a cross-sectional view of an intermediate product formed in step S18 of the method for preparing the GaN power amplifier transistor of the present embodiment; Fig.11 shown.
[0073] In some examples, step S18 may include patterning the positions corresponding to the source contact area and the drain contact area of the barrier layer 4 and the channel layer 3 to form a first connection via and a second connection via that penetrate the barrier layer 4, and the source 6 and the drain 7 are electrically connected to the source contact area and the drain contact area of the channel layer 3 through the first connection via and the second connection via, respectively. Of course, step S18 may also include ion implantation of the positions corresponding to the source contact area and the drain contact area of the barrier layer 4 and the channel layer 3 to form an ohmic contact area of the source 6 and an ohmic contact area of the drain 7, and then forming the source 6 and the drain 7, at which time the source 6 can be electrically connected to the source contact area of the channel layer 3 through the ohmic contact area of the source 6, and the drain 7 can be electrically connected to the drain contact area of the channel layer 3 through the ohmic contact area of the drain 7. The source 6 and the drain 7 may be formed by depositing a Ti / Al / Ni / Au metal layer, then patterning, and performing high temperature annealing to form the source 6 and the drain 7.
[0074] S19, forming a gate 5. Fig.12 is a cross-sectional view of an intermediate product formed in step S19 of the method for preparing the GaN power amplifier transistor of the present embodiment; Fig.12 shown.
[0075] In some examples, S19 may include depositing a Ni / Au metal layer, followed by patterning to form a pattern of the gate 5 , the gate 5 is in contact with the first doped region 41 of the barrier layer 4 to form a Schottky, and thus the preparation of the gate 5 is completed.
[0076] S110, forming a passivation layer 8 on the substrate 1 after completing the above steps, such as Figure 3 shown.
[0077] In some examples, step S110 may include depositing the passivation layer 8 using a plasma enhanced chemical vapor deposition (PECVD) method or an atomic deposition ALD system.
[0078] At this point, the preparation of the GaN power amplifier transistor is completed. It should be noted that, according to the application of the device, after forming the passivation layer 8, a through hole for device connection can be formed. The preparation order of the above steps S18 and S19 can be interchanged.
[0079] Second example: Take the case where the barrier layer 4 in the GaN power amplifier transistor is AlGaN and the P-type element doped in the first doping region 41 of the barrier layer 4 is Mg as an example. The preparation method of the GaN power amplifier transistor in the first example specifically includes the following steps:
[0080] S21, providing a substrate 1, depositing a nucleation layer 9, a buffer layer 2, a channel layer 3 and a barrier layer 4 in sequence on the substrate 1 to form an epitaxial substrate, and cleaning the epitaxial substrate.
[0081] S22 , forming a sacrificial layer 10 on the side of the barrier layer 4 facing away from the substrate 1 .
[0082] In some examples, the sacrificial layer 10 may be made of a passivation dielectric material, for example, the material of the sacrificial layer 10 includes but is not limited to SiN. In this case, step S12 may specifically include forming a passivation dielectric material as the sacrificial layer 10 by using a low pressure chemical vapor deposition (LPCVD) method or a metal-organic chemical vapor deposition (MOCVD) method.
[0083] S23, photoresist is applied on the side of the sacrificial layer 10 away from the substrate 1, and the photoresist is selectively exposed to remove the photoresist corresponding to the first doped region 41 of the barrier layer 4 (the position where the gate 5 is to be formed), and the photoresist at the remaining positions is retained.
[0084] S24, removing the material of the sacrificial layer 10 at the position without the photoresist.
[0085] S25 , using a high-energy particle implantation device to implant Mg particles into the first doping region 41 of the barrier layer 4 .
[0086] S26 , removing the sacrificial layer 10 by inorganic cleaning.
[0087] S27 , activating the ion-implanted Mg particles in a high-temperature environment, so that the (AlGaN) material of the first doping region 41 of the barrier layer 4 exhibits P-type characteristics.
[0088] S28 , forming a source electrode 6 and a drain electrode 7 , so that the source electrode 6 and the drain electrode 7 are electrically connected to the source contact region and the drain contact region of the channel layer 3 , respectively.
[0089] In some examples, step S28 may include patterning the positions corresponding to the source contact area and the drain contact area of the barrier layer 4 and the channel layer 3 to form a first connection via and a second connection via that penetrate the barrier layer 4, and the source 6 and the drain 7 are electrically connected to the source contact area and the drain contact area of the channel layer 3 through the first connection via and the second connection via, respectively. Of course, step S28 may also include ion implantation of the positions corresponding to the source contact area and the drain contact area of the barrier layer 4 and the channel layer 3 to form an ohmic contact area of the source 6 and an ohmic contact area of the drain 7, and then forming the source 6 and the drain 7, at which time the source 6 can be electrically connected to the source contact area of the channel layer 3 through the ohmic contact area of the source 6, and the drain 7 can be electrically connected to the drain contact area of the channel layer 3 through the ohmic contact area of the drain 7. The source 6 and the drain 7 may be formed by depositing a Ti / Al / Ni / Au metal layer, then patterning, and high-temperature annealing to form the source 6 and the drain 7.
[0090] S29, forming a gate 5.
[0091] In some examples, S29 may include depositing a Ni / Au metal layer, followed by patterning to form a pattern of the gate 5 , the gate 5 is in contact with the first doped region 41 of the barrier layer 4 to form a Schottky, and thus the preparation of the gate 5 is completed.
[0092] S210 , forming a passivation layer 8 on the base substrate 1 after completing the above steps.
[0093] In some examples, step S210 may include depositing the passivation layer 8 using a plasma enhanced chemical vapor deposition (PECVD) method or an atomic deposition ALD system.
[0094] At this point, the preparation of the GaN power amplifier transistor is completed. It should be noted that, according to the application of the device, after forming the passivation layer 8, a through hole for device connection may be formed. The preparation order of the above steps S28 and S29 may be interchangeable.
[0095] The disclosed embodiment also provides a power amplifier, which may include the above-mentioned GaN-based transistor. Among them, the first doped region of the barrier layer of the GaN-based transistor only corresponds to the position where the gate is located. By doping the first doped region with P-type elements, although the bandgap width of the first doped region of the barrier layer is the same as that of the remaining regions, the overall energy level of the barrier layer is pulled upward, the bottom of the conduction band is farther away from the Fermi level, and the top of the valence band is closer to the Fermi level. The doping of the first doped region with P-type elements obviously leads to an increase in the height of the gate Schottky barrier, which increases the difficulty for electrons in the gate to jump to the barrier layer at the barrier height, thereby effectively reducing the gate leakage current of the GaN-based transistor, thereby making the performance of the power amplifier better.
[0096] An embodiment of the present disclosure also provides a communication device, which includes the above-mentioned power amplifier.
[0097] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.
Claims
1. A GaN-based transistor, comprising a substrate, a barrier layer disposed on the substrate, and a gate disposed on a side of the barrier layer away from the substrate; the gate contacts the barrier layer to form a Schottky structure; characterized in that: The barrier layer has a first doped region, and the orthographic projection of the gate on the substrate is located within the orthographic projection of the first doped region of the barrier layer on the substrate; wherein the first doped region of the barrier layer is doped with a P-type element.
2. The GaN-based transistor according to claim 1, characterized in that: The orthographic projection of the gate on the substrate completely overlaps with the orthographic projection of the first doped region of the barrier layer on the substrate.
3. The GaN-based transistor according to claim 1, characterized in that: It also includes a buffer layer and a channel layer which are sequentially arranged on the side of the substrate close to the barrier layer, and a source and a drain which are arranged on the side of the channel layer away from the substrate; wherein the source and the drain are electrically connected to the source contact area and the drain contact area of the channel layer, respectively, and the orthographic projections of the source and the drain on the substrate have no overlap with the orthographic projections of the first doped region on the substrate.
4. The GaN-based transistor according to claim 3, characterized in that: Also included is a nucleation layer disposed between the buffer layer and the substrate.
5. The GaN-based transistor according to claim 3, characterized in that: It also includes a passivation layer arranged on a side of the layer where the gate, the source and the drain are located away from the substrate.
6. The GaN-based transistor according to claim 1, characterized in that: The P-type element includes any one of Mg, Be, Zn, C, and Cd.
7. The GaN-based transistor according to claim 1, characterized in that: The material of the barrier layer is selected from any one of AlGaN, AlInN, AlN, InAlGaN and AlScN.
8. The GaN-based transistor according to claim 3, characterized in that: The material of the channel layer includes any one of GaN, InGaN, and AlGaN with low aluminum content.
9. A method for preparing a GaN-based transistor, characterized in that: The method comprises providing a substrate, sequentially forming barrier layers on the substrate, and forming a gate on a side of the barrier layer away from the substrate; The gate contacts the barrier layer to form a Schottky layer; characterized in that the preparation method also includes: doping the first doped region of the barrier layer with a P-type element, and the orthographic projection of the gate on the substrate is located within the orthographic projection of the first doped region of the barrier layer on the substrate.
10. The preparation method according to claim 9, characterized in that: The step of doping the first doped region of the barrier layer with a P-type element comprises: The re-growth of the P-type element is completed in the first doping region of the barrier layer by using a re-growth method based on a vapor phase epitaxial growth MOCVD system, and high temperature annealing is performed to activate the P-type element.
11. The method for preparing a GaN-based transistor according to claim 10, characterized in that: The step of using a regrowth method based on a vapor phase epitaxial growth MOCVD system to complete the regrowth of a P-type element in the first doping region of the barrier layer, and performing high temperature annealing to activate the P-type element includes: Forming a sacrificial layer on a side of the barrier layer away from the substrate, and forming a first opening at a position of the sacrificial layer corresponding to the first doping region through a patterning process; removing the barrier layer material at the position of the first doping region of the barrier layer; The regrowth of the barrier layer material doped with the P-type element is completed in the first doping region of the barrier layer by using a regrowth method based on an MOCVD system, and high temperature annealing is performed to activate the P-type element; The remaining sacrificial layer material is removed.
12. The preparation method according to claim 9, characterized in that: The step of doping the first doped region of the barrier layer with a P-type element comprises: A high energy particle implantation device is used to perform P-type element doping in the first doping region of the barrier layer.
13. The preparation method according to any one of claims 8 to 12, characterized in that: The P-type element includes any one of Mg, Be, Zn, C, and Cd.
14. A power amplifier, characterized in that: A GaN-based transistor comprising the GaN-based transistor as described in any one of claims 1 to 8.
15. A communication device, characterized in that: Comprising the power amplifier as claimed in claim 14.