Substrate, preparation method thereof and light-emitting diode chip

Abstract

The embodiment of the invention provides a substrate, a preparation method thereof and a light-emitting diode chip, and belongs to the technical field of semiconductors. The substrate comprises a first sapphire layer and a plurality of protrusions located on the first surface of the first sapphire layer, each protrusion comprises a main body and a silicon dioxide layer, the main body and the silicon dioxide layer are sequentially stacked in the direction away from the first sapphire layer, and the silicon dioxide layer covers the top face and at least part of the side wall of the main body. The top surface is the surface of the main body away from the first surface, and at least part of the side wall is connected with the top surface. According to the embodiment of the invention, the luminous efficiency of the LED chip can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a substrate and a preparation method thereof, and a light emitting diode chip. Background Art

[0002] Light Emitting Diode (LED) has been widely used in various light source fields such as backlight, lighting, and landscape due to its small size, long service life, rich colors, and low energy consumption. LED chips usually include a substrate and a light-emitting structure located on the surface of the substrate.

[0003] In the related art, the substrate includes a sapphire substrate body and a plurality of protrusions located on the surface of the sapphire substrate body, wherein the bottom of the protrusions is a sapphire layer.

[0004] However, among the light emitted by the light-emitting structure, the total reflection angle of the interface between the light-emitting structure and the side wall of the sapphire layer at the bottom position of the protrusion is relatively large, and only a small part of the light with a large incident angle will be totally reflected at the interface of the side wall at the bottom position, thereby affecting the reflectivity of the substrate to the light and affecting the luminous efficiency of the LED chip. Summary of the invention

[0005] The embodiments of the present disclosure provide a substrate and a preparation method thereof, and a light-emitting diode chip, which can improve the light-emitting efficiency of the LED chip. The technical solution is as follows:

[0006] On the one hand, a substrate is provided, comprising a first sapphire layer and a plurality of protrusions located on a first surface of the first sapphire layer, the protrusions comprising a main body and a silicon dioxide layer, the main body and the silicon dioxide layer being stacked in sequence in a direction away from the first sapphire layer, the silicon dioxide layer covering a top surface and at least a portion of a side wall of the main body, the top surface being a surface of the main body away from the first surface, and the at least a portion of the side wall being connected to the top surface.

[0007] Optionally, the main body includes a second sapphire layer and a first distributed Bragg reflection (DBR) layer stacked in sequence in a direction away from the first sapphire layer, and the silicon dioxide layer covers the first DBR layer.

[0008] Optionally, the first DBR layer covers the second sapphire layer and is connected to the first surface, and the silicon dioxide layer is connected to the first surface.

[0009] Optionally, the silicon dioxide layer is connected to the second sapphire layer, and an orthographic projection of the silicon dioxide layer on the first surface is located inside an orthographic projection of the second sapphire layer on the first surface.

[0010] Optionally, a minimum distance between any point on an outer contour of an orthographic projection of the second sapphire layer on the first surface and an outer contour of an orthographic projection of the first DBR layer on the first surface is 0.1 μm to 0.5 μm.

[0011] Optionally, a minimum distance between any point on an outer contour of an orthographic projection of the first DBR layer on the first surface and an outer contour of an orthographic projection of the silicon dioxide layer on the first surface is 0.1 μm to 0.5 μm.

[0012] Optionally, the main body is a second sapphire layer, and the silicon dioxide layer covers the second sapphire layer and is connected to the first surface.

[0013] Optionally, a minimum distance between any point on an outer contour of an orthographic projection of the second sapphire layer on the first surface and an outer contour of an orthographic projection of the silicon dioxide layer on the first surface is 0.1 μm to 0.5 μm.

[0014] On the other hand, a method for preparing a substrate is provided, comprising: providing a first sapphire layer; forming a plurality of protrusions on a first surface of the first sapphire layer, the protrusions comprising a main body and a silicon dioxide layer, the main body and the silicon dioxide layer being stacked in sequence in a direction away from the first sapphire layer, the silicon dioxide layer covering a top surface and at least a portion of a side wall of the main body, the top surface being a surface of the main body away from the first surface, and the at least a portion of the side wall being connected to the top surface.

[0015] On the other hand, a light-emitting diode chip is provided, comprising a substrate and a light-emitting structure, wherein the substrate is any of the aforementioned substrates, and the light-emitting structure is located on the surface of the plurality of protrusions.

[0016] The technical solution provided by the embodiments of the present disclosure has the following beneficial effects:

[0017] In the disclosed embodiment, the protrusion includes a main body and a silicon dioxide layer, the main body and the silicon dioxide layer are stacked in sequence in a direction away from the first sapphire layer, the silicon dioxide layer covers the top surface of the main body and at least part of the side wall, the top surface is the surface of the main body away from the first surface, and at least part of the side wall is connected to the top surface, so that after the light-emitting structure is formed on the surface of the plurality of protrusions, the interface between the light-emitting structure and the part of the side wall at the bottom position of the protrusion is the interface between the light-emitting structure and the silicon dioxide layer. Compared with the sapphire material, the refractive index of the light-emitting structure is larger, and the refractive index of the silicon dioxide layer is smaller, that is, the refractive index difference between the light-emitting structure and the silicon dioxide layer is larger. Since when the light enters the film layer with a higher refractive index from the film layer with a lower refractive index, the greater the refractive index difference of the film layer, the smaller the total reflection angle, so the total reflection angle of the interface between the light-emitting structure and the silicon dioxide layer is smaller, and when the light emitted by the light-emitting structure is emitted from the light-emitting structure to the protrusion, more light with a small incident angle will be totally reflected on the side wall at the bottom position of the protrusion, thereby improving the reflectivity of the substrate to the light and improving the luminous efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a structural schematic diagram of an LED chip in the related art;

[0020] Figure 2 is a schematic structural diagram of a substrate provided by an embodiment of the present disclosure;

[0021] Figure 3 is a schematic diagram of the structure of an LED chip provided by an embodiment of the present disclosure;

[0022] Figure 4 is a schematic structural diagram of another substrate provided by an embodiment of the present disclosure;

[0023] Figure 5 is a schematic structural diagram of another LED chip provided by an embodiment of the present disclosure;

[0024] Figure 6 is a schematic structural diagram of another substrate provided by an embodiment of the present disclosure;

[0025] Figure 7 is a structural schematic diagram of another LED chip provided by an embodiment of the present disclosure;

[0026] Figure 8is a flow chart of a method for preparing a substrate provided by an embodiment of the present disclosure;

[0027] Fig. 9 is a flow chart of another method for preparing a substrate provided by an embodiment of the present disclosure;

[0028] Fig.10 is a structural schematic diagram of a substrate preparation process provided by an embodiment of the present disclosure;

[0029] Fig.11 is a structural schematic diagram of a substrate preparation process provided by an embodiment of the present disclosure;

[0030] Fig.12 is a flow chart of another method for preparing a substrate provided by an embodiment of the present disclosure;

[0031] Fig.13 is a structural schematic diagram of a substrate preparation process provided by an embodiment of the present disclosure;

[0032] Fig.14 is a structural schematic diagram of a substrate preparation process provided by an embodiment of the present disclosure;

[0033] Fig.15 This is a flow chart of another method for preparing a substrate provided in an embodiment of the present disclosure.

[0034] Reference numerals:

[0035] 1: initial sapphire substrate; 2: photoresist layer; 10: first sapphire layer; 11: first surface; 12: second surface; 20: protrusion; 21: second sapphire layer; 22: first DBR layer; 23: silicon dioxide layer; 23a: initial silicon dioxide layer; 30: light-emitting structure; 31: first semiconductor layer; 32: light-emitting layer; 33: second semiconductor layer; 40: second DBR layer. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0037] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Figure 1 Schematic diagram of the structure of an LED chip in the related art. Figure 1 As shown, the LED chip includes a substrate and a light-emitting structure 30' located on the surface of the substrate. The substrate includes a first sapphire layer 10' and a plurality of protrusions 20' located on the first surface 11' of the first sapphire layer 10', and the protrusion 20' includes a second sapphire layer 21' and a silicon dioxide layer 23' stacked in sequence in a direction away from the first sapphire layer 10', and the orthographic projection of the silicon dioxide layer 23' on the first surface 11 is located inside the orthographic projection of the second sapphire layer 21' on the first surface 11'. That is, the bottom material of the protrusion 20' is sapphire material, and the interface between the light-emitting structure 30' and the side wall at the bottom position of the protrusion 20' is the interface between the light-emitting structure 30' and the second sapphire layer 21'.

[0039] Figure 1 The arrow in the figure indicates the propagation path of the light near the protrusion 20'. Figure 1 As shown, among the light emitted by the light emitting structure 30', the total reflection angle of the interface between the light emitting structure 30' and the side wall of the second sapphire layer 21' at the bottom position of the protrusion 20' is relatively large, and only a small part of the light with a large incident angle will be totally reflected at the interface of the side wall at the bottom position, thereby affecting the reflectivity of the substrate to the light and affecting the luminous efficiency of the LED chip.

[0040] Figure 2 Schematic diagram of a substrate structure provided by an embodiment of the present disclosure. Figure 2As shown, the substrate includes a first sapphire layer 10 and a plurality of protrusions 20 located on a first surface 11 of the first sapphire layer 10, wherein the protrusion 20 includes a main body and a silicon dioxide layer 23, the main body and the silicon dioxide layer 23 are stacked in sequence in a direction away from the first sapphire layer 10, the silicon dioxide layer 23 covers the top surface and at least a portion of the side wall of the main body, the top surface is the surface of the main body away from the first surface 11, and at least a portion of the side wall is connected to the top surface.

[0041] In order to facilitate understanding of the embodiments of the present disclosure, the propagation path of light is described below in combination with the structure of the LED chip. In the embodiments of the present disclosure, the LED chip may be a normal-mounted LED chip.

[0042] Figure 3 Schematic diagram of the structure of an LED chip provided by the embodiment of the present disclosure. Figure 3 As shown, the LED chip includes a substrate and a light emitting structure 30, wherein the substrate is Figure 2 In the substrate shown, the light emitting structure 30 is located on the surface of the plurality of protrusions 20 .

[0043] In the embodiment of the present disclosure, the protrusion 20 includes a main body and a silicon dioxide layer 23, which are stacked in sequence along a direction away from the first sapphire layer 10, and the silicon dioxide layer 23 covers the top surface of the main body and at least a portion of the side wall, the top surface is the surface of the main body away from the first surface 11, and at least a portion of the side wall is connected to the top surface, so that after the light-emitting structure 30 is formed on the surface of multiple protrusions 20, the interface between the light-emitting structure 30 and a portion of the side wall at the bottom position of the protrusion 20 is the interface between the light-emitting structure 30 and the silicon dioxide layer 23. The light emitting structure 30 is generally made of GaN material. Compared with the refractive index of 1.76 of sapphire material, the refractive index of GaN material is larger, which is 2.7. The refractive index of the silicon dioxide layer 23 is smaller, which is 1.48. That is, the refractive index difference between the light emitting structure 30 and the silicon dioxide layer 23 is larger. When light enters the film layer with a lower refractive index from a film layer with a higher refractive index, the greater the refractive index difference of the film layer, the smaller the total reflection angle. The total reflection angle of the interface between the GaN material and the sapphire material is larger, which is about 49.9°. The total reflection angle of the interface between the GaN material and the silicon dioxide layer 23 is smaller, which is about 40.05°. Therefore, the total reflection angle of the interface between the light emitting structure 30 and the silicon dioxide layer 23 is smaller. When the light emitted by the light emitting structure 30 is emitted from the light emitting structure 30 to the protrusion 20, more light with a small incident angle will be totally reflected on the side wall at the bottom position of the protrusion 20, thereby improving the reflectivity of the substrate to the light and improving the luminous efficiency of the LED chip.

[0044] Total reflection angle refers to the minimum incident angle that causes total reflection to occur. Total reflection means that when light enters a film layer with a higher refractive index from a film layer with a lower refractive index and the incident angle is greater than or equal to the total reflection angle, all incident light is reflected and does not enter the film layer with a lower refractive index to generate refracted light. When total reflection occurs, the reflectivity is equal to 1.

[0045] Optionally, the top surface of the main body is a plane and parallel to the first surface 11 .

[0046] like Figure 2 As shown, the main body includes a second sapphire layer 21 and a first DBR layer 22 stacked in sequence in a direction away from the first sapphire layer 10, and a silicon dioxide layer 23 covers the first DBR layer 22. Here, covering means covering both the surface of the film layer and the side wall of the film layer. Figure 2 The silicon dioxide layer 23 covers both the surface of the first DBR layer 22 and the sidewall of the first DBR layer 22 , that is, the silicon dioxide layer 23 covers the first DBR layer 22 below.

[0047] Figure 3 The middle arrow indicates the propagation path of the light near the protrusion 20. Since the reflectivity of the DBR layer is relatively high, after the light-emitting structure is formed on the surface of the plurality of protrusions 20, part of the light whose incident angle is less than the total reflection angle of the interface between the light-emitting structure 30 and the protrusion 20 will be reflected by the first DBR layer 22 after entering the protrusion 20, which can reduce the probability of this part of the light entering the first sapphire layer 10, resulting in an increase in the propagation distance and loss of the light, thereby improving the luminous efficiency of the LED chip. The silicon dioxide layer 23 covers the first DBR layer 22, which can reduce the probability of the high refractive index material layer in the first DBR layer 22 contacting the light-emitting structure 30 and affecting the total reflection effect of the protrusion 20 on the light, and can reduce the influence of the thermal mismatch and lattice mismatch between the first DBR layer 22 and the light-emitting structure 30 on the growth quality of the light-emitting structure 30, thereby effectively improving the luminous efficiency of the LED chip while ensuring the quality of the LED chip.

[0048] For example, the first sapphire layer 10 and the second sapphire layer 21 in the protrusion 20 can be integrally formed, that is, formed in the same patterning process. For example, the sapphire substrate can be etched to form the protruding second sapphire layer 21 on the surface of the sapphire substrate.

[0049] like Figure 2 and Figure 3 As shown, the first DBR layer 22 covers the second sapphire layer 21 and is connected to the first surface 11 , and the silicon dioxide layer 23 is connected to the first surface 11 .

[0050] In this way, after the light-emitting structure 30 is formed on the surface of the plurality of protrusions 20, the interface between the light-emitting structure 30 and the protrusion 20 is the interface between the light-emitting structure 30 and the silicon dioxide layer 23. Therefore, the total reflection angle of the interface between the light-emitting structure 30 and the silicon dioxide layer 23 is smaller. When the light emitted by the light-emitting structure 30 is emitted from the light-emitting structure 30 to the protrusion 20, more light with a small incident angle will be totally reflected at the bottom of the protrusion 20, thereby improving the reflectivity of the substrate to the light and improving the luminous efficiency of the LED chip.

[0051] Optionally, the minimum distance A1 between any point on the outer contour of the orthographic projection of the second sapphire layer 21 on the first surface 11 and the outer contour of the orthographic projection of the first DBR layer 22 on the first surface 11 is 0.1 μm to 0.5 μm. In this way, the first DBR layer 22 has a better coating effect on the second sapphire layer 21, and the first DBR layer 22 can better reflect the light incident into the silicon dioxide layer 23, effectively reducing the probability of this part of the light entering the second sapphire layer 21 and the first sapphire layer 10, resulting in an increase in the propagation distance and loss of the light, which is beneficial to improving the luminous efficiency of the LED chip.

[0052] For example, the minimum distance A1 between any point on the outer contour of the orthographic projection of the second sapphire layer 21 on the first surface 11 and the outer contour of the orthographic projection of the first DBR layer 22 on the first surface 11 may be 0.1 μm, 0.3 μm, 0.5 μm, etc.

[0053] Exemplarily, the main body formed by the second sapphire layer 21 and the first DBR layer 22 may be a truncated cone protrusion.

[0054] In other embodiments, the main body formed by the second sapphire layer 21 and the first DBR layer 22 may also be a polygonal pyramid protrusion or a cylindrical protrusion, etc., which is not limited in the present disclosure.

[0055] Figure 4 is a schematic diagram of the structure of another substrate provided by an embodiment of the present disclosure, Figure 5 is a schematic diagram of the structure of another LED chip provided by an embodiment of the present disclosure, Figure 5 The LED chip shown has a substrate of Figure 4 The substrate shown. Figure 4 and Figure 5 Example and Figure 2 and Figure 3 The difference between the embodiments is that Figure 4 and Figure 5 The middle silicon dioxide layer 23 only covers the first DBR layer 22 but does not cover the second sapphire layer 21 .

[0056] like Figure 4 and Figure 5As shown, the silicon dioxide layer 23 is connected to the second sapphire layer 21, and the orthographic projection of the silicon dioxide layer 23 on the first surface 11 is located inside the orthographic projection of the second sapphire layer 21 on the first surface 11. In this way, the luminous efficiency of the LED chip can be effectively improved while ensuring the quality of the LED chip. In addition, the photolithography steps in preparing the substrate can be reduced, which is conducive to simplifying the process and improving production efficiency.

[0057] like Figures 2 to 5 As shown, the minimum distance A2 between any point on the outer contour of the orthographic projection of the first surface 11 of the first DBR layer 22 and the outer contour of the orthographic projection of the silicon dioxide layer 23 on the first surface 11 is 0.1 μm to 0.5 μm.

[0058] Since the DBR layer includes multiple high-refractive index material layers and multiple low-refractive index material layers that are alternately stacked, the difference between the refractive index of the high-refractive index material layer and the refractive index of the light-emitting structure 30 is small. If the first DBR layer 22 and the light-emitting structure 30 are in direct contact, the total reflection angle of the interface between the high-refractive index material layer in the first DBR layer 22 and the light-emitting structure 30 is large, which will affect the total reflection effect of the protrusion 20 on the light. In addition, there is a thermal mismatch and a lattice mismatch between the first DBR layer 22 and the light-emitting structure 30, which will affect the growth quality of the light-emitting structure 30.

[0059] The minimum distance A2 between any point on the outer contour of the orthographic projection of the first DBR layer 22 on the first surface 11 and the outer contour of the orthographic projection of the silicon dioxide layer 23 on the first surface 11 is within this range. The silicon dioxide layer 23 has a good coating effect on the first DBR layer 22, which can ensure that the substrate has a high reflectivity to light and can reduce the influence of lattice mismatch and thermal mismatch on the growth quality of the light-emitting structure 30, thereby effectively improving the luminous efficiency of the LED chip while ensuring the good quality of the LED chip.

[0060] For example, the minimum distance A2 between any point on the outer contour of the orthographic projection of the first surface 11 of the first DBR layer 22 and the outer contour of the orthographic projection of the silicon dioxide layer 23 on the first surface 11 may be 0.1 μm, 0.3 μm, 0.5 μm, etc.

[0061] Optionally, the first DBR layer 22 includes a plurality of SiO2 layers and a plurality of TiO2 layers alternately stacked. The refractive index of TiO2 is relatively large, about 2.5, and the refractive index of SiO2 is relatively small, 1.48. The difference in refractive index between the two materials is relatively large. Using the two materials as a high refractive index material layer and a low refractive index material layer, respectively, is conducive to improving the reflectivity of the first DBR layer 22 to light.

[0062] Exemplarily, the first DBR layer 22 includes a plurality of SiO2 layers and a plurality of TiO2 layers periodically and alternately stacked, and the number of periods may be 2 to 10. For example, the first DBR layer 22 may include 5 SiO2 layers and 5 TiO2 layers periodically and alternately stacked.

[0063] Optionally, the protrusion 20 may be a truncated cone protrusion, so that the light emitted by the light emitting structure 30 can generate total reflection better when it is directed toward the protrusion, and the truncated cone protrusion is conducive to production and manufacturing.

[0064] In other embodiments, the protrusion 20 may also be a conical protrusion, a truncated cone protrusion, a polygonal pyramid protrusion, a polygonal cone protrusion or a cylindrical protrusion, etc., and the present disclosure does not limit this.

[0065] For example, the second sapphire layer 21 may be a truncated cone protrusion, and the first DBR layer 22 may be a truncated cone protrusion.

[0066] In other embodiments, the second sapphire layer 21 and the first DBR layer 22 may also be polygonal pyramid protrusions or cylindrical protrusions, etc., which is not limited in the present disclosure.

[0067] Figure 6 It is a schematic diagram of the structure of another substrate provided in an embodiment of the present disclosure. Figure 6 The substrate and Figures 2 to 5 The difference between the substrates in Figure 6 The protrusion 20 does not include the first DBR layer, but only includes the second sapphire layer 21 and the silicon dioxide layer 23. Figure 6 As shown, the main body of the substrate is a second sapphire layer 21 , and the silicon dioxide layer 23 covers the second sapphire layer 21 and is connected to the first surface 11 .

[0068] Figure 7 FIG. 1 is a schematic diagram of the structure of another LED chip provided by the embodiment of the present disclosure. Figure 7 As shown, the LED chip includes a substrate and a light emitting structure 30, wherein the substrate is Figure 6 In the substrate shown, the light emitting structure 30 is located on the surface of the plurality of protrusions.

[0069] like Figure 7 As shown, after the light emitting structure 30 is formed on the surface of the plurality of protrusions 20, the interface between the light emitting structure 30 and the protrusions 20 is the interface between the light emitting structure 30 and the silicon dioxide layer 23, and the total reflection angle of the interface between the light emitting structure 30 and the silicon dioxide layer 23 is smaller. Figure 7 The middle arrow indicates the propagation path of the light near the protrusion 20. When the light emitted by the light-emitting structure 30 is directed from the light-emitting structure 30 to the protrusion 20, more light with a small incident angle will be totally reflected at the bottom of the protrusion 20, thereby improving the reflectivity of the substrate to the light and improving the luminous efficiency of the LED chip.

[0070] like Figure 6 As shown, the minimum distance A3 between any point on the outer contour of the orthographic projection of the second sapphire layer 21 on the first surface 11 and the outer contour of the orthographic projection of the silicon dioxide layer 23 on the first surface 11 is 0.1 μm to 0.5 μm. In this way, the silicon dioxide layer 23 has a better coating effect on the second sapphire layer 21, so that the reflectivity of light at each position of the protrusion 20 is higher, which is beneficial to improve the luminous efficiency of the LED chip.

[0071] For example, the minimum distance A3 between any point on the outer contour of the orthographic projection of the second sapphire layer 21 on the first surface 11 and the outer contour of the orthographic projection of the silicon dioxide layer 23 on the first surface 11 may be 0.1 μm, 0.3 μm or 0.5 μm, etc.

[0072] Optionally, the protrusion 20 may be a conical protrusion, so that the light emitted by the light emitting structure 30 can generate total reflection better when it is directed toward the protrusion 20, and the conical protrusion is conducive to production and manufacturing.

[0073] In other embodiments, the protrusion 20 may also be a truncated cone protrusion, a polygonal pyramid protrusion, a polygonal pyramid protrusion or a cylindrical protrusion, etc., and the present disclosure does not limit this.

[0074] Exemplarily, the second sapphire layer 21 may be a truncated cone protrusion.

[0075] In other embodiments, the second sapphire layer 21 may also be a polygonal pyramid protrusion or a cylindrical protrusion, etc., which is not limited in the present disclosure.

[0076] like Figures 2 to 7 As shown, a plurality of protrusions 20 are arranged in an array on the first surface 11 .

[0077] Exemplarily, the plurality of protrusions 20 may be arranged in a periodic hexagonal close-packed arrangement, a periodic square lattice arrangement, a quasi-crystalline structure arrangement, or a high-density random arrangement.

[0078] like Figure 2 , Figure 4 and Figure 6 As shown, the maximum width W of the orthographic projection of the protrusion 20 on the first surface 11 is 1 μm to 4 μm. Here, the maximum width refers to the maximum value of the width of the orthographic projection of the protrusion 20 on the first surface 11. For example, when the protrusion 20 is a conical protrusion, the maximum width W of the orthographic projection of the protrusion 20 on the first surface 11 is the diameter of the circular bottom surface of the conical protrusion.

[0079] Exemplarily, the maximum width W of the orthographic projection of the protrusion 20 on the first surface 11 may be 1 μm, 2 μm, or 4 μm.

[0080] Optionally, the distance D between adjacent protrusions 20 is 50 nm to 500 nm.

[0081] For example, the distance D between adjacent protrusions 20 may be 50 nm, 300 nm, or 500 nm.

[0082] Optionally, the height H of the protrusion 20 is 1 μm to 3 μm.

[0083] For example, the height H of the protrusion 20 may be 1 μm, 2 μm, 3 μm, or the like.

[0084] Figure 8 FIG. 1 is a flow chart of a method for preparing a substrate provided by an embodiment of the present disclosure. Figure 8 As shown, the preparation method comprises:

[0085] In step S101 , a first sapphire layer is provided.

[0086] In step S102 , a plurality of protrusions are formed on a first surface of a first sapphire layer.

[0087] The protrusion includes a main body and a silicon dioxide layer, which are stacked in sequence in a direction away from the first sapphire layer. The silicon dioxide layer covers the top surface of the main body and at least part of the side wall. The top surface is the surface of the main body away from the first surface, and at least part of the side wall is connected to the top surface.

[0088] In the disclosed embodiment, the protrusion includes a main body and a silicon dioxide layer, the main body and the silicon dioxide layer are stacked in sequence in a direction away from the first sapphire layer, the silicon dioxide layer covers the top surface of the main body and at least part of the side wall, the top surface is the surface of the main body away from the first surface, and at least part of the side wall is connected to the top surface, so that after the light-emitting structure is formed on the surface of the plurality of protrusions, the interface between the light-emitting structure and the part of the side wall at the bottom position of the protrusion is the interface between the light-emitting structure and the silicon dioxide layer. Compared with the sapphire material, the refractive index of the light-emitting structure is larger, and the refractive index of the silicon dioxide layer is smaller, that is, the refractive index difference between the light-emitting structure and the silicon dioxide layer is larger. Since when the light enters the film layer with a higher refractive index from the film layer with a lower refractive index, the greater the refractive index difference of the film layer, the smaller the total reflection angle, so the total reflection angle of the interface between the light-emitting structure and the silicon dioxide layer is smaller, and when the light emitted by the light-emitting structure is emitted from the light-emitting structure to the protrusion, more light with a small incident angle will be totally reflected on the side wall at the bottom position of the protrusion, thereby improving the reflectivity of the substrate to the light and improving the luminous efficiency of the LED chip.

[0089] Fig. 9 is a flow chart of another method for preparing a substrate provided by an embodiment of the present disclosure. The method is used to prepare Figure 2 The substrate shown, Fig. 9 As shown, the preparation method comprises:

[0090] In step S201 , a plurality of first initial protrusions are formed on a first surface of a first sapphire layer.

[0091] Fig.10 Schematic diagram of the structure of a substrate during the preparation process provided by an embodiment of the present disclosure. Fig.10 As shown, a photoresist structure can be obtained on the surface of a sapphire substrate by processes such as photoresist coating, exposure, and development, and the surface of the sapphire substrate is etched by an inductively coupled plasma (ICP) etching method using the photoresist structure as a mask to form a first sapphire layer 10 and a plurality of first initial protrusions located on the first surface 11 of the first sapphire layer 10, wherein the first initial protrusion is a second sapphire layer 21.

[0092] In the disclosed embodiment, the photoresist may be a positive photoresist.

[0093] Exemplarily, the etching gas used when etching the sapphire substrate may be BCl2.

[0094] In step S202 , a first DBR layer is formed on each of the first initial protrusions.

[0095] Fig.11 Schematic diagram of the structure of a substrate during the preparation process provided by an embodiment of the present disclosure. Fig.11 As shown, an initial first DBR layer can be deposited on the entire surface of multiple first initial protrusions, and a photoresist structure with a thickness of 2μm to 3μm is obtained on the initial first DBR layer through processes such as photoresist coating, exposure, and development. The initial first DBR layer is etched by an ICP etching method using the photoresist structure as a mask. After removing the photoresist structure, a first DBR layer 22 is formed on each first initial protrusion, and the first DBR layer 22 covers the second sapphire layer 21 and is connected to the first surface 11.

[0096] For example, ion source assisted plating may be used when forming the first DBR layer 22 , thereby improving the compactness and reflectivity of the first DBR layer 22 .

[0097] Exemplarily, the etching gas used when etching the initial first DBR layer may be CF4 and O2.

[0098] In step S203, a silicon dioxide layer is formed on the first DBR layer to obtain a substrate.

[0099] For example, a plasma enhanced chemical vapor deposition (PECVD) technique can be used to deposit an initial silicon dioxide layer on the entire surface of the first DBR layer, and a photoresist structure with a thickness of 2 μm to 4 μm is obtained on the initial silicon dioxide layer through processes such as photoresist coating, exposure, and development. The initial silicon dioxide layer is etched by an ICP etching method using the photoresist structure as a mask, and a silicon dioxide layer is formed on the first DBR layer after removing the photoresist structure, so as to obtain Figure 2 The substrate shown in FIG. 1 includes a silicon dioxide layer 23 covering the first DBR layer 22 , and the silicon dioxide layer 23 is connected to the first surface 11 .

[0100] Illustratively, the thickness of the initial silicon dioxide layer may be 2 μm to 4 μm.

[0101] Exemplarily, the etching gas used when etching the initial silicon dioxide layer may be BCl 2 .

[0102] Fig.12 is a flow chart of another method for preparing a substrate provided by an embodiment of the present disclosure. The preparation method is used to prepare Figure 4 The substrate shown, Fig.12 As shown, the preparation method comprises:

[0103] In step S301 , a plurality of second initial protrusions are formed on an initial sapphire substrate.

[0104] Fig.13 Schematic diagram of the structure of a substrate during the preparation process provided by an embodiment of the present disclosure. Fig.13 As shown, an initial first DBR layer can be deposited on the entire surface of the initial sapphire substrate 1, and a photoresist structure with a thickness of 2μm to 3μm is obtained on the initial first DBR layer through processes such as photoresist coating, exposure, and development. The initial first DBR layer is etched by an ICP etching method using the photoresist structure as a mask. After removing the photoresist structure, a plurality of second initial protrusions are formed on the initial sapphire substrate 1, and the second initial protrusions are the first DBR layer 22.

[0105] In step S302 , an initial silicon dioxide layer is formed on the plurality of second initial protrusions.

[0106] Fig.14 Schematic diagram of the structure of a substrate during the preparation process provided by an embodiment of the present disclosure. Fig.14 As shown, a preliminary silicon dioxide layer 23a may be deposited on the entire surface of the plurality of second preliminary protrusions using PECVD technology.

[0107] In step S303, the initial second silicon oxide layer and the initial sapphire substrate are etched to obtain a substrate.

[0108] like Fig.14 As shown, the photoresist layer 2 can be obtained on the surface of the initial second silicon oxide layer 23a by photoresist coating, exposure, development and other processes, and the initial second silicon oxide layer 23a and the initial sapphire substrate 1 are etched by ICP etching method using the photoresist layer 2 as a mask to obtain Figure 4 The substrate shown in FIG. 1 includes a silicon dioxide layer 23 covering the first DBR layer 22 , the silicon dioxide layer 23 is connected to the second sapphire layer 21 , and the orthographic projection of the silicon dioxide layer 23 on the first surface 11 is located inside the orthographic projection of the second sapphire layer 21 on the first surface 11 .

[0109] Exemplarily, the etching gas used when etching the initial second silicon oxide layer 23 a and the initial sapphire substrate 1 may be BCl 2 .

[0110] Fig.15 is a flow chart of another method for preparing a substrate provided by an embodiment of the present disclosure. The preparation method is used to prepare Figure 6 The substrate shown, Fig.15 As shown, the preparation method comprises:

[0111] In step S401 , a plurality of first initial protrusions are formed on a first surface of a first sapphire layer.

[0112] Illustratively, a photoresist structure can be obtained on the surface of a sapphire substrate through processes such as photoresist coating, exposure, and development, and the surface of the sapphire substrate is etched by an ICP etching method using the photoresist structure as a mask to form a first sapphire layer and a plurality of first initial protrusions located on the first surface of the first sapphire layer, wherein the first initial protrusion is a second sapphire layer.

[0113] In step S402, a silicon dioxide layer is formed on each of the first initial protrusions to obtain a substrate.

[0114] For example, a PECVD technique can be used to deposit an initial silicon dioxide layer on the entire surface of the plurality of first initial protrusions, and a photoresist structure with a thickness of 2 μm to 4 μm can be obtained on the initial silicon dioxide layer by photoresist coating, exposure, development and other processes, and the initial silicon dioxide layer is etched by an ICP etching method using the photoresist structure as a mask, and after removing the photoresist structure, a silicon dioxide layer is formed on each of the first initial protrusions to obtain a Figure 6 The substrate shown in FIG. 1 , wherein the silicon dioxide layer 23 covers the second sapphire layer 21 and is connected to the first surface 11 .

[0115] The present disclosure also provides an LED chip, such as Figure 3, Figure 5 and Figure 7 As shown, the LED chip includes a substrate and a light emitting structure 30, wherein the substrate is Figure 2 , Figure 4 and Figure 6 In the substrate shown, the light emitting structure 30 is located on the surface of the plurality of protrusions 20 .

[0116] For the structure, material, shape and size of the above substrate, please refer to Figures 2 to 7 The detailed description of the related embodiments is omitted here.

[0117] Optionally, the light emitting structure 30 includes a first semiconductor layer 31 , a light emitting layer 32 , and a second semiconductor layer 33 which are sequentially stacked in a direction away from the substrate.

[0118] Optionally, the first semiconductor layer 31 may be an N-type GaN layer, and the second semiconductor layer 33 may be a P-type GaN layer.

[0119] Exemplarily, the first semiconductor layer 31 is a Si-doped GaN layer, and the second semiconductor layer 33 is a Mg-doped GaN layer.

[0120] Optionally, the light-emitting layer 32 is a multi-quantum well layer, including multiple pairs of InGaN layers and GaN layers stacked alternately. Different materials can be selected for the light-emitting layer 32 according to the different light-emitting wavelength ranges of the LED chips. For example, the light-emitting layer 32 of the blue-green LED chip can use multiple pairs of InGaN layers and GaN layers stacked alternately, and the light-emitting layer 32 of the red LED chip can use multiple pairs of InGaAs layers and GaAs layers stacked alternately.

[0121] Exemplarily, the light emitting layer 32 includes 3 to 8 pairs of InGaN layers and GaN layers stacked alternately, for example, 5 pairs of InGaN layers and GaN layers stacked alternately, and of course other pairs are also possible, which is not limited in the present disclosure.

[0122] Optionally, the LED chip further includes a second DBR layer 40, which is located on the second surface 12 of the first sapphire layer 10, and the second surface 12 and the first surface 11 are opposite surfaces of the first sapphire layer 10. The second DBR layer 40 can reflect the light incident into the first sapphire layer 10 toward the direction where the light emitting structure 30 is located, which is beneficial to improving the light extraction efficiency of the LED chip.

[0123] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.

Claims

1. A substrate, characterized in that: The invention comprises a first sapphire layer (10) and a plurality of protrusions (20) located on a first surface (11) of the first sapphire layer (10). The protrusion (20) comprises a main body and a silicon dioxide layer (23), wherein the main body and the silicon dioxide layer (23) are stacked in sequence in a direction away from the first sapphire layer (10), and the silicon dioxide layer (23) covers the top surface and at least a portion of the side wall of the main body, wherein the top surface is the surface of the main body away from the first surface (11), and the at least a portion of the side wall is connected to the top surface.

2. The substrate according to claim 1, characterized in that The main body comprises a second sapphire layer (21) and a first distributed Bragg reflection layer (22) which are sequentially stacked in a direction away from the first sapphire layer (10), and the silicon dioxide layer (23) covers the first distributed Bragg reflection layer (22).

3. The substrate according to claim 2, characterized in that The first distributed Bragg reflection layer (22) covers the second sapphire layer (21) and is connected to the first surface (11), and the silicon dioxide layer (23) is connected to the first surface (11).

4. The substrate according to claim 2, characterized in that The silicon dioxide layer (23) is connected to the second sapphire layer (21), and an orthographic projection of the silicon dioxide layer (23) on the first surface (11) is located inside an orthographic projection of the second sapphire layer (21) on the first surface (11).

5. The substrate according to claim 3, characterized in that The minimum distance between any point on the outer contour of the orthographic projection of the second sapphire layer (21) on the first surface (11) and the outer contour of the orthographic projection of the first distributed Bragg reflection layer (22) on the first surface (11) is 0.1 μm to 0.5 μm.

6. The substrate according to any one of claims 2 to 5, characterized in that The minimum distance between any point on the outer contour of the orthographic projection of the first distributed Bragg reflection layer (22) on the first surface (11) and the outer contour of the orthographic projection of the silicon dioxide layer (23) on the first surface (11) is 0.1 μm to 0.5 μm.

7. The substrate according to claim 1, characterized in that The main body is a second sapphire layer (21), and the silicon dioxide layer (23) covers the second sapphire layer (21) and is connected to the first surface (11).

8. The substrate according to claim 7, characterized in that The minimum distance between any point on the outer contour of the orthographic projection of the second sapphire layer (21) on the first surface (11) and the outer contour of the orthographic projection of the silicon dioxide layer (23) on the first surface (11) is 0.1 μm to 0.5 μm.

9. A method for preparing a substrate, characterized in that: include: Providing a first sapphire layer (10); A plurality of protrusions (20) are formed on the first surface (11) of the first sapphire layer (10), wherein the protrusions (20) include a main body and a silicon dioxide layer (23), wherein the main body and the silicon dioxide layer (23) are stacked in sequence in a direction away from the first sapphire layer (10), and the silicon dioxide layer (23) covers the top surface and at least a portion of the side wall of the main body, wherein the top surface is the surface of the main body away from the first surface (11), and the at least a portion of the side wall is connected to the top surface.

10. A light emitting diode chip, characterized in that: It comprises a substrate and a light-emitting structure, wherein the substrate is the substrate according to any one of claims 1 to 8, and the light-emitting structure is located on the surface of the plurality of protrusions (20).

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