Power supply circuit
By designing a power supply circuit for automobiles, comparing the power supply voltage and controlling the conduction and shutdown of the switch tubes, the current backflow problem caused by signal delay during cold start of the car is solved, and higher power supply stability and safety are achieved sex.
Patent Information
- Application Number
- CN202411312968.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2024-12-31
AI Technical Summary
The existing multi-power rail design is slow to turn off due to signal delay during cold start of the car, resulting in the problem of current backflow, which is difficult to meet the demand for automobile power supply.
Design a power supply circuit, by comparing the first power supply voltage and the second power supply voltage, control the conduction and shutdown of the switch tube, and quickly turn off the corresponding switch tube using the third and fourth switch tubes to prevent the current from pouring back. And ensure that the rear-stage system works normally at higher voltages.
Effectively prevent current backflow, ensure that the system works normally at high voltage, and improve the power supply stability and safety during cold start of the car.
Smart Images
Figure CN119231883A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of dual power supply, and in particular to a power supply circuit. Background Art
[0002] With the rapid development of the automobile industry, especially the popularity of electric vehicles and hybrid vehicles, higher requirements are placed on the stability and reliability of vehicle power supply systems. During the cold start of a car, the battery voltage drops sharply in a short period of time, which often causes key components such as the on-board electronic control unit (ECU) and driver chips to fail to work normally due to insufficient power supply, thus affecting the starting performance and driving safety of the entire vehicle.
[0003] In the prior art, driver chips usually adopt a single power rail design, that is, they mainly rely on a high-voltage battery power supply (VS) to provide power for the analog circuits, digital circuits and driver circuits in the chip. However, in a cold start scenario, the VS voltage may quickly drop below 3V, which is far lower than the minimum power supply voltage (i.e., undervoltage threshold) required for most chips to work normally, causing the chip to fail and unable to effectively drive the load or perform necessary control operations.
[0004] To meet this challenge, the industry has begun to explore the use of multi-power rail design solutions to enhance the power supply stability of chips under extreme conditions. Among them, a low-voltage power supply (Vdd, usually 5V) is introduced as an auxiliary power rail to work in parallel with the high-voltage power supply (VS).
[0005] However, existing multi-power rail designs usually use control chip monitoring to switch the main power supply and backup power supply. The development of control chips requires extremely high costs and it is difficult to meet the good power supply requirements during the cold start process of the car. In addition, when controlling the switching, the switch is slow to shut down due to signal delay, resulting in the problem of current backflow between the two power supplies, which is also difficult to solve. Summary of the invention
[0006] The object of the present invention is to provide a power supply circuit to solve the problem of current backflow between two power supplies due to slow shutdown of a switch tube caused by signal delay when one of the power supplies is stepped down and controlled switching in a multi-power rail design in the prior art.
[0007] To achieve one of the above-mentioned objects of the invention, an embodiment of the present invention provides a power supply circuit, the circuit comprising: a first switch tube, having a first end, a second end and a control end, wherein the first end receives a first power supply voltage; a second switch tube, having a first end, a second end and a control end, wherein the first end receives a second power supply voltage, and the second end is coupled to the second end of the first switch tube and outputs an internal power supply voltage; wherein when the first power supply voltage is less than the sum of the second power supply voltage and a first reference threshold, the first switch tube is turned off, the second switch tube is turned on, and the internal power supply voltage is generated according to the second power supply voltage; and when the first power supply voltage is greater than the sum of the second power supply voltage and the second reference threshold, the first switch tube is turned on, and the second switch tube is turned on. The internal power supply voltage is generated according to the first power supply voltage; a third switch tube has a first end, a second end and a control end, the first end of which receives the second power supply voltage, the second end is coupled to the control end of the first switch tube, and the control end receives the first power supply voltage; and a fourth switch tube has a first end, a second end and a control end, the first end of which receives the first voltage, the second end is coupled to the control end of the second switch tube, and the control end receives the second power supply voltage; wherein, when the first power supply voltage is powered off so that the first power supply voltage is less than the second power supply voltage, the third switch tube is turned on and the first switch tube is turned off; when the second power supply voltage is powered off so that the second power supply voltage is less than the first power supply voltage, the fourth switch tube is turned on and the second switch tube is turned off.
[0008] Compared with the prior art, the present invention has the following beneficial effects: by comparing the first power supply voltage and the second power supply voltage, the circuit is determined and controlled to maintain a higher voltage output, thereby ensuring the normal operation of the subsequent system at a higher voltage, and when the circuit is switched, the first switch tube is quickly turned off through the third switch tube or the second switch tube is quickly turned off through the fourth switch tube to prevent current backflow. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 A schematic diagram of the connection structure of a power supply circuit 100 according to an embodiment of the present invention is given.
[0010] Figure 2 A circuit structure diagram of a channel selection circuit 4 according to an embodiment of the present invention is given.
[0011] Figure 3 A schematic structural diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 according to an embodiment of the present invention is given.
[0012] Figure 4 A schematic structural diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 according to another embodiment of the present invention is given.
[0013] Figure 5A schematic structural diagram of a first voltage divider circuit 11 and a second voltage divider circuit 12 according to another embodiment of the present invention is provided. DETAILED DESCRIPTION
[0014] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.
[0015] It should be noted that the term "comprises" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In addition, the terms "first", "second", "third", "fourth", "fifth", "sixth", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.
[0016] The phrases "one embodiment", "an embodiment", "an example", and "example" that appear in various places throughout the specification do not necessarily refer to the same embodiment or example. It should be understood by those skilled in the art that the various specific features, structures or parameters, steps, etc. disclosed in one or more embodiments of the present disclosure can be combined in any suitable manner.
[0017] Figure 1A power supply circuit 100 according to an embodiment of the present invention is provided. The power supply circuit 100 includes a first switch tube M1 and a second switch tube M2. The first switch tube M1 has a first end, a second end and a control end, and the first end thereof receives a first power supply voltage Vs. The second switch tube M2 has a first end, a second end and a control end, and the first end thereof receives a second power supply voltage Vdd. The second end of the second switch tube M2 is coupled to the second end of the first switch tube M1 and outputs an internal power supply voltage VINT. When the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first reference threshold TH1, the first switch tube M1 is turned off, the second switch tube M2 is turned on, and the internal power supply voltage VINT is generated according to the second power supply voltage Vdd. When the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second reference threshold TH2, the first switch tube M1 is turned on, the second switch tube M2 is turned off, and the internal power supply voltage INT is generated according to the first power supply voltage Vs. In one embodiment, the first reference threshold TH1 and the second reference threshold TH2 are 0. In one embodiment, the first reference threshold TH1 is equal to the second reference threshold TH2. In one embodiment, the first reference threshold TH1 is less than the second reference threshold TH2. In one embodiment, the first reference threshold TH1 is between 0.05V and 0.1V. In one embodiment, the first power supply voltage Vs is between 40V and 4V, and the second power supply voltage Vdd is between 3.5V and 5V. In one embodiment, the first switch tube M1 is a P-type field effect transistor, and the second switch tube M2 is a P-type field effect transistor.
[0018] continue Figure 1As described above, the power supply circuit 100 also includes a third switch tube M3 and a fourth switch tube M4. The third switch tube M3 has a first end, a second end, and a control end. The first end of the third switch tube M3 receives the second power supply voltage Vdd, the second end of the third switch tube M3 is coupled to the control end of the first switch tube M1, and the control end of the third switch tube M3 receives the first power supply voltage Vs. The fourth switch tube M4 has a first end, a second end, and a control end. The first end of the fourth switch tube M4 receives the first power supply voltage Vs, the second end of the fourth switch tube M4 is coupled to the control end of the second switch tube M2, and the control end of the fourth switch tube M4 receives the second power supply voltage Vdd. In one embodiment, when the first power supply voltage Vs is powered off so that the first power supply voltage Vs is less than the second power supply voltage Vdd, the third switch tube M3 is turned on and the first switch tube M1 is turned off. When the first power supply voltage Vs continues to decrease so that the first power supply voltage Vs is less than the second power supply voltage Vdd and the difference between the first power supply voltage Vs and the second power supply voltage Vdd (gate voltage and source voltage) of the third switch tube M3 reaches the threshold value of the gate voltage Vgs of the third switch tube M3, the internal channel of the fourth switch tube M4 is turned on, and the current generated by the first power supply voltage Vs flows through the fourth switch tube M4 and flows out from the second end of the fourth switch tube M4. In this way, the first switch tube M1 is turned off quickly to prevent the current generated by the second power supply voltage Vdd from flowing back to the first power supply voltage Vs through the second switch tube M2 and the first switch tube M1 due to the delay of the circuit control signal causing the first switch tube M1 to turn off slowly. In one embodiment, when the second power supply voltage Vdd is powered off so that the second power supply voltage Vdd is less than the first power supply voltage Vs, the fourth switch tube M4 is turned on and the second switch tube M2 is turned off. When the second power supply voltage Vdd continues to decrease so that the second power supply voltage Vdd is less than the first power supply voltage Vs and the difference between the second power supply voltage Vdd and the first power supply voltage Vs (gate voltage and source voltage) of the fourth switch tube M4 reaches the threshold of the gate voltage Vgs of the fourth switch tube M4, the internal channel of the fourth switch tube M4 is turned on, and the current generated by the first power supply voltage Vs flows through the fourth switch tube M4 and flows out from the second end of the fourth switch tube M4. In this way, the second switch tube M2 is quickly turned off to prevent the current generated by the first power supply voltage Vs from flowing back to the second power supply voltage Vdd through the first switch tube M1 and the second switch tube M2 due to the delay of the control signal of the circuit. In one embodiment, the third switch tube M3 is a P-type field effect transistor, and the fourth switch tube M4 is a P-type field effect transistor.
[0019] continue Figure 1As described above, the power supply circuit 100 further includes a channel selection circuit 4, which is coupled to the first power supply voltage Vs and the second power supply voltage Vdd, and is used to generate a first switch control signal S1 and a second switch control signal S2 according to the first power supply voltage Vs and the second power supply voltage Vdd to control the on and off of the first switch tube M1 and the second switch tube M2 respectively. In one embodiment, when the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second reference threshold TH2, the channel selection circuit 4 outputs the first switch control signal S1 to turn on the first switch tube M1, and the second end of the first switch tube M1 serves as the output end of the power supply circuit 100 to output the internal power supply voltage VINT. In one embodiment, when the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first reference threshold TH1, the channel selection circuit 4 outputs the second switch control signal S2 to turn on the second switch tube M2, and the second end of the second switch tube M2 serves as the output end of the power supply circuit 100 to output the internal power supply voltage VINT. In one embodiment, the first switch tube M1 and the second switch tube M2 have parasitic diodes. In this way, when the first switch tube M1 and the second switch tube M2 are both turned off, the parasitic diodes of the first switch tube M1 and the second switch tube M2 can also output a large voltage to supply to the subsequent system, so that some functional modules in the subsequent system that consume less power and require long-term power can be stably and continuously powered, and when the chip is in sleep mode, there is still a stable internal power supply voltage.
[0020] exist Figure 1 In the embodiment shown, the channel selection circuit 4 receives an enable signal S3, which is a signal for controlling the power supply circuit 100 to be in a sleep state. When the enable signal S3 is valid, the first switch control signal S1 is controlled to turn off the first switch tube M1, and the second control signal S2 is controlled to turn off the second switch tube M2. When the enable signal S3 is invalid, the first switch control signal S1 and the second control signal S2 output by the channel selection circuit 4 are used to control the first switch tube M1 to be turned on and the second switch tube M2 to be turned off, or the second switch tube M2 to be turned on and the first switch tube M1 to be turned off.
[0021] Figure 2A circuit structure diagram of a channel selection circuit 4 in one embodiment of the present invention is given. The channel selection circuit 4 includes a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13. The first voltage divider circuit 11 is coupled to the first power supply voltage Vs, and generates a first voltage divider signal Vfb1 representing the first power supply voltage Vs according to the first power supply voltage Vs. The second voltage divider circuit 12 is coupled to the second power supply voltage Vdd, and generates a second voltage divider signal Vfb2 representing the second power supply voltage Vdd according to the second power supply voltage Vdd. The logic operation circuit 13 receives the first voltage divider signal Vfb1 and the second voltage divider signal Vfb2, and generates a first switch control signal S1 and a second switch control signal S2 according to the first voltage divider signal Vfb1 and the second voltage divider signal Vfb2 to control the conduction and shutoff of the first switch tube M1 and the second switch tube M2 respectively. In one embodiment, the logic operation circuit 13 receives an enable signal S3, and when the enable signal S3 is valid, the first switch control signal S1 is controlled to shut off the first switch tube M1, and the second control signal S2 is controlled to shut off the second switch tube M2.
[0022] Figure 3 A circuit structure diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 in one embodiment of the present invention is given. The first voltage divider circuit 11 includes a first voltage divider resistor Z1 and a second voltage divider resistor Z2, and the second voltage divider circuit 12 includes a third voltage divider resistor Z3 and a fourth voltage divider resistor Z4. The first end of the first voltage divider resistor Z1 is coupled to the first supply voltage Vs, the second end of the first voltage divider resistor Z1 is coupled to the first end of the second voltage divider resistor Z2, and the second end of the second voltage divider resistor Z2 is coupled to the reference ground GND. The first supply voltage Vs is divided by the first voltage divider resistor Z1 and the second voltage divider resistor Z2 to form a first voltage divider signal Vfb1. The first end of the third voltage divider resistor Z3 is coupled to the second supply voltage Vdd, the second end of the third voltage divider resistor Z3 is coupled to the first end of the fourth voltage divider resistor Z4, and the second end of the fourth voltage divider resistor Z4 is coupled to the reference ground GND. The second voltage V2 is divided by the third voltage divider resistor Z3 and the fourth voltage divider resistor Z4 to form a second voltage divider signal Vfb2. In one embodiment, the value of the first divided voltage signal Vfb1 is one tenth of the value of the first supply voltage Vs.
[0023] exist Figure 3In the embodiment, the logic operation circuit 13 includes a comparator A and an inverter F, wherein the first input terminal of the comparator A receives the first voltage-divided signal Vfb1, and the second input terminal of the comparator A receives the second voltage-divided signal Vfb2. The output terminal of the comparator A is coupled to the control terminal of the second switch tube M2, the input terminal of the inverter F is coupled to the output terminal of the comparator A, and the output terminal of the inverter F is coupled to the control terminal of the first switch tube M1. In one embodiment, when the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second reference threshold TH2, the comparator A outputs a high level "1", the first switch control signal S1 is characterized by a low level "0" to turn on the first switch tube M1, and the second switch control signal S2 is characterized by a high level "1" to turn off the second switch tube M2. In one embodiment, when the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first reference threshold TH1, the comparator A outputs a low level "0", the first switch control signal S1 is characterized by a high level "1" to turn off the first switch tube M1, and the second switch control signal S2 is characterized by a low level "0" to turn on the second switch tube M2. In one embodiment, the first reference threshold TH1 is related to the first voltage division signal Vfb1. In one embodiment, the comparator A is a hysteresis comparator, and the values of the first reference threshold TH1 and the second reference threshold TH2 are related to the first voltage division signal Vfb1 and the hysteresis VD of the hysteresis comparator A. The voltage division coefficient between the first voltage division signal Vfb1 and the first power supply voltage Vs is K1, the first reference threshold TH1 = (VK + VD) / K1, and the second reference threshold TH2 = (VK - VD) / K1. Wherein, VK represents the rated preset value in the comparator A, which is represented as the basic voltage of the hysteresis of the hysteresis comparator A, and the hysteresis comparator A oscillates up or down by the hysteresis amount VD based on the basic voltage. In one embodiment, the rated preset value VK is set according to the voltage drop value generated by the first power supply voltage Vs in the power supply circuit 100.
[0024] Figure 4 A circuit structure diagram of a first voltage divider circuit 11, a second voltage divider circuit 12 and a logic operation circuit 13 in another embodiment of the present invention is given. The first voltage divider circuit 11 includes a first voltage divider resistor Z1 and a second voltage divider resistor Z2, and the second voltage divider circuit 12 includes a third voltage divider resistor Z3 and a fourth voltage divider resistor Z4. The first end of the first voltage divider resistor Z1 is coupled to the first supply voltage Vs, the second end of the first voltage divider resistor Z1 is coupled to the first end of the second voltage divider resistor Z2, and the second end of the second voltage divider resistor Z2 is coupled to the reference ground GND. The first supply voltage Vs is divided by the first voltage divider resistor Z1 and the second voltage divider resistor Z2 to form a first voltage divider signal Vfb1. The first end of the third voltage divider resistor Z3 is coupled to the second supply voltage Vdd, the second end of the third voltage divider resistor Z3 is coupled to the first end of the fourth voltage divider resistor Z4, and the second end of the fourth voltage divider resistor Z4 is coupled to the reference ground GND. The second voltage V2 is divided by the third voltage divider resistor Z3 and the fourth voltage divider resistor Z4 to form a second voltage divider signal Vfb2.
[0025] exist Figure 4 In the embodiment, the logic operation circuit 13 includes a comparator A, a first NAND gate 41, a first OR gate 43, a first resistor R1, an inverter F, a second NAND gate 42, a second OR gate 44 and a second resistor R2. The first input terminal of the comparator A receives the first voltage division signal Vfb1, and the second input terminal of the comparator receives the second voltage division signal Vfb2. The first NAND gate 41, the first OR gate 43, the second NAND gate 42 and the second OR gate 44 all have a first input terminal, a second input terminal and an output terminal. The first input terminal of the first NAND gate 41 is coupled to the output terminal of the comparator A. The first input terminal of the first OR gate 43 receives the enable signal S3, and the second input terminal is coupled to the output terminal of the first NAND gate 41. The first terminal of the first resistor R1 is coupled to the output terminal of the first OR gate 43, and the second terminal of the first resistor R1 is coupled to the control terminal of the first switch tube M1. The input terminal of the inverter F is coupled to the output terminal of the comparator A. The first input terminal of the second NAND gate 42 is coupled to the output terminal of the inverter F, and the second input terminal is coupled to the second terminal of the first resistor R1. The first input terminal of the second OR gate 44 receives the enable signal S3, and the second input terminal is coupled to the output terminal of the second NAND gate 42. The first terminal of the second resistor R2 is coupled to the output terminal of the second OR gate 44, the second terminal of the second resistor R2 is coupled to the control terminal of the second switch tube M2, and the second terminal of the second resistor R2 is also coupled to the second input terminal of the first NAND gate 41.
[0026] for Figure 4 The explanation is that when both inputs of the OR gate are "0", the output is "0". When both inputs of the NAND gate are "1", the output is "0".
[0027] exist Figure 4 In one embodiment, when the enable signal S3 is valid, the enable signal S3 is a high-level signal "1", and the first OR gate 43 and the second OR gate 44 receive the signal "1", then the outputs of the first OR gate 43 and the second OR gate 44 are always high-level signals "1", keeping the first switch tube M1 and the second switch tube M2 turned off.
[0028] exist Figure 4In one embodiment, when the enable signal S3 is invalid, the enable signal S3 is a low-level signal "0". If the first power supply voltage Vs is greater than the sum of the second power supply voltage Vdd and the second reference threshold TH2, the output end of the comparator A outputs a "1" signal, the first input end of the first NAND gate 41 receives the "1" signal, the second input end of the first NAND gate 41 receives the "1" signal, and the first NAND gate 41 outputs a "0" signal. The two input ends of the first OR gate 43 are respectively a "0" signal and a "0" signal, that is, the output "0" signal turns on the first switch tube M1. The first input end of the second NAND gate 42 receives a "0" signal, the second input end of the second NAND gate 42 receives a "1" signal, and the second NAND gate 42 outputs a "1" signal. The two input ends of the second OR gate 44 are respectively a "1" signal and a "0" signal, that is, the output "1" signal turns off the second switch tube M2. If the first power supply voltage Vs is less than the sum of the second power supply voltage Vdd and the first reference threshold TH1, the output terminal of the comparator A outputs a "0" signal, the first input terminal of the first NAND gate 41 receives a "0" signal, the second input terminal of the first NAND gate 41 receives a "1" signal, and the first NAND gate 41 outputs a "1" signal. The two input terminals of the first OR gate 43 are respectively a "1" signal and a "0" signal, that is, the output "1" signal turns off the first switch tube M1. The first input terminal of the second NAND gate 42 receives a "1" signal, the second input terminal of the second NAND gate 42 receives a "1" signal, and the second NAND gate 42 outputs a "0" signal. The two input terminals of the second OR gate 44 are respectively a "0" signal and a "0" signal, that is, the output "0" signal turns on the second switch tube M2.
[0029] Figure 5 A schematic diagram of the circuit structure of a first voltage divider circuit 11 and a second voltage divider circuit 12 according to another embodiment of the present invention is provided. The first voltage divider circuit 11 includes a first voltage divider resistor Z1 and a second voltage divider resistor Z2, and the second voltage divider circuit 12 includes a third voltage divider resistor Z3 and a fourth voltage divider resistor Z4. Figure 3 As shown, no further details are given here. The first voltage-dividing circuit 11 also includes a control switch Km, a third Zener diode D3 and a third capacitor C3. The control switch Km is connected between the first voltage-dividing resistor Z1 and the second voltage-dividing resistor Z2, and outputs a first voltage-dividing signal Vfb1 when the control switch Km is closed. One end of the third Zener diode D3 is coupled between the first voltage-dividing resistor Z1 and the second voltage-dividing resistor Z2, and the other end is coupled to the reference ground GND. One end of the third capacitor C3 is coupled between the first voltage-dividing resistor Z1 and the second voltage-dividing resistor Z2, and the other end is coupled to the reference ground GND. In this way, the first voltage-dividing signal Vfb1 is clamped and filtered. The second voltage-dividing circuit 12 also includes a fourth capacitor C4. One end of the fourth capacitor C4 is coupled between the third voltage-dividing resistor Z3 and the fourth voltage-dividing resistor Z4, and the other end is coupled to the reference ground GND. In this way, the second voltage-dividing signal Vfb2 is filtered.
[0030] In a power supply circuit according to an embodiment of the present invention, the first switch M1 can be controlled to be quickly turned off through the third switch M3, and the second switch M2 can be controlled to be quickly turned off through the fourth switch M4. When the first power supply voltage Vs is powered off so that the first power supply voltage Vs is less than the second power supply voltage Vdd, the third switch tube M3 is turned on and the first switch tube M1 is turned off. When the second power supply voltage Vdd is powered off so that the second power supply voltage Vdd is less than the first power supply voltage Vs, the fourth switch tube M4 is turned on and the second switch tube M2 is turned off. This avoids the problem of current backflow caused by the signal delay output by the channel selection circuit 4.
[0031] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0032] The above-mentioned specific embodiments are only used to illustrate the present invention in an exemplary manner. These embodiments are not completely exhaustive and are not intended to limit the scope of the present invention. It is possible to change and modify the disclosed embodiments, and other feasible optional embodiments and equivalent changes to the elements in the embodiments can be understood by those of ordinary skill in the art. Other changes and modifications to the embodiments disclosed by the present invention do not exceed the spirit of the present invention and the scope of protection defined by the claims.
[0033] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.
Claims
1. A power supply circuit, comprising: A first switch tube has a first end, a second end and a control end, and the first end receives a first power supply voltage; A second switch tube has a first end, a second end and a control end, wherein the first end receives the second power supply voltage, and the second end is coupled to the second end of the first switch tube and outputs the internal power supply voltage; When the first supply voltage is less than the sum of the second supply voltage and the first reference threshold, the first switch tube is turned off, the second switch tube is turned on, and the internal supply voltage is generated according to the second supply voltage; when the first supply voltage is greater than the sum of the second supply voltage and the second reference threshold, the first switch tube is turned on, the second switch tube is turned off, and the internal supply voltage is generated according to the first supply voltage; A third switch tube has a first end, a second end and a control end, wherein the first end receives the second power supply voltage, the second end is coupled to the control end of the first switch tube, and the control end receives the first power supply voltage; as well as A fourth switch tube has a first end, a second end and a control end, wherein the first end receives the first voltage, the second end is coupled to the control end of the second switch tube, and the control end receives the second power supply voltage; Among them, when the first power supply voltage fails and the first power supply voltage is lower than the second power supply voltage, the third switch tube is turned on and the first switch tube is turned off; when the second power supply voltage fails and the second power supply voltage is lower than the first power supply voltage, the fourth switch tube is turned on and the second switch tube is turned off.
2. The power supply circuit according to claim 1, wherein the first reference threshold is equal to the second reference threshold. 3 . The power supply circuit according to claim 1 , wherein the first power supply voltage ranges from 40V to 4V, and the second power supply voltage ranges from 3.5V to 5V. The power supply circuit according to claim 1 , wherein the first switch tube is a P-type field effect transistor.
5. The power supply circuit according to claim 1, further comprising a channel selection circuit, which generates a first switch control signal and a second switch control signal according to the first power supply voltage and the second power supply voltage to control the on and off of the first switch tube and the second switch tube respectively.
6. The power supply circuit according to claim 5, wherein the channel selection circuit comprises: A first voltage-dividing circuit generates a first voltage-dividing signal representing the first power supply voltage according to the first power supply voltage; A second voltage dividing circuit generates a second voltage dividing signal representing the second supply voltage according to the second supply voltage; as well as The logic operation circuit receives the first voltage division signal and the second voltage division signal, and generates the first switch control signal and the second switch control signal according to the first voltage division signal and the second voltage division signal to control the conduction and disconnection of the first switch tube and the second switch tube respectively.
7. The power supply circuit according to claim 6, wherein the logic operation circuit comprises: A comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a first switch control signal, the second input terminal receives a second voltage-divided signal, and the output terminal is coupled to the control terminal of the second switch tube; The inverter has an input end coupled to the output end of the comparator and an output end coupled to the control end of the first switch tube.
8. The power supply circuit according to claim 5, wherein the channel selection circuit further receives an enable signal, and when the enable signal is valid, the first switch control signal turns off the first switch tube, and the second control signal turns off the second switch tube.
9. The power supply circuit according to claim 5, wherein the channel selection circuit comprises: A first voltage-dividing circuit generates a first voltage-dividing signal representing the first power supply voltage according to the first power supply voltage; A second voltage dividing circuit generates a second voltage dividing signal representing the second supply voltage according to the second supply voltage; as well as The logic operation circuit receives a first voltage division signal, a second voltage division signal and an enable signal, wherein when the enable signal is valid, the first switch control signal controls the first switch tube to be turned off, and the second switch control signal controls the second switch tube to be turned off.
10. The power supply circuit according to claim 9, wherein the logic operation circuit comprises: A comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a first voltage-divided signal, and the second input terminal receives a second voltage-divided signal; A first NAND gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the comparator; A first OR gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives an external signal, and the second input terminal is coupled to the output terminal of the first NAND gate; A first resistor, a first end of which is coupled to the output end of the first OR gate, and a second end of which is coupled to the control end of the first switch tube; an inverter, an input terminal of which is coupled to the output terminal of the comparator; A second NAND gate has a first input terminal, a second input terminal and an output terminal, the first input terminal is coupled to the output terminal of the inverter, and the second input terminal is coupled to the second terminal of the first resistor; A second OR gate has a first input terminal, a second input terminal and an output terminal, the first input terminal receives an external signal, and the second input terminal is coupled to the output terminal of the second NAND gate; The second resistor has a first end coupled to the output end of the second OR gate, a second end coupled to the control end of the second switch tube, and a second end coupled to the second input end of the first NAND gate.