Clock signal generation circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a clock signal generation circuit, a chip and electronic equipment, and the clock signal generation circuit comprises a current bias module which is used for outputting bias current; the signal shaping module is used for shaping the oscillation signal to output a target clock signal; wherein the current bias module controls the magnitude of bias current according to an oscillation signal fed back by the crystal oscillation circuit, and the magnitude of the bias current is in negative correlation with the oscillation amplitude of the oscillation signal. The power consumption after the crystal oscillation circuit is started can be reduced while quick starting of the crystal oscillation circuit is guaranteed, and the problem that the power consumption is increased due to the fact that the crystal oscillation circuit still provides large bias current after starting is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock signal generating circuit, a chip and an electronic device. Background Art

[0002] As a clock frequency source, crystal oscillators are widely used in military and civilian consumer electronics fields due to their excellent frequency accuracy and stability compared to other types of oscillators. Taking the Pierce oscillator as an example, the Pierce oscillator mainly includes a bias current generating circuit, a crystal oscillator circuit and a shaping output circuit. The bias current generating circuit can provide a bias current for the crystal oscillator circuit so that the crystal oscillator circuit vibrates based on the bias current and outputs an oscillation signal. The shaping output circuit can shape the oscillation signal to output a square wave clock signal with a duty cycle of 50%.

[0003] In the related art, in order to speed up the startup speed of the Pierce oscillator, a large bias current is often provided to the crystal oscillator circuit at the beginning of the oscillation, so that the crystal oscillator circuit can obtain sufficient energy to start quickly. However, after the crystal oscillator circuit is started, the crystal oscillator circuit usually only needs a small bias current to ensure its normal oscillation. If a large bias current is still provided to the crystal oscillator circuit after the startup is completed, it will lead to the problem of increased power consumption of the Pierce oscillator. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a clock signal generating circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides a clock signal generating circuit, the clock signal generating circuit is used to output a target clock signal according to an oscillation signal output by a crystal oscillator circuit, the crystal oscillator circuit outputs an oscillation signal under bias current control, and the clock signal generating circuit includes:

[0006] A current bias module, the current bias module is used to output a bias current;

[0007] A signal shaping module, the signal shaping module is used to shape the oscillation signal to output a target clock signal;

[0008] The current bias module controls the magnitude of the bias current according to the oscillation signal fed back by the crystal oscillation circuit, and the magnitude of the bias current is negatively correlated with the swing amplitude of the oscillation signal.

[0009] In a second aspect, an embodiment of the present application further provides a chip, comprising the above-mentioned clock signal generating circuit.

[0010] In a third aspect, an embodiment of the present application further provides an electronic device, comprising the above-mentioned chip or clock signal generating circuit.

[0011] The present application outputs a bias current through a current bias module, so that the crystal oscillator circuit can output an oscillation signal under the control of the bias current, and finally uses a signal shaping module to shape the oscillation signal output by the crystal oscillator circuit, so as to output a target clock signal. Since the current bias module can control the magnitude of the bias current according to the oscillation signal fed back by the crystal oscillator circuit, and make the magnitude of the bias current negatively correlated with the swing of the oscillation signal, when the swing of the oscillation signal is small when the crystal oscillator circuit just starts, the current bias module can output a larger bias current according to the oscillation signal fed back by the crystal oscillator circuit, thereby ensuring that the crystal oscillator circuit starts quickly; and when the swing of the oscillation signal is large when the crystal oscillator circuit completes the startup, the current bias module can reduce the bias current according to the oscillation signal fed back by the crystal oscillator circuit, until the bias current output by the current bias module is stable near the minimum current that ensures the normal operation of the crystal oscillator circuit, and finally can ensure that the crystal oscillator circuit starts quickly while reducing the power consumption after the startup is completed, avoiding the problem that the crystal oscillator circuit still provides a larger bias current after the startup is completed, thereby increasing the power consumption.

[0012] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of a Pierce oscillator in the related art is shown.

[0015] Figure 2 A schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0016] Figure 3 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0017] Figure 4 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0018] Figure 5 A schematic diagram showing changes in the second terminal voltage, the second terminal current, and the control terminal voltage of the first transistor in an embodiment of the present application when the first transistor operates in the subthreshold region.

[0019] Figure 6Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0020] Figure 7 Another schematic diagram showing changes in the second terminal voltage, the second terminal current, and the control terminal voltage of the first transistor in the embodiment of the present application when the first transistor operates in the subthreshold region is shown.

[0021] Figure 8 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0022] Fig. 9 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0023] Fig.10 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0024] Fig.11 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0025] Fig.12 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0026] Fig.13 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0027] Fig.14 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0028] Fig.15 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0029] Fig.16 A schematic diagram of a clock signal generating circuit and a crystal oscillator circuit in an embodiment of the present application is shown.

[0030] Fig.17 A schematic diagram of a power supply voltage, a first oscillation signal, a second oscillation signal and a target clock signal in an embodiment of the present application is shown.

[0031] Fig.18 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0032] Fig.19 A schematic diagram of a power supply voltage, an oscillation signal, a reference voltage, and a target clock signal in an embodiment of the present application is shown.

[0033] Fig. 20 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0034] Fig.21 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0035] Fig. 22 Another schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown.

[0036] Among them, 1 is a crystal oscillator circuit, 10 is a current bias module, 11 is a current bias unit, 12 is a gate voltage control unit, 121 is a DC filtering subunit, 122 is a first filtering subunit, 123 is a second filtering subunit, 13 is a bias current output unit, 20 is a signal shaping module, 21 is a reference voltage output unit, 22 is a DC component adjustment unit, and 23 is a comparison unit;

[0037] Bias current IB, oscillation signal XIO, target clock signal CLK, first oscillation signal XO, second oscillation signal XI, AC signal Vac, reference voltage Vref, control terminal voltage VG_M1 of the first transistor, second terminal voltage VD_M1 of the first transistor;

[0038] The first transistor M1, the first capacitor C1, the first resistor R1, the second capacitor C2, the second resistor R2, the third capacitor C3, the third resistor R3, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the first current source IS1, the fourth resistor R4, the fifth resistor R5, the fourth capacitor C4, the fifth capacitor C5, and the sixth resistor R6. DETAILED DESCRIPTION

[0039] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0040] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0041] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0042] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0043] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0044] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0045] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0046] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0047] The control end of each transistor used in the embodiments of the present application is a gate, the first pole / first end of each transistor is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain.

[0048] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0049] At present, crystal oscillators are widely used in military and civilian consumer electronics fields as clock frequency sources due to their excellent frequency accuracy and stability compared with other types of oscillators. Figure 1 , Figure 1 A schematic diagram of a Pierce oscillator in the related art is shown, wherein the Pierce oscillator mainly includes a current source IS that provides a bias current through a power supply terminal VDD, a crystal oscillator circuit composed of a crystal oscillator Y, a capacitor Cx, a capacitor Cy, a feedback resistor R0 and a transistor MN0, and a comparator COMP that compares the voltage across the crystal oscillator Y to output a square wave clock signal.

[0050] During the operation of the Pierce oscillator, due to the negative gain from the gate to the drain of transistor MN0, the gate voltage VG and the drain voltage VD of transistor MN0 are respectively:

[0051] VG=V0-V1Cosωt

[0052] VD=V0+V1cosωt

[0053] Among them, V0 is the offset voltage, V1 is the amplitude of the oscillation signal output by the crystal oscillator Y, and ω is the oscillation frequency of the crystal oscillator Y.

[0054] It can be seen that the gate voltage VG and the drain voltage VD of the transistor MN0 have opposite changing trends, so the comparator COMP can compare the gate voltage of the transistor MN0 with the drain voltage of the transistor MN0 to output the square wave clock signal CLK0.

[0055] In the related art, in order to speed up the startup speed of the Pierce oscillator, the current source IS often provides a large bias current to the crystal oscillator circuit at the beginning of the oscillation, so that the crystal oscillator circuit can obtain sufficient energy to ensure that it can start quickly. However, after the crystal oscillator circuit is started, the crystal oscillator circuit usually only needs a small bias current to ensure its oscillation. If the current source IS still provides a large bias current to the crystal oscillator circuit after the startup is completed, it will cause the problem of increased power consumption of the Pierce oscillator.

[0056] To this end, the present application provides a clock signal generating circuit, chip and electronic device, see Figure 2 , Figure 2 A schematic diagram of a clock signal generating circuit in an embodiment of the present application is shown, wherein the clock signal generating circuit is used to output a target clock signal CLK according to an oscillation signal XIO output by a crystal oscillator circuit 1, and the clock signal generating circuit includes a current bias module 10 and a signal shaping module 20.

[0057] Specifically, the crystal oscillator circuit 1 can output an oscillation signal XIO under the control of the bias current IB. The oscillation signal XIO can be a sine signal and / or a cosine signal, so that the signal shaping module 20 can shape the sine signal and / or the cosine signal and output it as a square wave target clock signal CLK. Generally, the crystal oscillator circuit 1 includes a crystal oscillator (also known as a quartz resonator, or crystal oscillator for short). The crystal oscillator is made of a quartz crystal sheet with a piezoelectric effect. When the crystal oscillator is subjected to an external alternating electric field, mechanical vibrations will be generated. When the frequency of the alternating electric field is the same as the natural frequency of the quartz crystal, a resonance phenomenon can be generated, so that the crystal oscillator circuit 1 can output an oscillation signal XIO.

[0058] It should be pointed out that how the crystal oscillator circuit 1 outputs the oscillation signal XIO according to the bias current IB has been fully explained in the known technology. In order to avoid unnecessary details that make the description of the present invention obscure, this application will not go into details about it. However, it should be understood that the circuit / module having a crystal oscillator and outputting the oscillation signal XIO under the control of the bias current IB should be identified as the crystal oscillator circuit 1 of the present application.

[0059] The current bias module 10 can output a bias current IB to control the crystal oscillator circuit 1 to oscillate and output an oscillation signal XIO through the bias current IB. In some embodiments of the present application, the current bias module 10 can provide the bias current IB by self-biasing without accessing an external control signal. For example, the current bias module 10 can include a self-biased cascode current mirror. After the power supply is powered on, the self-biased cascode current mirror can output the bias current IB to the crystal oscillator circuit 1. In some embodiments of the present application, the current bias module 10 can access an external control signal and provide the bias current IB based on the external control signal. For example, the current bias module 10 can include a voltage-controlled current source. After the power supply is powered on and the voltage-controlled current source receives an external control voltage, the voltage-controlled current source outputs the bias current IB based on the external control voltage that is connected.

[0060] The signal shaping module 20 can shape the oscillation signal XIO output by the crystal oscillator circuit 1, so as to output the target clock signal CLK. In some embodiments of the present application, the crystal oscillator circuit 1 can output two oscillation signals XIO (for example, a sine signal and a cosine signal), and the signal shaping module 20 can output the target clock signal CLK according to the two oscillation signals XIO. For example, the signal shaping module 20 can include a voltage comparison circuit, and the two input ends of the voltage comparison circuit are respectively connected to the two oscillation signals XIO, and the target clock signal CLK as a square wave is output by comparing the levels of the two oscillation signals XIO. In some embodiments of the present application, the signal shaping module 20 can output the target clock signal CLK according to one oscillation signal XIO (for example, a sine signal or a cosine signal). For example, the signal shaping module 20 can include a voltage comparison circuit, and the two input ends of the voltage comparison circuit are respectively connected to one oscillation signal XIO and a fixed reference voltage Vref, and the target clock signal CLK as a square wave is output by comparing the levels of one oscillation signal XIO and the reference voltage Vref.

[0061] In the embodiment of the present application, the current bias module 10 controls the magnitude of the bias current IB according to the oscillation signal XIO fed back by the crystal oscillator circuit 1, and the magnitude of the bias current IB is negatively correlated with the swing amplitude of the oscillation signal XIO. Figure 2 In the figure, before time t0, the clock signal generating circuit is in the startup stage, the swing of the oscillation signal XIO gradually increases, and the current bias module 10 makes the bias current IB gradually decrease according to the oscillation signal fed back by the crystal oscillation circuit 1; and after time t0, the clock signal generating circuit completes the startup, the swing of the oscillation signal XIO stabilizes, and the current bias module 10 makes the bias current IB at the lowest value according to the oscillation signal fed back by the crystal oscillation circuit 1.

[0062] It can be seen that when the swing of the oscillation signal XIO is small when the crystal oscillator circuit 1 just starts, the current bias module 10 can output a larger bias current IB according to the oscillation signal XIO fed back by the crystal oscillator circuit 1, thereby ensuring that the crystal oscillator circuit 1 starts quickly; and when the swing of the oscillation signal XIO is large when the crystal oscillator circuit 1 completes the startup, the current bias module 10 can reduce the bias current IB according to the oscillation signal XIO fed back by the crystal oscillator circuit 1, until the bias current IB output by the current bias module 10 stabilizes near the minimum current that ensures the normal operation of the crystal oscillator circuit 1, which is ultimately beneficial to ensure that the crystal oscillator circuit 1 starts quickly while reducing the power consumption after the startup is completed, and avoiding the problem of the crystal oscillator circuit 1 still providing a large bias current IB after the startup is completed, thereby increasing the power consumption.

[0063] In some embodiments of the present application, the current bias module 10 includes a first transistor M1 operating in a subthreshold region, a current bias unit 11 , a gate voltage control unit 12 , and a bias current output unit 13 .

[0064] Specifically, the current biasing unit 11 can bias the current flowing through the first transistor M1. As an example, refer to Figure 3 , Figure 3 Another schematic diagram of the clock signal generating current in the embodiment of the present application is shown, the first transistor M1 is an NMOS tube, the first end of the first transistor M1 is connected to the ground terminal GND, and the current bias unit 11 can bias the input current of the second end of the first transistor M1. As another exemplary embodiment, refer to Figure 4 , Figure 4 Another schematic diagram of the clock signal generating current in an embodiment of the present application is shown, the first transistor M1 is a PMOS tube, the first end of the first transistor M1 is connected to the power supply terminal VDD, and the current bias unit 11 can bias the output current of the second end of the first transistor M1.

[0065] The gate voltage control unit 12 can control the control terminal voltage VG_M1 of the first transistor M1 to oscillate according to the second terminal voltage VD_M1 of the first transistor M1 and the oscillation signal XIO, and input the DC component of the second terminal voltage VD_M1 of the first transistor M1 into the bias current output unit 13, so that the bias current output unit 13 controls the magnitude of the bias current IB according to the DC component of the second terminal voltage VD_M1 of the first transistor M1.

[0066] For example, Figure 3 For example, the first transistor M1 is an NMOS tube, see Figure 5 , Figure 5FIG. 1 shows a schematic diagram of a change of the second terminal voltage VD_M1, the second terminal current ID_M1, and the control terminal voltage VG_M1 when the first transistor M1 works in the subthreshold region. Since the first transistor M1 works in the subthreshold region, the control terminal voltage VG_M1 of the first transistor M1 is Figure 5 The exponential relationship of the curve (c) is shown in FIG. 1 , and the control terminal voltage VG_M1 of the first transistor M1 and the second terminal current ID_M1 satisfy the following relationship:

[0067]

[0068] Wherein, I0 is a constant (related to the width-to-length ratio of the first transistor M1 ), VTH_M1 is the threshold voltage of the first transistor M1 , and VT is the thermal voltage.

[0069] At the same time, since the gate voltage control unit 12 can control the control terminal voltage VG_M1 of the first transistor M1 to oscillate according to the second terminal voltage VD_M1 of the first transistor M1 and the oscillation signal XIO, the control terminal voltage VG_M1 of the first transistor M1 will be as follows: Figure 5 The curve (d) changes periodically over time and finally changes according to Figure 5 The middle (c) curve and Figure 5 From the curve (d), it can be seen that the second terminal current ID_M1 of the first transistor M1 is as follows Figure 5 The curve in (a) changes periodically over time.

[0070] Since the current biasing unit 11 biases the current flowing through the first transistor M1 and the impedance remains unchanged, the second terminal voltage VD_M1 of the first transistor M1 satisfies the following relationship:

[0071] VD_M1=VDD-ID_M1*r0

[0072] Wherein, r0 is the impedance of the current bias unit 11 .

[0073] According to the above formula, since the second terminal current ID_M1 of the first transistor M1 changes periodically, Figure 5 The variation trend of the variation curve (b) of the voltage VD_M1 at the second end of the first transistor M1 is opposite to the variation trend of the variation curve (a) of the current ID_M1 at the second end of the first transistor M1.

[0074] Combination Figure 5From the curves (a), (b), (c) and (d), it can be seen that in the first half cycle when the control terminal voltage VG_M1 of the first transistor M1 changes, the control terminal voltage VG_M1 of the first transistor M1 is higher than that in the second half cycle, so the average value of the second terminal current ID_M1 of the first transistor M1 in the first half cycle is larger, while the average value of the second terminal voltage VD_M1 of the first transistor M1 in the first half cycle is smaller; and in the second half cycle when the control terminal voltage VG_M1 of the first transistor M1 changes, the control terminal voltage VG_M1 of the first transistor M1 is lower than that in the first half cycle, so the average value of the second terminal current ID_M1 of the first transistor M1 in the second half cycle is smaller, while the average value of the second terminal voltage VD_M1 of the first transistor M1 in the second half cycle is larger.

[0075] On the whole, although the control terminal voltage VG_M1 of the first transistor M1 changes periodically and its average size does not change, since the first transistor M1 operates in the subthreshold region, the average size of the second terminal current ID_M1 of the first transistor M1 is increased, and the average size of the second terminal voltage VD_M1 of the first transistor M1 is reduced. Therefore, after the gate control unit inputs the DC component in the second terminal voltage VD_M1 of the first transistor M1 into the bias current output unit 13, this is equivalent to reducing the control voltage of the bias current output unit 13. Therefore, the size of the bias current IB output by the bias current output unit 13 can be reduced according to the reduced control voltage.

[0076] For example, see Figure 6 , Figure 6 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. The bias current output unit 13 includes an NMOS tube MN1. The gate control unit inputs the DC component in the second terminal voltage VD_M1 of the first transistor M1 into the gate of the NMOS tube MN1. Since the average magnitude of the second terminal voltage VD_M1 of the first transistor M1 is reduced, the gate voltage of the NMOS tube MN1 is also reduced, thereby reducing the current flowing through the NMOS tube MN1, and finally reducing the bias current IB of the input crystal oscillator circuit 1 and achieving the purpose of reducing power consumption.

[0077] As another example, Figure 4 For example, the first transistor M1 is a PMOS tube, see Figure 7 , Figure 7 FIG. 1 shows a schematic diagram of a change of the second terminal voltage VD_M1, the second terminal current ID_M1, and the control terminal voltage VG_M1 of the first transistor M1 when the first transistor M1 works in the subthreshold region. Since the first transistor M1 works in the subthreshold region, the control terminal voltage VG_M1 of the first transistor M1 is Figure 7The exponential relationship of the curve (c) is shown in FIG. 1 , and the control terminal voltage VG_M1 of the first transistor M1 and the second terminal current ID_M1 satisfy the following relationship:

[0078]

[0079] Wherein, I0 is a constant (related to the width-to-length ratio of the first transistor M1 ), VTH_M1 is the threshold voltage of the first transistor M1 , and VT is the thermal voltage.

[0080] At the same time, since the gate voltage control unit 12 can control the control terminal voltage VG_M1 of the first transistor M1 to oscillate according to the second terminal voltage VD_M1 of the first transistor M1 and the oscillation signal XIO, the control terminal voltage VG_M1 of the first transistor M1 will be as follows: Figure 7 The curve (d) changes periodically over time and finally changes according to Figure 7 The middle (c) curve and Figure 7 From the curve (d), it can be seen that the second terminal current ID_M1 of the first transistor M1 is as follows Figure 7 The curve in (a) changes periodically over time.

[0081] Since the current biasing unit 11 biases the current flowing through the first transistor M1 and the impedance remains unchanged, the second terminal voltage VD_M1 of the first transistor M1 satisfies the following relationship:

[0082] VD_M1=ID_M1*r0

[0083] Wherein, r0 is the output impedance of the current bias unit 11 .

[0084] According to the above formula, since the second terminal current ID_M1 of the first transistor M1 changes periodically, Figure 7 The variation trend of the variation curve (b) of the voltage VD_M1 at the second end of the first transistor M1 is the same as the variation curve (a) of the current ID_M1 at the second end of the first transistor M1.

[0085] Combination Figure 7From the curves (a), (b), (c) and (d), it can be seen that in the first half cycle when the control terminal voltage VG_M1 of the first transistor M1 changes, the control terminal voltage VG_M1 of the first transistor M1 is higher than that in the second half cycle, so the average value of the second terminal current ID_M1 of the first transistor M1 in the first half cycle is smaller, and the average value of the second terminal voltage VD_M1 of the first transistor M1 in the first half cycle is smaller; and in the second half cycle when the control terminal voltage VG_M1 of the first transistor M1 changes, the control terminal voltage VG_M1 of the first transistor M1 is lower than that in the first half cycle, so the average value of the second terminal current ID_M1 of the first transistor M1 in the second half cycle is larger, and the average value of the second terminal voltage VD_M1 of the first transistor M1 in the second half cycle is larger.

[0086] On the whole, although the control terminal voltage VG_M1 of the first transistor M1 changes periodically and its average size does not change, since the first transistor M1 operates in the subthreshold region, the average size of the second terminal current ID_M1 of the first transistor M1 is increased, and the average size of the second terminal voltage VD_M1 of the first transistor M1 is also increased. Therefore, after the gate control unit inputs the DC component in the second terminal voltage VD_M1 of the first transistor M1 into the bias current output unit 13, this is equivalent to increasing the control voltage of the bias current output unit 13. Therefore, the size of the bias current IB output by the bias current output unit 13 can be reduced according to the increased control voltage.

[0087] For example, see Figure 8 , Figure 8 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown. The bias current output unit 13 includes a PMOS tube MP1. The gate control unit inputs the DC component in the second terminal voltage VD_M1 of the first transistor M1 into the gate of the PMOS tube MP1. Since the average magnitude of the second terminal voltage VD_M1 of the first transistor M1 is increased, the gate voltage of the PMOS tube MP1 is also increased, thereby reducing the current flowing through the PMOS tube MP1, and finally reducing the bias current IB of the input crystal oscillator circuit 1 and achieving the purpose of reducing power consumption.

[0088] In summary Figure 5 as well as Figure 7It can be seen that when the first transistor M1 is an NMOS tube, the change voltage △V of the second terminal voltage VD_M1 of the first transistor M1 is a negative value, and when the swing of the oscillation signal XIO is larger, which makes the oscillation swing of the control terminal voltage VG_M1 of the first transistor M1 larger, the change voltage △V corresponding to the second terminal voltage VD_M1 of the first transistor M1 is larger, that is, at this time, the DC component in the second terminal voltage VD_M1 of the first transistor M1 is negatively correlated with the swing of the oscillation signal XIO; when the first transistor M1 is a PMOS tube, the change voltage △V of the second terminal voltage VD_M1 of the first transistor M1 is a positive value, and when the swing of the oscillation signal XIO is larger, which makes the oscillation swing of the control terminal voltage VG_M1 of the first transistor M1 larger, the change voltage △V corresponding to the second terminal voltage VD_M1 of the first transistor M1 is larger, that is, at this time, the DC component in the second terminal voltage VD_M1 of the first transistor M1 is positively correlated with the swing of the oscillation signal XIO. That is to say, the DC component in the second terminal voltage VD_M1 of the first transistor M1 is positively correlated or negatively correlated with the swing of the oscillation signal XIO, which can enable the bias current output unit 13 to further reduce the bias current IB input to the crystal oscillator circuit 1, and ultimately make the magnitude of the bias current IB negatively correlated with the swing of the oscillation signal XIO.

[0089] In some embodiments of the present application, see Fig. 9 , Fig. 9 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, the gate voltage control unit 12 includes a DC filtering subunit 121, a first filtering subunit 122 and a second filtering subunit 123; the DC filtering subunit 121 is used to filter out the DC component in the oscillation signal XIO, so as to input the AC component in the oscillation signal XIO into the control end of the first transistor M1; the first filtering subunit 122 is used to filter out the AC component in the second terminal voltage VD_M1 of the first transistor M1, so as to input the DC component of the second terminal voltage VD_M1 of the first transistor M1 into the control end of the first transistor M1; the second filtering subunit 123 is used to filter out the AC component in the second terminal voltage VD_M1 of the first transistor M1, so as to input the DC component in the second terminal voltage VD_M1 of the first transistor M1 into the bias current output unit 13.

[0090] For example, the first filter subunit 122 and the second filter subunit 123 filter out the AC component in the second terminal voltage VD_M1 of the first transistor M1 and output the DC component of the second terminal voltage VD_M1 of the first transistor M1 as Vx, and the control terminal oscillation signal XIO input to the first transistor M1 satisfies the following formula:

[0091] XIO=Vy+V1Cosωt

[0092] Wherein, Vy is the offset voltage, V1 is the swing amplitude of the oscillation signal XIO, and ω is the oscillation frequency of the oscillation signal XIO.

[0093] After the DC filtering subunit 121 filters out the DC component in the oscillation signal XIO, the AC component in the oscillation signal XIO input to the control terminal of the first transistor M1 by the DC filtering subunit 121 is: V1Cosωt, combined with the DC component Vx of the second terminal voltage VD_M1 output by the first filtering subunit 122, the control terminal voltage VG_M1 of the first transistor M1 is:

[0094] VG_M1=Vx+V1Cosωt

[0095] Therefore, according to the DC filtering subunit 121 and the first filtering subunit 122 in the above embodiment, the DC component of the second terminal voltage VD_M1 of the first transistor M1 and the AC component of the oscillation signal XIO can be input to the control terminal of the first transistor M1, so that the control terminal voltage VG_M1 of the first transistor M1 oscillates. At the same time, through the second filtering subunit 123 in the above embodiment, the DC component in the second terminal voltage VD_M1 of the first transistor M1 can be input to the bias current output unit 13, so that the bias current output unit 13 controls the magnitude of the bias current IB according to the DC component in the second terminal voltage VD_M1 of the first transistor M1.

[0096] It can be understood that the above embodiment only filters out the DC component in the oscillation signal XIO, so that the control terminal voltage VG_M1 of the first transistor M1 oscillates with the help of the AC component in the oscillation signal XIO. In some possible embodiments, the oscillation signal XIO can also be processed and converted (for example, amplified by an amplifier circuit) and then input into the control terminal of the first transistor M1, so that the control terminal voltage VG_M1 of the first transistor M1 oscillates.

[0097] As an example, see Fig.10 , Fig.10Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the DC filtering subunit 121 includes a first capacitor C1, the first filtering subunit 122 includes a first resistor R1 and a second capacitor C2, and the second filtering subunit 123 includes a second resistor R2 and a third capacitor C3; the first end of the first capacitor C1 is used to access the oscillation signal XIO, and the second end of the first capacitor C1 is connected to the control end of the first transistor M1; the first end of the first resistor R1 is connected to the control end of the first transistor M1, the second end of the first resistor R1 is connected to the second end of the first transistor M1, the first end of the second capacitor C2 is connected to the control end of the first transistor M1, and the second end of the second capacitor C2 is connected to the first end of the first transistor M1; the first end of the second resistor R2 is connected to the second end of the first transistor M1, the second end of the second resistor R2 is connected to the bias current output unit 13, the first end of the third capacitor C3 is connected to the second end of the second resistor R2, and the second end of the third capacitor C3 is connected to the first end of the first transistor M1.

[0098] In the above embodiment, since the first capacitor C1 has the characteristic of passing AC and blocking DC, the first capacitor C1 can be used to filter out the DC component in the oscillation signal XIO, and the AC component in the oscillation signal XIO is input to the control end of the first transistor M1; at the same time, since the first resistor R1 and the second capacitor C2 form an RC filter circuit, the AC component in the second terminal voltage VD_M1 of the first transistor M1 can be filtered out, and the DC component of the second terminal voltage VD_M1 of the first transistor M1 is input to the control end of the first transistor M1; in addition, since the second resistor R2 and the third capacitor C3 also form an RC filter circuit, the AC component in the second terminal voltage VD_M1 of the first transistor M1 can be filtered out (and the AC component in the oscillation signal XIO can also be filtered out), so that the DC component of the second terminal voltage VD_M1 of the first transistor M1 is input to the bias current output unit 13.

[0099] It can be understood that the above embodiment uses a capacitor to realize the function of the DC filtering subunit 121, and a first-order low-pass RC filter circuit to realize the functions of the first filtering subunit 122 and the second filtering subunit 123, which should not be understood as a limitation on the DC filtering subunit 121, the first filtering subunit 122 and the second filtering subunit 123 of the present application. In some possible embodiments, the drain and the source of the MOS tube can also be short-circuited, so that the substrate metal plate and the gate metal plate of the MOS tube form a capacitor structure and realize the function of the DC filtering subunit 121 to pass AC signals and block DC signals; or, a second-order or third-order low-pass RC filter circuit can also be used to realize the function of the first filtering subunit 122 and the second filtering subunit 123 to pass DC signals and block AC signals.

[0100] In some embodiments of the present application, for example, in an embodiment where the first transistor M1 is a PMOS transistor, see Fig.11 , Fig.11 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the bias current output unit 13 includes a second transistor M2; the control end of the second transistor M2 is connected to the output end of the second filter subunit 123, the first end of the second transistor M2 is connected to the power supply end VDD, and the second end of the second transistor M2 is used to output the bias current IB.

[0101] exist Fig.11 In the embodiment, since the first transistor M1 is a PMOS tube and the first transistor M1 operates in the subthreshold region, after the AC component of the oscillation signal XIO is applied to the control terminal of the first transistor M1 through the first capacitor C1, the average magnitude of the second terminal voltage VD_M1 of the first transistor M1 will increase. Therefore, after the second terminal voltage VD_M1 of the first transistor M1 is filtered through the second resistor R2 and the third capacitor C3 and input to the control terminal of the second transistor M2, the control terminal voltage of the second transistor M2, which is a PMOS tube, will increase, thereby reducing the bias current IB output by the second transistor M2, so as to achieve the purpose of reducing the power consumption of the crystal oscillator circuit 1.

[0102] In some embodiments of the present application, for example, in an embodiment where the first transistor M1 is an NMOS transistor, see Fig.12 , Fig.12 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the bias current output unit 13 includes a second transistor M2, a third transistor M3 and a fourth transistor M4; the first end of the third transistor M3 is connected to the power supply end VDD, and the control end of the third transistor M3 is connected to the second end; the control end of the second transistor M2 is connected to the output end of the second filtering sub-unit 123, the second end of the second transistor M2 is connected to the second end of the third transistor M3, and the first end of the second transistor M2 is connected to the ground end GND; the first end of the fourth transistor M4 is connected to the power supply end VDD, the control end of the fourth transistor M4 is connected to the control end of the third transistor M3, and the second end of the fourth transistor M4 is used to output the bias current IB.

[0103] It should be noted that, since the first transistor M1 is an NMOS tube and the first transistor M1 operates in the subthreshold region, after the AC component of the oscillation signal XIO is applied to the control end of the first transistor M1 through the first capacitor C1, the average magnitude of the second-end voltage VD_M1 of the first transistor M1 will be reduced, and after the second-end voltage VD_M1 of the first transistor M1 is filtered through the second resistor R2 and the third capacitor C3 and input to the control end of the second transistor M2, the control end voltage of the second transistor M2, which is an NMOS tube, will be reduced, thereby reducing the current of the branch where the second transistor M2 and the third transistor M3 are located; at the same time, since the third transistor M3 and the fourth transistor M4 are current mirrors to each other, the fourth transistor M4 will proportionally mirror the current of the third transistor M3, so after the current of the branch where the second transistor M2 and the third transistor M3 are located is reduced, the bias current IB output by the fourth transistor M4 can be reduced, so as to achieve the purpose of reducing the power consumption of the crystal oscillator circuit 1.

[0104] In some embodiments of the present application, see Fig.13 , Fig.13 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the current biasing unit 11 includes a fifth transistor M5; the first end of the fifth transistor M5 is connected to the power supply end VDD, the second end of the fifth transistor M5 is connected to the second end of the first transistor M1, and the control end of the fifth transistor M5 is connected to the control end of the third transistor M3. It can be seen that at this time, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4 and the fifth transistor M5 form a self-biased common source and common gate current mirror. After the power supply is powered on, the self-biased common source and common gate current mirror can output a bias current IB to the crystal oscillator circuit 1, and at the same time, the control end voltage of the fifth transistor M5 is biased by the second end voltage of the third transistor M3, so that the fifth transistor M5 can bias the current flowing through the first transistor.

[0105] In some embodiments of the present application, see Fig.14 , Fig.14 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the current bias unit 11 includes a first current source IS1, a first end of the first transistor M1 is connected to the ground end GND, an input end of the first current source IS1 is connected to the power supply end VDD, and an output end of the first current source IS1 is connected to the second end of the first transistor M1, so that the first current source IS1 providing input current can bias the current flowing through the first transistor M1.

[0106] It can be understood that the above embodiment takes the first transistor M1 as an NMOS tube as an example to illustrate the electrical connection relationship of the first current source IS1. When the first transistor M1 is a PMOS tube, refer to Fig.15 , Fig.15 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, in which the first end of the first transistor M1 is connected to the power supply terminal VDD, the input end of the first current source IS1 is connected to the second end of the first transistor M1, and the output end of the first current source IS1 is connected to the ground terminal GND. Therefore, the first current source IS1 connected to the ground terminal GND can bias the output current of the first transistor M1.

[0107] In some embodiments of the present application, the oscillation signal XIO includes a first oscillation signal XO and a second oscillation signal XI, the phase difference between the first oscillation signal XO and the second oscillation signal XI is 180°, and the signal shaping module 20 outputs the target clock signal CLK according to the first oscillation signal XO or the second oscillation signal XI.

[0108] For example, see Fig.16 , Fig.16 A schematic diagram of a clock signal generating circuit and a crystal oscillator circuit 1 in an embodiment of the present application is shown, wherein the crystal oscillator circuit 1 includes a crystal oscillator Y0, a feedback resistor Rf, a capacitor C01, a capacitor C02 and a sixth transistor M6. When the fourth transistor M4 inputs a bias current IB, the crystal oscillator Y0 starts to oscillate. Due to the transconductance of the sixth transistor M6, the two ends of the crystal oscillator Y0 can respectively output a first oscillation signal XO and a second oscillation signal XI with a phase difference of 180°. The signal shaping module 20 can output a target clock signal CLK according to the first oscillation signal XO (i.e., the drain voltage of the sixth transistor M6).

[0109] It should be noted that, in general, the power supply voltage VDD has a jitter phenomenon, so the first oscillation signal XO and the second oscillation signal XI will include a low-frequency jitter voltage of the power supply voltage VDD. Fig.17 , Fig.17 A schematic diagram of the power supply voltage, the first oscillation signal XO, the second oscillation signal XI and the target clock signal CLK in an embodiment of the present application is shown. The low-frequency jitter voltage change trends of the power supply voltage VDD contained in the first oscillation signal XO and the second oscillation signal XI are opposite. Due to the influence of the low-frequency jitter voltage caused by the power supply voltage VDD, the voltage of the first oscillation signal XO is lower than the voltage of the second oscillation signal XI for a longer period of time in the same cycle, and the voltage of the first oscillation signal XO is higher than the voltage of the second oscillation signal XI for a shorter period of time in the same cycle, thereby making the high-level duration and low-level duration of the target clock signal CLK output by the signal shaping module 20 not equal, which leads to the phenomenon that the duty cycle of the target clock signal CLK is not 50%.

[0110] In the above embodiment, since the signal shaping module 20 outputs the target clock signal CLK according to the first oscillation signal XO or the second oscillation signal XI, it can be avoided that the first oscillation signal XO and the second oscillation signal XI contain opposite low-frequency jitter voltages, which ultimately causes the duty cycle of the target clock signal CLK to be not 50%.

[0111] In some embodiments of the present application, see Fig.18 , Fig.18 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the signal shaping module 20 includes a reference voltage output unit 21, a DC component adjustment unit 22 and a comparison unit 23; the reference voltage output unit 21 outputs a reference voltage Vref according to the power supply voltage; the DC component adjustment unit 22 is used to output an AC signal Vac according to the first oscillation signal XO and the second oscillation signal XI, and the reference voltage Vref; the first input end of the comparison unit 23 is used to access the AC signal Vac, and the second input end of the comparison unit 23 is used to access the reference voltage Vref, so as to compare the AC signal Vac with the reference voltage Vref and output the target clock signal CLK.

[0112] It should be noted that the reference voltage output unit 21 can output the reference voltage Vref that follows the jitter of the power supply voltage VDD, and the AC signal Vac output by the DC component adjustment unit 22 is equal to the amplitude, frequency and phase of the first oscillation signal XO, or the AC signal Vac is equal to the amplitude, frequency and phase of the second oscillation signal XI. For example, Fig.18 In the embodiment, the DC component adjustment unit 22 outputs the AC signal Vac according to the first oscillation signal XO and the reference voltage Vref. Therefore, the AC signal Vac output by the DC component adjustment unit 22 is equal to the amplitude, frequency and phase of the first oscillation signal XO.

[0113] Meanwhile, for the reference voltage Vref and the AC signal Vac, the offset voltage of the AC signal Vac is equal to the reference voltage Vref. Fig.19 , Fig.19 Another schematic diagram of the power supply voltage, the oscillation signal XIO, the reference voltage Vref and the target clock signal CLK in the embodiment of the present application is shown. The offset voltage of the AC signal Vac is equal to the reference voltage Vref and follows the jitter of the power supply voltage VDD, that is, the AC signal Vac satisfies the following relationship:

[0114] Vac=Vref+V1Cosωt

[0115] Wherein, Vref is the reference voltage Vref, V1 is the swing amplitude of the oscillation signal XIO, and ω is the oscillation frequency of the oscillation signal XIO.

[0116] It can be seen that for the AC signal Vac and the reference voltage Vref input to the comparison unit 23, the low-frequency jitter voltage caused by the jitter of the power supply voltage VDD is offset by the common mode, and the comparison unit 23 is actually judging the positive or negative of the V1Cosωt term in the above formula. Therefore, the clock signal output by the comparison unit 23 will not be affected by the low-frequency jitter voltage caused by the jitter of the power supply voltage VDD, so that the comparison unit 23 can output the target clock signal CLK with a duty cycle of 50%.

[0117] In some embodiments of the present application, see Fig. 20 , Fig. 20 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, wherein the reference voltage output unit 21 includes a fourth resistor R4 and a fifth resistor R5; the first end of the fourth resistor R4 is connected to the power supply terminal VDD, the second end of the fourth resistor R4 is connected to the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is connected to the ground terminal GND; the first node m1 between the fourth resistor R4 and the fifth resistor R5 is used to output the reference voltage Vref. That is, the fourth resistor R4 and the fifth resistor R5 are connected in series between the power supply terminal VDD and the ground terminal GND, so the first node m1 can output the reference voltage Vref that jitters with the power supply voltage VDD, so that the comparison unit 23 outputs the target clock signal CLK with a duty cycle of 50% according to the reference voltage Vref and the AC signal Vac.

[0118] In some embodiments of the present application, see Fig.21 , Fig.21 Another schematic diagram of the clock signal generating circuit in an embodiment of the present application is shown, wherein the DC component adjustment unit 22 includes a fourth capacitor C4, a fifth capacitor C5 and a sixth resistor R6; the first end of the fourth capacitor C4 is used to connect the first oscillation signal XO or the second oscillation signal XI, and the second end of the fourth capacitor C4 is connected to the first input end of the comparison unit 23; the first end of the fifth capacitor C5 is connected to the first node m1, and the second end of the fifth capacitor C5 is connected to the ground terminal GND; the first end of the sixth resistor R6 is connected to the first node m1, and the second end of the sixth resistor R6 is connected to the first input end of the comparison unit 23.

[0119] It should be noted that, due to the characteristic of the fourth capacitor C4 that it passes AC and blocks DC, the fourth capacitor C4 can input the AC component of the oscillation signal XIO (the first oscillation signal or the second oscillation signal XI) into the first input terminal of the comparison unit 23; at the same time, due to the filter capacitor composed of the fifth capacitor C5 and the sixth resistor R6, not only can the AC component of the oscillation signal XIO be prevented from being input into the second input terminal of the comparison unit 23, but the low-frequency jitter reference voltage Vref can also be input into the first input terminal of the comparison unit 23, so that the AC signal Vac satisfies the relationship Vac=Vref+V1Cosωt, that is, the offset voltage of the AC signal Vac is equal to the reference voltage Vref, so that the offset voltage of the AC signal Vac and the reference voltage Vref are offset in common mode in the comparison unit 23, so that the comparison unit 23 outputs the target clock signal according to the AC component (i.e., V1Cosωt) in the oscillation signal XIO.

[0120] As an exemplary embodiment of the comparison unit 23, see Fig. 22 , Fig. 22 Another schematic diagram of the clock signal generating circuit in the embodiment of the present application is shown, the comparison unit 23 includes transistors M7 to M13, wherein the transistor M7 and the transistor M8 form a differential input pair, the gate of the transistor M7 is connected to the AC signal Vac as the first input terminal of the comparison unit 23, the gate of the transistor M8 is connected to the reference voltage Vref as the second input terminal of the comparison unit 23, the gate of the transistor M13 is biased by the drain voltage of the third transistor M3 to provide a bias current IB for the differential input pair, the transistor M9 and the transistor M11 are a group of current mirrors connected to the drains of the transistor M7 and the transistor M8, and the transistor M10 and the transistor M12 are another group of current mirrors connected to the drains of the transistor M7 and the transistor M8.

[0121] When the voltage of the AC signal Vac is greater than the reference voltage Vref, the current output by the transistor M8 is greater than the current output by the transistor M7. Under the current mirroring effect of the transistor M10 and the transistor M12, the current output by the transistor M7 is less than the current input to the transistor M12. Therefore, the drain voltage of the transistor M7 is pulled down, which is equivalent to outputting a low-level voltage of the target clock signal CLK. On the contrary, when the voltage of the AC signal Vac is less than the reference voltage Vref, the current output by the transistor M8 is less than the current output by the transistor M7. Under the current mirroring effect of the transistor M10 and the transistor M12, the current output by the transistor M7 is greater than the current input to the transistor M12. Therefore, the drain voltage of the transistor M7 is pulled up, which is equivalent to outputting a high-level voltage of the target clock signal CLK. Therefore, the target clock signal CLK with periodic changes and a duty cycle of 50% can be finally output through the above-mentioned comparison unit 23.

[0122] It should be noted that the above contents about the clock signal generating circuit are intended to clearly illustrate the implementation verification process of the present application. Under the guidance of the present application, those skilled in the art can also make equivalent modified designs. For example, Fig. 20 In the embodiment, a second-order or third-order low-pass RC filter circuit may be used to replace the first-order RC filter circuit composed of the fifth capacitor C5 and the sixth resistor R6; for example, in Fig. 20 In the embodiment, the comparison unit 23 is a single-limit comparator. In some possible embodiments, the comparison unit 23 may also be a hysteresis comparator or a window comparator.

[0123] The embodiment of the present application also provides a chip, which includes the above-mentioned clock signal generating circuit. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip) chip or a SIP (system in package) chip. Since the chip of the present application has the clock signal generating circuit described in the above embodiment, it has all the beneficial effects of the clock signal generating circuit in the above embodiment, which will not be repeated here.

[0124] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control screen, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0125] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A clock signal generating circuit, characterized in that: The clock signal generating circuit is used to output a target clock signal according to an oscillation signal output by a crystal oscillator circuit, wherein the crystal oscillator circuit outputs the oscillation signal under bias current control, and the clock signal generating circuit comprises: A current bias module, the current bias module is used to output the bias current; A signal shaping module, the signal shaping module is used to shape the oscillation signal to output the target clock signal; The current bias module controls the magnitude of the bias current according to the oscillation signal fed back by the crystal oscillator circuit, and the magnitude of the bias current is negatively correlated with the swing amplitude of the oscillation signal.

2. The clock signal generating circuit according to claim 1, wherein: The current bias module includes a first transistor, a current bias unit, a gate voltage control unit and a bias current output unit; The current bias unit is used to bias the current flowing through the first transistor, and the gate voltage control unit controls the control terminal voltage of the first transistor to oscillate according to the second terminal voltage of the first transistor and the oscillation signal; The bias current output unit controls the magnitude of the bias current according to the DC component in the second terminal voltage of the first transistor; Among them, the first transistor operates in the subthreshold region, the gate voltage control unit inputs the DC component in the second terminal voltage of the first transistor into the bias current output unit, and the DC component in the second terminal voltage of the first transistor is positively correlated or negatively correlated with the swing amplitude of the oscillation signal.

3. The clock signal generating circuit according to claim 2, wherein: The gate voltage control unit includes a DC filtering subunit, a first filtering subunit and a second filtering subunit; The DC filtering subunit is used to filter out the DC component in the oscillation signal so as to input the AC component in the oscillation signal into the control terminal of the first transistor; The first filtering subunit is used to filter out the AC component in the voltage at the second terminal of the first transistor, so as to input the DC component of the voltage at the second terminal of the first transistor into the control terminal of the first transistor; The second filtering subunit is used for filtering out the AC component in the second terminal voltage of the first transistor, so as to input the DC component in the second terminal voltage of the first transistor into the bias current output unit.

4. The clock signal generating circuit according to claim 3, characterized in that: The DC filtering subunit includes a first capacitor, the first filtering subunit includes a first resistor and a second capacitor, and the second filtering subunit includes a second resistor and a third capacitor; The first end of the first capacitor is used to access the oscillation signal, and the second end of the first capacitor is connected to the control end of the first transistor; A first end of the first resistor is connected to the control end of the first transistor, a second end of the first resistor is connected to the second end of the first transistor, a first end of the second capacitor is connected to the control end of the first transistor, and a second end of the second capacitor is connected to the first end of the first transistor; The first end of the second resistor is connected to the second end of the first transistor, the second end of the second resistor is connected to the bias current output unit, the first end of the third capacitor is connected to the second end of the second resistor, and the second end of the third capacitor is connected to the first end of the first transistor.

5. The clock signal generating circuit according to claim 3, wherein: The bias current output unit includes a second transistor; The control end of the second transistor is connected to the output end of the second filter subunit, the first end of the second transistor is connected to the power supply end, and the second end of the second transistor is used to output the bias current.

6. The clock signal generating circuit according to claim 3, characterized in that: The bias current output unit includes a second transistor, a third transistor and a fourth transistor; The first end of the third transistor is connected to the power supply end, and the control end of the third transistor is connected to the second end of the third transistor; The control end of the second transistor is connected to the output end of the second filter subunit, the second end of the second transistor is connected to the second end of the third transistor, and the first end of the second transistor is connected to the ground end; The first end of the fourth transistor is connected to the power supply end, the control end of the fourth transistor is connected to the control end of the third transistor, and the second end of the fourth transistor is used to output the bias current.

7. The clock signal generating circuit according to claim 6, wherein: The current bias unit includes a fifth transistor; The first end of the fifth transistor is connected to the power supply end, the second end of the fifth transistor is connected to the second end of the first transistor, and the control end of the fifth transistor is connected to the control end of the third transistor.

8. The clock signal generating circuit according to claim 2, wherein: The current bias unit includes a first current source; The first terminal of the first transistor is connected to a power supply terminal, the input terminal of the first current source is connected to the second terminal of the first transistor, and the output terminal of the first current source is connected to a ground terminal; or The first terminal of the first transistor is connected to the ground terminal, the input terminal of the first current source is connected to the power supply terminal, and the output terminal of the first current source is connected to the second terminal of the first transistor.

9. The clock signal generating circuit according to claim 1, wherein: The oscillation signal includes a first oscillation signal and a second oscillation signal, and a phase difference between the first oscillation signal and the second oscillation signal is 180°; The signal shaping module outputs the target clock signal according to the first oscillation signal or the second oscillation signal.

10. The clock signal generating circuit according to claim 9, characterized in that: The signal shaping module includes a reference voltage output unit, a DC component adjustment unit and a comparison unit; The reference voltage output unit outputs a reference voltage according to the power supply voltage, and the reference voltage follows the power supply voltage jitter; The DC component adjustment unit is used to output an AC signal according to one of the first oscillation signal and the second oscillation signal and the reference voltage, wherein the offset voltage of the AC signal is equal to the reference voltage; The first input terminal of the comparison unit is used to access the AC signal, and the second input terminal of the comparison unit is used to access the reference voltage, so as to compare the AC signal with the reference voltage and output the target clock signal.

11. The clock signal generating circuit according to claim 10, wherein: The reference voltage output unit includes a fourth resistor and a fifth resistor; The first end of the fourth resistor is connected to the power supply end, the second end of the fourth resistor is connected to the first end of the fifth resistor, and the second end of the fifth resistor is connected to the ground end; A first node between the fourth resistor and the fifth resistor is used to output the reference voltage.

12. The clock signal generating circuit according to claim 11, wherein: The DC component adjustment unit includes a fourth capacitor, a fifth capacitor and a sixth resistor; The first end of the fourth capacitor is used to receive the first oscillation signal or the second oscillation signal, and the second end of the fourth capacitor is connected to the first input end of the comparison unit; The first end of the fifth capacitor is connected to the first node, and the second end of the fifth capacitor is connected to the ground end; A first end of the sixth resistor is connected to the first node, and a second end of the sixth resistor is connected to the first input end of the comparison unit.

13. A chip, characterized in that: The method comprises a clock signal generating circuit as claimed in any one of claims 1 to 12.

14. An electronic device, characterized in that: Comprising the chip as claimed in claim 13.

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