Hybrid mode driver circuit suitable for high-speed SerDes
By designing a hybrid mode driver circuit in a high-speed SerDes circuit, combining NMOS and PMOS tubes and bias current sources, the problem of existing differential drivers being difficult to take into account low power consumption and high output swing, achieving low power consumption and high equalization Effective circuit design.
Patent Information
- Application Number
- CN202411286053.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2024-12-31
AI Technical Summary
Existing differential drivers are difficult to take into account both low power consumption and high output swing. Especially in high-speed SerDes circuits, the current-mode driver consumes a large power consumption while the voltage-mode driver is slow, making it impossible to achieve both low power consumption and high swing at the same time.
A hybrid mode driver circuit is designed, using a combination of NMOS and PMOS tubes to control the output signal by biasing the current source and inverter, to realize the opening and closing of the current mode driver, adjust the output swing, and combine it with a 3tap pre-emphasis circuit. Optimize the number of drive modules and tap coefficients.
While ensuring the equalization effect, the overall power consumption of the circuit is significantly reduced, and by adjusting the output swing, the high output swing at low power consumption is achieved, which is suitable for high-speed SerDes circuits.
Smart Images
Figure CN119232139A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of high-speed interface circuits, and in particular to a hybrid mode driver circuit suitable for high-speed SerDes. Background Art
[0002] The interface circuit usually includes a transmitter and a receiver. The transmitter is responsible for sending the data signal to be transmitted, and the receiver is responsible for receiving these data signals. Since long-distance transmission is often required and the transmission channel has non-ideal characteristics, how to prevent the data signal from being distorted during the transmission process is the key to the design of the interface circuit.
[0003] SerDes is the abbreviation of serializer and deserializer. As an interface circuit, its principle is to convert parallel multi-channel low-speed data signals into a serial single-channel high-speed data signal through a serializer at the signal transmitting end, and then transmit the signal to the receiving end through a transmission line for deserialization and data recovery, so as to achieve successful data transmission. In the currently commonly used high-speed SerDes circuit, the transmitter usually includes a parallel-to-serial conversion module and a driver module.
[0004] Compared with single-ended drivers, differential drivers have larger output swings and are suitable for transmitting long-distance high-speed signals. According to the driving method of differential drivers, they can be mainly divided into two types: current mode drivers and voltage mode drivers. Current mode drivers are easy to balance, have strong driving capabilities, fast speeds, and have larger output swings, but also consume more power; voltage mode drivers have smaller currents and therefore lower power consumption, but are slower. Therefore, it is difficult for existing differential drivers to take into account both low power consumption and high swings. Summary of the invention
[0005] In view of the shortcomings of the prior art, the present application provides a hybrid mode driver circuit suitable for high-speed SerDes, which significantly reduces the power consumption of the entire circuit and can also adjust the output swing, thereby achieving high output swing with low power consumption.
[0006] In a first aspect, a hybrid mode driver circuit suitable for high-speed SerDes is provided, comprising: an NMOS tube N1, an NMOS tube N2, a PMOS tube P1, a PMOS tube P2, a PMOS tube P4, a PMOS tube P5 and a bias current source I1;
[0007] The gate of the NMOS tube N1 is connected to the gate of the PMOS tube P1 to receive the input signal Vin-p, and the input signal Vin-p is any one of the pre-marked data signal Pre-p, the main data signal Main-p and the post-marked data signal Pos-p; the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1, and is connected to the port of the output signal Txp; the source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to the port of the bias voltage A;
[0008] The gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2 to receive an input signal Vin-n, where the input signal Vin-n is any one of the pre-marked data signal Pre-n, the main data signal Main-n, and the post-marked data signal Pos-n; the drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2, and is connected to the port of the output signal Txn;
[0009] The gate of the PMOS tube P4 receives the input signal Vin-p; the drain of the PMOS tube P4 is connected to the port of the output signal Txp; the source of the PMOS tube P4 is connected to the power supply voltage terminal VDD2 through the bias current source I1;
[0010] The gate of the PMOS tube P5 receives the input signal Vin-n; the drain of the PMOS tube P5 is connected to the port of the output signal Txn; the source of the PMOS tube P5 is connected to the power supply voltage terminal VDD2 through the bias current source I1.
[0011] In combination with the first aspect, in certain implementations of the first aspect, the circuit further includes a PMOS tube P3 and a resistor R1; the source of the PMOS tube P3 is connected to the power supply voltage VDD1, and the first end of the resistor R1 is connected to the power supply voltage VDD1; the second end of the resistor R1 is connected to the drain of the PMOS tube P3 to form a port of the bias voltage A.
[0012] In combination with the first aspect, in certain implementations of the first aspect, the circuit further includes an NMOS tube N3 and a resistor R2; the source of the NMOS tube N3 is grounded, and the first end of the resistor R2 is grounded; the second end of the resistor R2 is connected to the drain of the NMOS tube N3 to form a port of the bias voltage B.
[0013] In combination with the first aspect, in some implementations of the first aspect, the input signal Vin-p first passes through the inverter INV1 and then is input to the gate of the NMOS transistor N1 and the gate of the PMOS transistor P1;
[0014] The input signal Vin-n first passes through the inverter INV2 and then is input to the gate of the NMOS tube N2 and the gate of the PMOS tube P2.
[0015] The input signal Vin-p first passes through the inverter INV3 and then is input to the gate of the PMOS tube P4;
[0016] The input signal Vin-n first passes through the inverter INV4 and is then input to the gate of the PMOS tube P5.
[0017] In combination with the first aspect, in some implementations of the first aspect, when Vin-p is at a high level and Vin-n is at a low level, INV1 outputs a low level, INV2 outputs a high level, the NMOS tube N2 and the PMOS tube P1 are turned on, the NMOS tube N1 and the PMOS tube P2 are turned off, Txp is at a high level, and Txn is at a low level; INV3 outputs a low level, INV4 outputs a high level, the PMOS tube P4 is turned on, the PMOS tube P5 is turned off, the current source I1 is output through the PMOS tube P4, and a voltage is superimposed on Txp;
[0018] When Vin-p is low and Vin-n is high, INV1 outputs high, INV2 outputs low, NMOS tube N2 and PMOS tube P1 are turned off, NMOS tube N1 and PMOS tube P2 are turned on, Txp is low, and Txn is high; INV3 outputs high, INV4 outputs low, PMOS tube P4 is turned off, PMOS tube P5 is turned on, and current source I1 is output through PMOS tube P5, and voltage is superimposed on Txn.
[0019] In combination with the first aspect, in some implementations of the first aspect, the NMOS transistor N3 and the PMOS transistor P3 are used as switches, and the NMOS transistor N3 and the PMOS transistor P3 are biased in a linear region.
[0020] In combination with the first aspect, in some implementations of the first aspect, the PMOS transistor P4 and the PMOS transistor P5 are used as current sources, and the PMOS transistor P4 and the PMOS transistor P5 are biased in a saturation region.
[0021] In combination with the first aspect, in some implementations of the first aspect, Vin-p and Vin-n are a pair of differential input data signals, and the values of Vin-p and Vin-n are both between the power supply voltage VDD1 and the ground.
[0022] In a second aspect, a driver module is provided, the driver module comprising a plurality of driver units, each driver unit comprising a hybrid mode driver circuit as described in any one of the implementations in the first aspect above, at least one driver unit in the driver module processes a main data signal, and at least one driver unit in the driver module processes a front-label data signal or a rear-label data signal.
[0023] In a third aspect, a high-speed SerDes transmitter circuit structure is provided, wherein the transmitter circuit structure includes a parallel-to-serial conversion module, a delay module, a driver module, and a decoder module;
[0024] The parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the received multi-bit parallel differential input data signal data_in, convert it into a serial signal and output the pre-mark data signals Pre-p and Pre-n to the delay module and the driver module;
[0025] The delay module is used to delay the output of the pre-marked data signals Pre-p and Pre-n from the parallel-to-serial conversion module, generate the main data signals Main-p and Main-n by delaying 1T and output them to the driver module, and generate the post-marked data signals Pos-p and Pos-n by delaying 2T and output them to the driver module;
[0026] The decoder module is used to output an on control signal and a pre-emphasis control signal according to an external input control signal, so as to control the on number and tap coefficient of multiple driver units in the driver module;
[0027] The driver module is a driver module as described in any one of the implementation methods in the second aspect above, and the driver module is used to receive the pre-mark data signals Pre-p and Pre-n from the parallel-to-serial conversion module, and the main data signals Main-p, Main-n and the post-mark data signals Pos-p and Pos-n from the delay module, and control the data signal input to the driver unit according to the pre-emphasis enable signal output by the decoder module, so that the turned-on driver unit processes one of the pre-mark data signal, the main data signal, and the post-mark data signal, thereby completing the pre-emphasis processing of the main data signal, and finally outputting a pair of differential data signals Txp and Txn as transmitter output.
[0028] Compared with the prior art, the solution provided by this application includes at least the following beneficial technical effects:
[0029] (1) The present invention adopts a hybrid mode structure, which can reduce the overall power consumption of the circuit while ensuring the balancing effect;
[0030] (2) The present invention uses a current mode driver structure, and the output swing of the driver can be adjusted by controlling whether it is turned on;
[0031] (3) The present invention has strong portability and is applicable to various interconnection protocols and general CMOS process circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 The structure block diagram of the transmitter circuit is shown in Figure 2.
[0033] Figure 2This is a schematic diagram of the connections between the driver units inside the driver module.
[0034] Figure 3 The circuit diagram of a single mixed-mode driver unit consisting of voltage mode and current mode. DETAILED DESCRIPTION
[0035] The present application is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0036] Figure 1 The present invention is a schematic diagram of a high-speed SerDes transmitter circuit structure, which includes a parallel-to-serial conversion module, a delay module, a driver module and a decoder module.
[0037] The parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the received multi-bit parallel differential input data signal data_in, convert it into a serial signal and output the pre-mark data signals Pre-p and Pre-n to the delay module and the driver module.
[0038] The delay module is used to delay the output of the pre-mark data signals Pre-p and Pre-n from the parallel-to-serial conversion module, generate the main data signals Main-p and Main-n by delaying 1T and output them to the driver module, and generate the post-mark data signals Pos-p and Pos-n by delaying 2T and output them to the driver module.
[0039] The decoder module is used to output an on control signal and a pre-emphasis control signal according to an external input control signal, so as to control the on number and tap coefficient of multiple driver units in the driver module.
[0040] The driver module receives the pre-marked data signals Pre-p and Pre-n from the parallel-to-serial conversion module, and the main data signals Main-p and Main-n and the post-marked data signals Pos-p and Pos-n from the delay module, and controls the data signal input to the driver unit according to the pre-emphasis enable signal output by the decoder module, so that the enabled driver unit processes one of the pre-marked data signal, the main data signal, and the post-marked data signal (at least one driver unit in the driver module processes the pre-marked data signal or the post-marked data signal), thereby completing the pre-emphasis processing of the main data Main-p and Main-n, and finally outputting a pair of differential data signals Txp and Txn as the transmitter output, and the differential output terminals Txn and Txp are respectively connected to the two ends of the load module to form a current loop. The number of enabled driver units in the driver module can be controlled according to the enable control signal output by the decoder module.
[0041] Figure 2 A schematic structural diagram of a driver module is shown. Figure 2The driver module shown includes a 3tap pre-emphasis circuit. The 3tap pre-emphasis circuit includes a driver unit a, a driver unit b, and a driver unit c. When each driver unit in the 3tap pre-emphasis circuit is in the on state, the pre-marked data signals Pre-p and Pre-n are input to the driver unit a, the main data signals Main-p and Main-n are input to the driver unit b, and the post-marked data signals Pos-p and Pos-n are input to the driver unit c. The signal processed by the driver unit is pre-emphasized by superposition at the output end. The p signal output by each driver unit is superimposed to form a data signal Txp, and the n signal output by each driver unit is superimposed to form a data signal Txn. The data signals Txp and Txn are input to the load module, so the final output voltage Vout = Txp-Txn.
[0042] The actual circuit driver may contain many 3tap pre-emphasis circuits. Figure 2 Only two are drawn and their connection method is illustrated. In addition, the number of enabled pre-mark data signals, main data signals and post-mark signals is not necessarily the same. Multiple driver units may not be pre-emphasized in the form of a 3tap pre-emphasis circuit. The pre-emphasis enable signal output by the decoder module can control whether each driver unit is turned on. Assume that the pre-emphasis enable signal indicates that n0 driver units are used to receive main data signals Main-p and Main-n, n1 driver units are used to receive pre-mark data signals Pre-p and Pre-n, and n2 driver units are used to receive post-mark data signals Pos-p and Pos-n. Then n0+n1+n2 driver units are connected in parallel to form a pre-emphasis circuit to complete the pre-emphasis processing of the main data Main-p and Main-n, and finally output a pair of differential data signals Txp and Txn as transmitter output. Usually, the number of enabled main data signals will be much greater than the number of pre-mark data signals and post-mark signals.
[0043] Figure 3 A schematic diagram of a hybrid mode driver circuit is shown. The hybrid mode driver circuit can be applied to Figure 2 The drive unit shown.
[0044] The circuit includes an NMOS tube N1, an NMOS tube N2, a PMOS tube P1, a PMOS tube P2, a PMOS tube P4, a PMOS tube P5 and a bias current source I1.
[0045] In order to make the input data signal and the output data signal in phase, the input signal Vin-p (the input signal Vin-p is any one of the pre-marked data signal Pre-p, the main data signal Main-p and the post-marked data signal Pos-p) first passes through the inverter INV1. The gate of the NMOS tube N1 is connected to the gate of the PMOS tube P1, and is connected to the output end of the inverter INV1 to receive the input signal Vin-p. The drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1, and is connected to the port of the output signal Txp. The source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to the port of the bias voltage A. The bias voltage A is the high level limit V OH . V OH close to the value of the power supply voltage.
[0046] In order to make the input data signal and the output data signal in phase, the input signal Vin-n (the input signal Vin-n is any one of the pre-marked data signal Pre-n, the main data signal Main-n and the post-marked data signal Pos-n) first passes through the inverter INV2. The gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2, and is connected to the output end of the inverter INV2 to receive the input signal Vin-n. The drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2, and is connected to the port of the output signal Txn. The source of the NMOS tube N1 and the source of the NMOS tube N2 are connected to the port of the bias voltage B. The bias voltage B is the low level limit V OL . V OL Close to ground value.
[0047] exist Figure 3 In the illustrated embodiment, the circuit may further include a PMOS tube P3 and a resistor R1. The bias voltage A may be provided by the PMOS tube P3 and the resistor R1. The source of the PMOS tube P3 is connected to the power supply voltage VDD1, and the first end of the resistor R1 is connected to the power supply voltage VDD1. The second end of the resistor R1 is connected to the drain of the PMOS tube P3 to form a port for the bias voltage A. The port for the bias voltage A is connected to both the source of the PMOS tube P1 and the source of the PMOS tube P2, and the PMOS tube P3 and the resistor R1 provide the bias voltage A for the driver.
[0048] exist Figure 3 In the illustrated embodiment, the circuit may further include an NMOS tube N3 and a resistor R2. The bias voltage B may be provided by the NMOS tube N3 and the resistor R2. The source of the NMOS tube N3 is grounded, and the first end of the resistor R2 is grounded. The second end of the resistor R2 is connected to the drain of the NMOS tube N3 to form a port for the bias voltage B, and the port for the bias voltage B is connected to the source of the NMOS tube N1 and the source of the NMOS tube N2. The NMOS tube N3 and the resistor R2 provide the bias voltage B for the driver.
[0049] The gate of the PMOS tube P4 receives the input signal Vin-p. The drain of the PMOS tube P4 is connected to the port of the output signal Txp. The source of the PMOS tube P4 is connected to the power supply voltage terminal VDD2 through the bias current source I1. In order to make the input data signal and the output data signal in phase, the front end of the gate of the PMOS tube P4 is connected to the inverter INV3.
[0050] The gate of the PMOS tube P5 receives the input signal Vin-n. The drain of the PMOS tube P5 is connected to the port of the output signal Txn. The source of the PMOS tube P5 is connected to the power supply voltage terminal VDD2 through the bias current source I1. In order to make the input data signal and the output data signal in phase, the front end of the gate of the PMOS tube P5 is connected to the inverter INV4.
[0051] The working principle of the circuit is explained below.
[0052] Vin-p and Vin-n are a pair of differential input data signals, whose values are between the power supply voltage VDD1 and the ground. When their values are close to the power supply voltage VDD1, they are called high-level inputs, and when their values are close to 0V, they are called low-level inputs. When the data signals are input normally, Vin-p and Vin-n cannot be both high or both low.
[0053] for Figure 3 In the circuit shown, according to the MOS tube principle and the characteristics of Vin-p and Vin-n, only one of the PMOS tube P1 and PMOS tube P2 can be turned on at the same time, and only one of the NMOS tube N1 and NMOS tube N2 can be turned on at the same time.
[0054] When Vin-p is high and Vin-n is low, INV1 outputs low and INV2 outputs high, then NMOS tube N2 and PMOS tube P1 are turned on, NMOS tube N1 and PMOS tube P2 are turned off, Txp is high and Txn is low, which is equivalent to a positive value for the load module voltage Vout=Txp-Txn.
[0055] When Vin-p is low and Vin-n is high, INV1 outputs high and INV2 outputs low, then NMOS tube N2 and PMOS tube P1 are turned off, NMOS tube N1 and PMOS tube P2 are turned on, Txp is low and Txn is high, which is equivalent to a negative value for the load module voltage Vout=Txp-Txn.
[0056] NMOS tube N3 and PMOS tube P3 are used as switches. At this time, the MOS tube is biased in the linear region, and its linear on-resistance, that is, output resistance, is very small, and can be regarded as a conductor. The drain current in the linear region is small, so the power consumption is usually low.
[0057] Thus, the input main data signal or the pre-marker and post-marker signals can be transmitted to the subsequent stage, and then the pre-emphasis operation is performed. That is, a single driver unit is used to drive the main data and pre-emphasize the main data, and the output differential data signal is sent to the load module after the current of multiple driver units is superimposed.
[0058] PMOS tube P4, PMOS tube P5 and bias current source I1 are used to adjust the output swing. Bias current source I1 provides a suitable and stable bias current, and the final output voltage Vout = Txp-Txn = load resistance * I1. The load resistance is, for example, two 50Ω in series, so the appropriate value of bias current source I1 can be obtained by the output voltage requirement. For example, if the output voltage Vout is required to be 800mV, then I1 = 8mA. VDD2 is, for example, 1.8V.
[0059] When the high and low levels of the input signals Vin-p and Vin-n change, and the swing adjustment is enabled, the outputs of the PMOS tubes P4 and P5 will superimpose a voltage signal on the ports of the output signals Txp and Txn, so that the swing of the output signals Txp and Txn is adjusted. The PMOS tubes P4 and P5 are biased in the saturation region and used as current sources. Even if the source and drain voltages of the MOS tubes change, their drain currents remain almost unchanged, that is, their output resistance is approximately infinite. The drain current in the saturation region is large, so the power consumption of the current mode driver is high. Since the output swing is proportional to the load current, the current mode driver has a large output swing.
[0060] Specifically, when the swing adjustment is enabled, only one of the PMOS transistor P4 and the PMOS transistor P5 can be turned on at the same time.
[0061] When Vin-p is high and Vin-n is low, INV3 outputs low and INV4 outputs high, then PMOS tube P4 is turned on and PMOS tube P5 is turned off, and current source I1 flows into the load module through PMOS tube P4, which is equivalent to superimposing a small voltage on the basis of Txp, while the value of Txn remains unchanged, which ultimately increases the absolute value of the load voltage Vout, that is, the positive value is more positive.
[0062] When Vin-p is low and Vin-n is high, INV3 outputs high and INV4 outputs low, then PMOS tube P4 is turned off and PMOS tube P5 is turned on, and current source I1 flows into the load module through PMOS tube P5, which is equivalent to superimposing a small voltage on the basis of Txn, while the value of Txp remains unchanged, which ultimately increases the absolute value of the load voltage Vout, that is, the negative value becomes more negative.
[0063] In this way, the input data signal can be converted into a swing adjustment voltage, and its absolute value can be increased when the load voltage is positive or negative. According to "driver output swing = (maximum value when the load voltage is positive) - (minimum value when the load voltage is negative)", which is equivalent to the sum of the absolute values of the two, it can be known that the current mode driver can increase the output swing. For example, when the load voltage is positive, the maximum is 0.5V, and when it is negative, the minimum is -0.5V, then the driver output swing is 0.5V-(-0.5V) = 1V.
[0064] The existing voltage mode driver power supply VDD1=0.9V, and the output swing is about 800mV. The present invention can increase the differential output swing to more than 1V without changing the power supply voltage VDD1. In other words, a higher and adjustable output swing can be achieved under the premise of low power consumption.
[0065] The purpose of the present invention is to provide a hybrid mode driver circuit suitable for high-speed SerDes, which can realize low power consumption and transmit data signals with high swing amplitude. The structure has the advantages of low power consumption and strong equalization capability, and can realize driving the main data and pre-emphasis, as well as adjusting the output swing amplitude. Usually, the tap coefficient of the main data is large, so while meeting the equalization function, the power consumption of the entire circuit can be significantly reduced, which meets the design requirements and can be used in the design of the transmitter driver in the high-speed interface circuit.
[0066] Although the present invention is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.
Claims
1. A hybrid mode driver circuit suitable for high-speed SerDes, characterized in that: include: NMOS tube N1, NMOS tube N2, PMOS tube P1, PMOS tube P2, PMOS tube P4, PMOS tube P5 and bias current source I1; The gate of the NMOS tube N1 is connected to the gate of the PMOS tube P1 to receive the input signal Vin-p, and the input signal Vin-p is any one of the pre-marked data signal Pre-p, the main data signal Main-p and the post-marked data signal Pos-p; the drain of the NMOS tube N1 is connected to the drain of the PMOS tube P1, and is connected to the port of the output signal Txp; the source of the PMOS tube P1 and the source of the PMOS tube P2 are connected to the port of the bias voltage A; The gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2 to receive an input signal Vin-n, where the input signal Vin-n is any one of the pre-marked data signal Pre-n, the main data signal Main-n, and the post-marked data signal Pos-n; the drain of the NMOS tube N2 is connected to the drain of the PMOS tube P2, and is connected to the port of the output signal Txn; The gate of the PMOS tube P4 receives the input signal Vin-p; the drain of the PMOS tube P4 is connected to the port of the output signal Txp; the source of the PMOS tube P4 is connected to the power supply voltage terminal VDD2 through the bias current source I1; The gate of the PMOS tube P5 receives the input signal Vin-n; the drain of the PMOS tube P5 is connected to the port of the output signal Txn; the source of the PMOS tube P5 is connected to the power supply voltage terminal VDD2 through the bias current source I1.
2. The hybrid mode driver circuit according to claim 1, characterized in that: The circuit also includes a PMOS tube P3 and a resistor R1; the source of the PMOS tube P3 is connected to the power supply voltage VDD1, and the first end of the resistor R1 is connected to the power supply voltage VDD1; the second end of the resistor R1 is connected to the drain of the PMOS tube P3 to form a port of the bias voltage A.
3. The hybrid mode driver circuit according to claim 1, characterized in that: The circuit also includes an NMOS tube N3 and a resistor R2; the source of the NMOS tube N3 is grounded, and the first end of the resistor R2 is grounded; the second end of the resistor R2 is connected to the drain of the NMOS tube N3 to form a port of the bias voltage B.
4. The mixed mode driver circuit according to claim 1, characterized in that: The input signal Vin-p first passes through the inverter INV1 and then is input to the gate of the NMOS tube N1 and the gate of the PMOS tube P1; The input signal Vin-n first passes through the inverter INV2 and then is input to the gate of the NMOS tube N2 and the gate of the PMOS tube P2. The input signal Vin-p first passes through the inverter INV3 and then is input to the gate of the PMOS tube P4; The input signal Vin-n first passes through the inverter INV4 and is then input to the gate of the PMOS tube P5.
5. The hybrid mode driver circuit according to claim 4, characterized in that: When Vin-p is high and Vin-n is low, INV1 outputs low, INV2 outputs high, NMOS tube N2 and PMOS tube P1 are turned on, NMOS tube N1 and PMOS tube P2 are turned off, Txp is high, and Txn is low; INV3 outputs low, INV4 outputs high, PMOS tube P4 is turned on, PMOS tube P5 is turned off, and current source I1 is output through PMOS tube P4, and voltage is superimposed on Txp; When Vin-p is low and Vin-n is high, INV1 outputs high, INV2 outputs low, NMOS tube N2 and PMOS tube P1 are turned off, NMOS tube N1 and PMOS tube P2 are turned on, Txp is low, and Txn is high; INV3 outputs high, INV4 outputs low, PMOS tube P4 is turned off, PMOS tube P5 is turned on, and current source I1 is output through PMOS tube P5, and voltage is superimposed on Txn.
6. The mixed mode driver circuit according to claim 1, characterized in that: The NMOS tube N3 and the PMOS tube P3 are used as switches, and the NMOS tube N3 and the PMOS tube P3 are biased in a linear region.
7. The mixed mode driver circuit according to claim 1, characterized in that: The PMOS tube P4 and the PMOS tube P5 are used as current sources, and the PMOS tube P4 and the PMOS tube P5 are biased in a saturation region.
8. The mixed mode driver circuit according to claim 1, characterized in that: Vin-p and Vin-n are a pair of differential input data signals, and the values of Vin-p and Vin-n are both between the power supply voltage VDD1 and the ground.
9. A driver module, characterized in that: The driver module includes multiple driver units, each driver unit includes a hybrid mode driver circuit as described in any one of claims 1 to 8, at least one driver unit in the driver module processes the main data signal, and at least one driver unit in the driver module processes the front-label data signal or the rear-label data signal.
10. A high-speed SerDes transmitter circuit structure, characterized in that: The transmitter circuit structure includes a parallel-to-serial conversion module, a delay module, a driver module and a decoder module; The parallel-to-serial conversion module is used to perform parallel-to-serial conversion on the received multi-bit parallel differential input data signal data_in, convert it into a serial signal and output the pre-mark data signals Pre-p and Pre-n to the delay module and the driver module; The delay module is used to delay the output of the pre-marked data signals Pre-p and Pre-n from the parallel-to-serial conversion module, generate the main data signals Main-p and Main-n by delaying 1T and output them to the driver module, and generate the post-marked data signals Pos-p and Pos-n by delaying 2T and output them to the driver module; The decoder module is used to output an on control signal and a pre-emphasis control signal according to an external input control signal, so as to control the on number and tap coefficient of multiple driver units in the driver module; The driver module is the driver module as claimed in claim 9, and the driver module is used to receive the pre-mark data signals Pre-p and Pre-n from the parallel-to-serial conversion module, and the main data signals Main-p, Main-n and the post-mark data signals Pos-p and Pos-n from the delay module, and control the data signal input to the driver unit according to the pre-emphasis enable signal output by the decoder module, so that the turned-on driver unit processes one of the pre-mark data signal, the main data signal, and the post-mark data signal, thereby completing the pre-emphasis processing of the main data signal, and finally outputting a pair of differential data signals Txp and Txn as transmitter output.