Fast decoding method and device suitable for integrated CV-QKD
By reducing the number of residual error elimination modules in the CV-QKD system and adopting a pipelined hardware architecture, the problem of FPGA hardware resource limitation is solved, and the overall decoding throughput and key generation rate of the CV-QKD system is improved.
Patent Information
- Application Number
- CN202411323109.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-23
- Publication Date
- 2024-12-31
AI Technical Summary
In CV-QKD systems, the FPGA hardware resources are limited, resulting in the cascading structure of multiple decoders and multiple residual error elimination modules limiting the number of decoders that can be realized, and thus limiting the overall decoding throughput.
By reducing the number of residual error elimination modules, using a pipelined hardware architecture design, calculate the running time of the decoder and residual error elimination modules, determine the maximum number of decoders that can be supported, so as to save hardware resources and improve overall translation Code throughput.
It effectively increases the number of achievable decoders, improves the overall decoding throughput, and achieves more efficient key generation rate and secure code rate.
Smart Images
Figure CN119232177A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of continuous variable quantum key distribution (CV-QKD), and in particular to a fast decoding method and device suitable for integrated CV-QKD. Background Art
[0002] With the development of quantum physics and quantum information theory, quantum cryptography based on the principles of quantum mechanics has been proven to have unconditional security in the sense of information theory. Among them, the most representative technology is quantum key distribution (QKD). QKD mainly includes two major technical approaches: discrete variables and continuous variables. Among them, continuous variable quantum key distribution (CV-QKD) uses the orthogonal components of the quantum light field as the information carrier, has the advantages of high security code rate within medium and short transmission distances, and is compatible with the traditional optical communication industry chain. It is an important development direction of QKD technology.
[0003] The CV-QKD system includes the preparation, transmission, detection of quantum states, and post-processing of classical data. The overall block diagram is as follows: Figure 1 The data post-processing process significantly affects the overall security of the system and the key generation rate. After the data post-processing on the classical channel, Alice and Bob obtain a set of completely consistent security keys. The data post-processing flow chart is shown in Figure 2 As shown, conducting research on integrated post-processing technology is the key to promoting the practical application of CV-QKD systems, among which achieving integrated high-speed and efficient error correction is the difficulty and key point of realizing integrated post-processing.
[0004] The error correction of CV-QKD post-processing can be accelerated by devices with parallel computing capabilities. Compared with GPU, FPGA is small in size, low in power consumption, and cheaper, making it more suitable for the integrated design and implementation of CV-QKD post-processing. However, the hardware resources on the FPGA chip are limited. In order to achieve fast decoding, the decoder can only be designed based on fixed-point numbers with limited precision, resulting in residual errors after decoding and a high frame error rate, which greatly affects the system security bit rate. Cascading a residual error elimination module after the decoder is an effective way to reduce the frame error rate and improve the security bit rate of the CV-QKD system. In addition, in order to make full use of hardware resources to maximize the decoding rate, the existing decoding device adopts a structure in which multiple decoders and multiple residual error elimination modules are in parallel. However, the implementation of a residual error elimination module requires a large amount of hardware resources. In a decoding device in which multiple decoders and multiple residual error elimination modules are cascaded, the hardware resources consumed by the residual error elimination module limit the number of achievable decoders to a certain extent, thereby limiting the overall decoding throughput. Summary of the invention
[0005] In the integrated CV-QKD post-processing error correction device, the current decoding scheme of cascading multiple decoders and multiple residual error elimination modules consumes a lot of hardware resources because the residual error elimination module consumes a lot of hardware resources, resulting in a reduction in the number of decoders that can be implemented under limited hardware resources, limiting its overall decoding throughput. Based on the characteristic that the running time of the residual error elimination step is much less than the running time of the decoding process, the present invention provides a fast decoding method and device suitable for integrated CV-QKD, which reduces the number of residual error elimination modules to save a lot of hardware resources, thereby effectively increasing the number of achievable decoders and achieving the purpose of improving the overall decoding throughput.
[0006] The present invention provides a fast decoding method suitable for integrated CV-QKD, the method comprising:
[0007] Using k decoders and a residual error elimination module for decoding;
[0008] The maximum value of k is calculated based on the decoder running time and the residual error elimination module running time.
[0009] Furthermore, a pipelined hardware architecture is designed between the decoder and the residual error elimination module.
[0010] Furthermore, the method for calculating k is:
[0011] During the operation of the decoder, the counter cnt_time1 is used to record its operation time. When the decoder starts working, cnt_time1 starts counting from 0, and the value of cnt_time1 increases by 1 in each clock cycle. After the decoding is completed, the value of cnt_time1 can represent the operation time of the decoder.
[0012] During the operation of the residual error elimination module, the counter cnt_time2 is used to record its operation time. When the data in the decoding result storage unit is stored, the residual error elimination module starts to run, and cnt_time2 starts counting from 0. The value of cnt_time2 is increased by 1 in each clock cycle. After the residual error elimination module is finished running, the value of cnt_time2 can represent the running time of the residual error elimination module.
[0013] According to the values of counters cnt_time1 and cnt_time2, the maximum number of decoders that a residual error elimination module can support under the pipeline hardware architecture is obtained, that is, the maximum value of k is cnt_time1cnt_time2 rounded down.
[0014] Furthermore, the actual value of k needs to be determined based on the hardware resources consumed by a decoder and a residual error elimination module, combined with the total amount of FPGA hardware resources used.
[0015] Furthermore, the consumed hardware resources include BRAM and LUT hardware resources.
[0016] The present invention also provides a fast decoding device suitable for integrated CV-QKD, comprising:
[0017] k decoders;
[0018] and a residual error elimination module connected to the k decoders for decoding;
[0019] The maximum value of k is calculated based on the decoder running time and the residual error elimination module running time.
[0020] Furthermore, a pipelined hardware architecture is designed between the decoder and the residual error elimination module.
[0021] Furthermore, the method for calculating k is:
[0022] During the operation of the decoder, the counter cnt_time1 is used to record its operation time. When the decoder starts working, cnt_time1 starts counting from 0, and the value of cnt_time1 increases by 1 in each clock cycle. After the decoding is completed, the value of cnt_time1 can represent the operation time of the decoder.
[0023] During the operation of the residual error elimination module, the counter cnt_time2 is used to record its operation time. When the data in the decoding result storage unit is stored, the residual error elimination module starts to run, and cnt_time2 starts counting from 0. The value of cnt_time2 is increased by 1 in each clock cycle. After the residual error elimination module is finished running, the value of cnt_time2 can represent the running time of the residual error elimination module.
[0024] According to the values of counters cnt_time1 and cnt_time2, the maximum number of decoders that a residual error elimination module can support under the pipeline hardware architecture is obtained, that is, the maximum value of k is cnt_time1cnt_time2 rounded down.
[0025] Furthermore, the actual value of k needs to be determined based on the hardware resources consumed by a decoder and a residual error elimination module, combined with the total amount of FPGA hardware resources used.
[0026] Furthermore, the consumed hardware resources include BRAM and LUT hardware resources.
[0027] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:
[0028] Based on the characteristic that the running time of the residual error elimination step is much less than the running time of the decoding process, the present invention reduces the number of residual error elimination modules to save a large amount of hardware resources, thereby effectively increasing the number of achievable decoders, thereby achieving the purpose of improving the overall decoding throughput. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is the flow chart of the CV-QKD system.
[0030] Figure 2 This is the data post-processing flow chart of the CV-QKD system.
[0031] Figure 3 A structural diagram of a fast decoding device suitable for integrated CV-QKD provided in an embodiment of the present invention.
[0032] Figure 4 The hardware architecture diagram of the decoder.
[0033] Figure 5 This is the hardware architecture diagram of the residual error elimination module. DETAILED DESCRIPTION
[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0035] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0036] Example
[0037] Based on the fact that the running time of the residual error elimination step is much shorter than the running time of the decoding process, this embodiment provides a fast decoding method and device suitable for integrated CV-QKD, such as Figure 3 As shown, one residual error elimination module supports k decoders, and a large amount of hardware resources are saved by reducing the number of residual error elimination modules, thereby effectively increasing the number of achievable decoders, thereby achieving the purpose of improving the overall decoding throughput.
[0038] In the integrated post-processing error correction device of the CV-QKD system (such as FPGA, etc.), a multilateral type MET-LDPC code is usually used for error correction. Its decoding algorithm is a layered logarithmic domain belief propagation decoding algorithm. Compared with the traditional belief propagation decoding algorithm, the layered logarithmic domain belief propagation decoding algorithm not only reduces the computational complexity in the iterative decoding process, but also can achieve a decoding efficiency similar to that of the traditional belief propagation decoding algorithm with fewer iterations. The hardware architecture diagram of the decoder implemented based on the layered logarithmic domain belief propagation decoding algorithm is shown in the figure below. Figure 4 During the operation of the decoder, the counter cnt_time1 can be used to record its operation time. When the decoder starts working, cnt_time1 starts counting from 0, and the value of cnt_time1 increases by 1 in each clock cycle. After the decoding is completed, the value of cnt_time1 can represent the operation time of the decoder.
[0039] Assume that the code length of a MET-LDPC code is N, its variable node set N = {0, 1, ..., N-1}, and the check matrix H = {h i ,i∈N}, the check matrix H corresponding to the subset s of variable nodes s ={h i,i∈s}. The data decoded by the decoder is subjected to residual error elimination by the residual error elimination module. The hardware architecture diagram of the residual error elimination module is shown in Figure 5 As shown. During the operation of the residual error elimination module, the counter cnt_time2 is used to record its operation time. When the data in the decoding result storage unit is stored, the residual error elimination module starts to run, and cnt_time2 starts counting from 0. The value of cnt_time2 is increased by 1 in each clock cycle. After the residual error elimination module is finished running, the value of cnt_time2 can represent the operation time of the residual error elimination module.
[0040] Since the residual error elimination module processes the output of the decoder, a pipelined hardware architecture can be designed between the decoder and the residual error elimination module to improve the decoding throughput. According to the values of the counters cnt_time1 and cnt_time2, it can be obtained that under the pipelined hardware architecture, the maximum number of decoders that can be supported by a residual error elimination module in the decoding scheme proposed by the present invention is cnt_time1×cnt_time2 rounded down.
[0041] Based on the hardware resources consumed to implement a decoder and a residual error elimination module, combined with the total amount of FPGA hardware resources used, the maximum number of decoders that can be implemented on a single FPGA can be obtained.
[0042] For example, for a MET-LDPC code with a code rate of 0.2 and a code length of 80,000, using a common specification FPGA to implement a decoder consumes 20% of BRAM (Block Random Access Memory) and 5.8% of LUT (Look Up Table) hardware resources, and implementing the residual error elimination module consumes 8.7% of BRAM and 28% of LUT. The test shows that the ratio of the decoder's running time cnt_time1 to the residual error elimination module's running time cnt_time2 satisfies In the existing decoding scheme of one decoder cascaded with one residual error elimination module, due to the limitation of LUT hardware resources, only two decoders and two residual error elimination modules can be implemented on a single FPGA. However, the decoding scheme of multiple decoders cascaded with one residual error elimination module proposed by the present invention can realize three decoders and one residual error elimination module, and the decoding throughput is improved by 50% compared with the existing decoding scheme.
[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A fast decoding method suitable for integrated CV-QKD, characterized in that: The method is: Using k decoders and a residual error elimination module for decoding; The maximum value of k is calculated based on the decoder running time and the residual error elimination module running time.
2. The fast decoding method suitable for integrated CV-QKD according to claim 1, characterized in that: The decoder and the residual error elimination module are designed to form a pipeline hardware architecture.
3. The fast decoding method suitable for integrated CV-QKD according to claim 2, characterized in that: The method to calculate k is: During the operation of the decoder, the counter cnt_time1 is used to record its operation time. When the decoder starts working, cnt_time1 starts counting from 0, and the value of cnt_time1 increases by 1 in each clock cycle. After the decoding is completed, the value of cnt_time1 can represent the operation time of the decoder. During the operation of the residual error elimination module, the counter cnt_time2 is used to record its operation time. When the data in the decoding result storage unit is stored, the residual error elimination module starts to run, and cnt_time2 starts counting from 0. The value of cnt_time2 is increased by 1 in each clock cycle. After the residual error elimination module is finished running, the value of cnt_time2 can represent the running time of the residual error elimination module. According to the values of counters cnt_time1 and cnt_time2, the maximum number of decoders that a residual error elimination module can support under the pipeline hardware architecture is obtained, that is, the maximum value of k is cnt_time1cnt_time2 rounded down.
4. The fast decoding method suitable for integrated CV-QKD according to any one of claims 1 to 3, characterized in that: The actual value of k also needs to be determined based on the hardware resources consumed by a decoder and a residual error elimination module, combined with the total amount of FPGA hardware resources used.
5. The fast decoding method suitable for integrated CV-QKD according to claim 4, characterized in that: The consumed hardware resources include BRAM and LUT hardware resources.
6. A fast decoding device suitable for integrated CV-QKD, characterized in that: include: k decoders; and a residual error elimination module connected to the k decoders for decoding; The maximum value of k is calculated based on the decoder running time and the residual error elimination module running time.
7. The fast decoding device suitable for integrated CV-QKD according to claim 6, characterized in that: The decoder and the residual error elimination module are designed to form a pipeline hardware architecture.
8. The fast decoding device suitable for integrated CV-QKD according to claim 7, characterized in that: The method to calculate k is: During the operation of the decoder, the counter cnt_time1 is used to record its operation time. When the decoder starts working, cnt_time1 starts counting from 0, and the value of cnt_time1 increases by 1 in each clock cycle. After the decoding is completed, the value of cnt_time1 can represent the operation time of the decoder. During the operation of the residual error elimination module, the counter cnt_time2 is used to record its operation time. When the data in the decoding result storage unit is stored, the residual error elimination module starts to run, and cnt_time2 starts counting from 0. The value of cnt_time2 is increased by 1 in each clock cycle. After the residual error elimination module is finished running, the value of cnt_time2 can represent the running time of the residual error elimination module. According to the values of counters cnt_time1 and cnt_time2, the maximum number of decoders that a residual error elimination module can support under the pipeline hardware architecture is obtained, that is, the maximum value of k is cnt_time1cnt_time2 rounded down.
9. The fast decoding device suitable for integrated CV-QKD according to any one of claims 6 to 8, characterized in that: The actual value of k also needs to be determined based on the hardware resources consumed by a decoder and a residual error elimination module, combined with the total amount of FPGA hardware resources used.
10. The fast decoding device suitable for integrated CV-QKD according to claim 9, characterized in that: The consumed hardware resources include BRAM and LUT hardware resources.