Switching circuit for converting RGMII interface into GMII interface

Abstract

The invention provides a conversion circuit for converting an RGMII interface into a GMII interface, the conversion circuit comprises the RGMII interface, the GMII interface and an IDDR module unit, the input end of the IDDR module unit is connected with the RGMII interface, the output end of the IDDR module unit is connected with the GMII interface, the IDDR module unit is used for converting a first data unit into a second data unit, and the second data unit is used for converting the first data unit into the second data unit. The receiving control signal is converted into a receiving data effective signal and a receiving error identification signal; through the structure, the conversion from the RGMII interface to the GMII interface is realized by adopting the IDDR module unit, and compared with an Ethernet phy chip in the prior art, the IDDR module is relatively simple and can be directly integrated into the FPGA, so that the dependence on external hardware is reduced, and the cost is generally low; meanwhile, the IDDR module in the FPGA can be flexibly configured through programming, different design requirements and changes can be met, and the flexibility is high.

Description

Technical Field

[0001] The present application relates to the field of computer communication technology, and in particular to a conversion circuit for converting an RGMII interface to a GMII interface. Background Art

[0002] GMII interface and RGMII interface are two commonly used Ethernet physical layer interfaces. The GMII interface (Gigabit Media Independent Interface) receiving end signal includes receiving clock signal, eight-bit receiving data signal, receiving data valid signal and receiving error identification signal; RGMII interface is a simplified GMII interface, the data line is simplified to four bits, and the receiving end signal includes receiving clock signal, four-bit receiving data signal and receiving control signal.

[0003] In the prior art, an Ethernet PHY chip is usually used to convert data from the RGMII interface to the GMII interface. However, this conversion method requires additional hardware, including chip, power supply and layout design, which will increase the complexity and cost of the overall design. At the same time, the configuration of the PHY chip is usually relatively fixed and has limited flexibility. Summary of the invention

[0004] The purpose of this application is to provide a conversion circuit for converting an RGMII interface to a GMII interface in order to solve the above problems.

[0005] The present application provides a conversion circuit for converting an RGMII interface to a GMII interface, comprising: RGMII interface, the receiving end signal of the RGMII interface includes receiving a first clock signal, a first data unit and a receiving control signal; A GMII interface, wherein a receiving end signal of the GMII interface includes a receiving second clock signal, a second data unit, a receiving data valid signal, and a receiving error identification signal; An IDDR module unit, wherein the input end of the IDDR module unit is connected to the RGMII interface, the output end of the IDDR module unit is connected to the GMII interface, and the IDDR module unit is used to convert the first data unit into a second data unit, and convert the receiving control signal into a receiving data valid signal and a receiving error identification signal.

[0006] According to the technical solution provided by the present application, the first data unit includes: a first RGMII received data signal, a second RGMII received data signal, a third RGMII received data signal and a fourth RGMII received data signal; The second data unit includes: a first GMII receive data signal, a second GMII receive data signal, a third GMII receive data signal, a fourth GMII receive data signal, a fifth GMII receive data signal, a sixth GMII receive data signal, a seventh GMII receive data signal and an eighth GMII receive data signal; The IDDR module unit comprises: a first IDDR module, a second IDDR module, a third IDDR module, a fourth IDDR module, and a fifth IDDR module; the first IDDR module has a first input terminal, a second input terminal, a first output terminal, and a second output terminal; the second IDDR module has a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the third IDDR module has a fifth input terminal, a sixth output terminal, a fourth fifth output terminal, and a sixth output terminal; the fourth IDDR module has a seventh input terminal, an eighth input terminal, a seventh output terminal, and an eighth output terminal; the fifth IDDR module has a ninth input terminal, a fourth input terminal, a ninth output terminal, and a tenth output terminal; Wherein, the second input terminal, the fourth input terminal, the sixth input terminal, the eighth input terminal and the tenth input terminal are all used to input the first clock signal; The first input terminal is used to input a fourth RGMII receive data signal, the third input terminal is used to input a third RGMII receive data signal, the fifth input terminal is used to input a second RGMII receive data signal, the seventh input terminal is used to input a first RGMII receive data signal, and the ninth input terminal is used to input a receive control signal; The first output end is used to output a fourth GMII receive data signal, the second output end is used to output an eighth GMII receive data signal, the third output end is used to output a third GMII receive data signal, the fourth output end is used to output a seventh GMII receive data signal, the fifth output end is used to output a second GMII receive data signal, the sixth output end is used to output a sixth GMII receive data signal, the seventh output end is used to output a first GMII receive data signal, and the eighth output end is used to output a fifth GMII receive data signal; the ninth output end is used to output a receive data valid signal, and the tenth output end and the eleventh output end are also used to output a receive error identification signal.

[0007] According to the technical solution provided in the present application, the RGMII interface is connected to a clock buffer module, the input end of the clock buffer module is used to input the first clock signal, the output end of the clock buffer module is connected to the second input end, the fourth input end, the sixth input end, the eighth output end and the tenth input end, and the output end of the clock buffer module is used to output the system clock.

[0008] According to the technical solution provided by the present application, the RGMII interface is connected to a delay module unit, and the delay module unit is used to make the first data unit and the receiving control signal reach the corresponding IDDR module at the same time, so as to achieve synchronous alignment of the input first data unit and the receiving control signal; the delay module unit includes: a first delay module, a second delay module, a third delay module, a fourth delay module and a fifth delay module; Among them: the input end of the first delay module is used to input the fourth RGMII receive data signal, and the output end of the first delay module is connected to the first input end; the input end of the second delay module is used to input the third RGMII receive data signal, and the output end of the second delay module is connected to the third input end; the input end of the third delay module is used to input the second RGMII receive data signal, and the output end of the third delay module is connected to the fifth input end; the input end of the fourth delay module is used to input the first RGMII receive data signal, and the output end of the fourth delay module is connected to the seventh input end; the input end of the fifth delay module is used to input the receive control signal, and the output end of the fifth delay module is connected to the ninth input end.

[0009] According to the technical solution provided in the present application, a plurality of data cache modules are further provided, and data cache modules are respectively provided between the first IDDR module, the second IDDR module, the third IDDR module, the fourth IDDR module and the GMII interface, and the input ends of the plurality of data cache modules are also connected to the output end of the clock buffer module; the data cache module is used to synchronize the outputted plurality of GMII receiving data signals with the system clock.

[0010] According to the technical solution provided in the present application, the ninth output end is connected to a buffer, the input end of the buffer is also connected to the output end of the clock buffer module, the output end of the buffer is used to output a valid received data signal, and the buffer is used to synchronize the outputted valid received data signal with the system clock.

[0011] According to the technical solution provided in the present application, the ninth output terminal and the tenth output terminal are commonly connected to an XOR device, the input terminal of the XOR device is also connected to the output terminal of the clock buffer module, the output terminal of the XOR device is used to output a reception error identification signal, and the XOR device is used to synchronize the output reception error identification signal with the system clock.

[0012] Compared with the prior art, the present invention has the following advantages: The present application provides a conversion circuit for converting an RGMII interface to a GMII interface, comprising: an RGMII interface, a GMII interface and an IDDR module unit, wherein a receiving end signal of the RGMII interface comprises a first receiving clock signal, a first data unit and a receiving control signal; a receiving end signal of the GMII interface comprises a second receiving clock signal, a second data unit, a receiving data valid signal and a receiving error identification signal; an input end of the IDDR module unit is connected to the RGMII interface, and an output end of the IDDR module unit is connected to the GMII interface, and the IDDR module unit is used to convert the first data unit to a second data unit, and convert the receiving control signal to a receiving data valid signal and a receiving error identification signal respectively; through the above structure, the IDDR module unit is used in the present application to realize the conversion of the RGMII interface to the GMII interface, and compared with the Ethernet PHY chip used in the prior art, the IDDR module in the present application is relatively simple and can be directly integrated into the FPGA, reducing the dependence on external hardware and generally having a lower cost; at the same time, the IDDR module in the FPGA can be flexibly configured through programming to adapt to different design requirements and changes, and has a higher flexibility.

[0013] It should be understood that the description of technical features, technical solutions, beneficial effects or similar language in this application does not imply that all features and advantages can be realized in any single embodiment. On the contrary, it is understood that the description of features or beneficial effects means that specific technical features, technical solutions or beneficial effects are included in at least one embodiment. Therefore, the description of technical features, technical solutions or beneficial effects in this specification does not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and beneficial effects described in the present embodiment can also be combined in any appropriate manner. Those skilled in the art will understand that the embodiment can be realized without one or more specific technical features, technical solutions or beneficial effects of a specific embodiment. In other embodiments, additional technical features and beneficial effects can also be identified in a specific embodiment that does not embody all embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solution in this embodiment, the drawings required for use in the description of the embodiment will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A schematic diagram of a conversion circuit for converting an RGMII interface to a GMII interface provided in Example 1 of the present application.

[0016] In the figure: 1, the first IDDR module; 2, the second IDDR module; 3, the third IDDR module; 4, the fourth IDDR module; 5, the fifth IDDR module; 6, the first delay module; 7, the second delay module; 8, the third delay module; 9, the fourth delay module; 10, the fifth delay module; 11, the clock buffer module; 12, the first data cache module; 13, the second data cache module; 14, the third data cache module; 15, the fourth data cache module; 16, the buffer; 17, the XOR; D1: The first input terminal; C2: the second input terminal; D3: the third input terminal; C4: the fourth input terminal; D5: the fifth input terminal; C6: the sixth input terminal; D7: the seventh input terminal; C8: the eighth input terminal; D9: the ninth input terminal; C10: the tenth input terminal; Q1: the first output terminal; Q2: the second output terminal; Q3: the third output terminal; Q4: the fourth output terminal; Q5: the fifth output terminal; Q6: the sixth output terminal; Q7: the seventh output terminal; Q8: the eighth output terminal; Q9: the ninth output terminal; Q10: the tenth output terminal. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings. The description in this section is only exemplary and explanatory and should not have any limiting effect on the protection scope of the present application. Specifically, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work should fall within the scope of protection of the present application.

[0018] It should be noted that similar reference numerals and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0019] Example 1 Please refer to Figure 1 , a schematic diagram of a conversion circuit for converting an RGMII interface to a GMII interface provided in this embodiment includes: RGMII interface, the receiving end signal of the RGMII interface includes receiving a first clock signal, a first data unit and a receiving control signal; GMII interface, the receiving end signal of the GMII interface includes receiving a second clock signal, a second data unit, a receiving data valid signal and a receiving error identification signal; An IDDR module unit, the input end of the IDDR module unit is connected to the RGMII interface, the output end of the IDDR module unit is connected to the GMII interface, and the IDDR module unit is used to convert the first data unit into the second data unit, and convert the receiving control signal into a receiving data valid signal and a receiving error identification signal.

[0020] In this embodiment, the RGMII (Reduced Gigabit Media Independent Interface) interface adopts a double-edge DDR (Double Data Rate) mode, which means that data is transmitted at both the rising and falling edges of the clock, so that twice the data can be transmitted in each clock cycle; while the GMII (Gigabit Media Independent Interface) interface adopts a single-edge SDR (Single Data Rate) mode, where data is transmitted only at the rising edge of the clock, and data can only be transmitted once in each clock cycle; The IDDR module can receive data in dual-edge DDR mode and convert it into unit SDR mode output after processing. At the same time, the IDDR module can also adjust the timing of the received data to ensure that the data is correctly sampled and processed on the clock signal to avoid data loss or error; Working principle: In this application, an IDDR module unit is used to implement the conversion of the RGMII interface to the GMII interface. Compared with the Ethernet PHY chip used in the prior art, the IDDR module in this application is relatively simple and can be directly integrated into the FPGA, reducing dependence on external hardware and usually at a lower cost. At the same time, the IDDR module in the FPGA can be flexibly configured through programming to adapt to different design requirements and changes, with high flexibility.

[0021] In some embodiments, the first data unit includes: a first RGMII receive data signal, a second RGMII receive data signal, a third RGMII receive data signal, and a fourth RGMII receive data signal; The second data unit includes: a first GMII receive data signal, a second GMII receive data signal, a third GMII receive data signal, a fourth GMII receive data signal, a fifth GMII receive data signal, a sixth GMII receive data signal, a seventh GMII receive data signal and an eighth GMII receive data signal; The IDDR module unit includes: a first IDDR module 1, a second IDDR module 2, a third IDDR module 3, a fourth IDDR module 4, and a fifth IDDR module 5; the first IDDR module 1 has a first input terminal D1, a second input terminal C2, a first output terminal Q1, and a second output terminal Q2; the second IDDR module 2 has a third input terminal D3, a fourth input terminal C4, a third output terminal Q3, and a fourth output terminal Q4; the third IDDR module 3 has a fifth input terminal D5, a sixth output terminal Q6, a fourth fifth output terminal, and a sixth output terminal Q6; the fourth IDDR module 4 has a seventh input terminal D7, an eighth input terminal C8, a seventh output terminal Q7, and an eighth output terminal Q8; the fifth IDDR module 5 has a ninth input terminal D9, a fourth input terminal, a ninth output terminal Q9, and a tenth output terminal Q10; Among them, the second input terminal C2, the fourth input terminal C4, the sixth input terminal C6, the eighth input terminal C8, and the tenth input terminal C10 are all used to input the first clock signal; The first input terminal D1 is used to input the fourth RGMII receive data signal, the third input terminal D3 is used to input the third RGMII receive data signal, the fifth input terminal D5 is used to input the second RGMII receive data signal, the seventh input terminal D7 is used to input the first RGMII receive data signal, and the ninth input terminal D9 is used to input the receive control signal; The first output terminal Q1 is used to output the fourth GMII receive data signal, the second output terminal Q2 is used to output the eighth GMII receive data signal, the third output terminal Q3 is used to output the third GMII receive data signal, the fourth output terminal Q4 is used to output the seventh GMII receive data signal, the fifth output terminal Q5 is used to output the second GMII receive data signal, the sixth output terminal Q6 is used to output the sixth GMII receive data signal, the seventh output terminal Q7 is used to output the first GMII receive data signal, and the eighth output terminal Q8 is used to output the fifth GMII receive data signal; the ninth output terminal Q9 is used to output a receive data valid signal, and the tenth output terminal Q10 and the eleventh output terminal are also used to output a receive error identification signal.

[0022] Specifically, Figure 1 As shown in the figure, rgmii_rxd[0] is the first RGMII receive data signal, rgmii_rxd[1] is the second RGMII receive data signal, rgmii_rxd[2] is the third RGMII receive data signal, rgmii_rxd[3] is the third RGMII receive data signal, rgmii_rxc is the first clock signal, and rgmii_rx_ctl is the receive control signal; In the figure, gmii_rxd[0] is the first GMII receive data signal, gmii_rxd[1] is the second GMII receive data signal, gmii_rxd[2] is the third GMII receive data signal, gmii_rxd[3] is the fourth GMII receive data signal, gmii_rxd[4] is the fifth GMII receive data signal, gmii_rxd[5] is the sixth GMII receive data signal, gmii_rxd[6] is the seventh GMII receive data signal, gmii_rxd[7] is the eighth GMII receive data signal, gmii_rx_clk is the second clock signal, gmii_rx_dv is the receive data valid signal, and gmii_rx_er is the receive error identification signal; At the same time, in the figure: the first input terminal D1, the third input terminal D3, the fifth input terminal D5, the seventh input terminal D7 and the ninth input terminal D9 are data input terminals; the second input terminal C2, the fourth input terminal C4, the sixth input terminal C6, the eighth input terminal C8 and the tenth input terminal C10 are clock input terminals; the first output terminal Q1, the third output terminal Q3, the fifth output terminal Q5, the seventh output terminal Q7 and the ninth output terminal Q9 are rising edge data output terminals; the second output terminal Q2, the fourth output terminal Q4, the sixth output terminal Q6, the eighth output terminal Q8 and the tenth output terminal Q10 are falling edge data output terminals; After conversion by the IDDR module, the four signals rgmii_rxd[3]~rgmii_rxd[0] are converted to gmii_rxd[3]~gmii_rxd[0] and gmii_rxd[7]~gmii_rxd[4] respectively. After splicing, the GMII interface data gmii_rxd[7:0] can be obtained.

[0023] In some embodiments, the RGMII interface is connected to a clock buffer module 11, the input end of the clock buffer module 11 is used to input a first clock signal, the output end of the clock buffer module 11 is connected to a second input end C2, a fourth input end C4, a sixth input end C6, an eighth output end Q8 and a tenth input end C10, and the output end of the clock buffer module 11 is used to output a system clock.

[0024] Specifically, the RGMII interface is connected to a clock buffer module 11, the input end of the clock buffer module 11 is used to input a first clock signal, and the output end of the clock buffer module 11 is connected to a second input end C2, a fourth input end C4, a sixth input end C6, an eighth output end Q8 and a tenth input end C10; the first clock signal passes through the clock buffer module 11 and becomes a system clock, which is respectively connected to the first IDDR module 1, the second IDDR module 2, the third IDDR module 3, the fourth IDDR module 4, and the fifth IDDR module 5; at the same time, the system clock is input to the GMII interface as a second clock module; Specifically, the clock buffer module 11 can increase the driving capability of the clock, so that the input clock has the ability to provide clocks to various modules in the FPGA chip.

[0025] In some embodiments, the RGMII interface is connected to a delay module unit, which is used to make the first data unit and the receiving control signal reach the corresponding IDDR module at the same time, so as to achieve synchronous alignment of the input first data unit and the receiving control signal; the delay module unit includes: a first delay module 6, a second delay module 7, a third delay module 8, a fourth delay module 9 and a fifth delay module 10; Among them: the input end of the first delay module 6 is used to input the fourth RGMII receiving data signal, and the output end of the first delay module 6 is connected to the first input end D1; the input end of the second delay module 7 is used to input the third RGMII receiving data signal, and the output end of the second delay module 7 is connected to the third input end D3; the input end of the third delay module 8 is used to input the second RGMII receiving data signal, and the output end of the third delay module 8 is connected to the fifth input end D5; the input end of the fourth delay module 9 is used to input the first RGMII receiving data signal, and the output end of the fourth delay module 9 is connected to the seventh input end D7; the input end of the fifth delay module 10 is used to input the receiving control signal, and the output end of the fifth delay module 10 is connected to the ninth input end D9.

[0026] Specifically, the first RGMII received data signal, the second RGMII received data signal, the third RGMII received data signal, the fourth RGMII received data signal and the receiving control signal enter the corresponding IDDR module after passing through the delay modules connected to them respectively. Each delay module can adjust the signal arrival time according to external factors such as printed circuit board making to ensure that the five signals arrive at their corresponding IDDR modules at the same time. Each IDDR module converts the double-edge data within a clock cycle into single-edge data. The rising edge data is output at the first output terminal Q1, the third output terminal Q3, the fifth output terminal Q5, the seventh output terminal Q7 and the ninth output terminal Q9, and the falling edge data is output at the second output terminal Q2, the fourth output terminal Q4, the sixth output terminal Q6, the eighth output terminal Q8 and the tenth output terminal Q10.

[0027] In some embodiments, multiple data cache modules are also provided, and data cache modules are respectively provided between the first IDDR module 1, the second IDDR module 2, the third IDDR module 3, the fourth IDDR module 4 and the GMII interface, and the input ends of the multiple data cache modules are also connected to the output end of the clock buffer module 11; the data cache module is used to synchronize the output multiple GMII receiving data signals with the system clock.

[0028] Specifically, each IDDR module of the present application is correspondingly provided with a data buffer module, so the present embodiment also includes a first data cache module 12, a second data cache module 13, a third data cache module 14 and a fourth data cache module 15. The first IDDR module 1 is connected to the first data cache module 12, the second IDDR module 2 is connected to the second data cache module 13, the third IDDR module 3 is connected to the third data cache module 14, and the fourth IDDR module 4 is connected to the fourth data cache module 15. Since there will be a certain delay after the data passes through the IDDR module, causing it to be out of sync with the system clock, a data buffer module is set between the IDDR module and the GMII interface to cache the data output by the IDDR module for one clock cycle, and the data output after caching can be synchronized with the system clock.

[0029] In some embodiments, the ninth output terminal Q9 is connected to a buffer 16, the input terminal of the buffer 16 is also connected to the output terminal of the clock buffer module 11, the output terminal of the buffer 16 is used to output a valid received data signal, and the buffer 16 is used to synchronize the output valid received data signal with the system clock.

[0030] Specifically, the ninth output terminal Q9 is connected to the buffer 16, and the input terminal of the buffer 16 is also connected to the output terminal of the clock buffer module 11. After the receiving control signal passes through the fifth IDDR module 5, it is output by the ninth output terminal Q9 (i.e., the rising edge data output terminal) and cached by the buffer 16 for one clock cycle. The received data valid signal output after caching is synchronized with the system clock.

[0031] In some embodiments, the ninth output terminal Q9 and the tenth output terminal Q10 are commonly connected to an XOR device 17, the input end of the XOR device 17 is also connected to the output end of the clock buffer module 11, the output end of the XOR device 17 is used to output a receiving error identification signal, and the XOR device 17 is used to synchronize the output receiving error identification signal with the system clock.

[0032] Specifically, the receiving control signal passes through the fifth IDDR module 5, and the output rising edge data and falling edge data are XORed in the XOR device 17 to obtain a receiving error identification signal. Since the XOR device 17 can buffer data of one clock cycle, the receiving error identification signal is synchronously aligned with the first GMII receiving data signal, the second GMII receiving data signal, the third GMII receiving data signal, the fourth GMII receiving data signal, the fifth GMII receiving data signal, the sixth GMII receiving data signal, the seventh GMII receiving data signal, the eighth GMII receiving data signal, and the receiving data valid signal.

[0033] Specifically, the present application converts the first clock signal into the system clock through the clock buffer module 11, and provides an IDDR module unit, a delay module unit, a data cache module 13, a buffer 16 and an XOR 17; at this time, the delay module unit synchronizes the time when the first data unit and the receiving control signal arrive at the corresponding IDDR module with the system clock, thereby achieving synchronous alignment of the input first data unit and the receiving control signal; at the same time, multiple data buffer modules 13 synchronize the time when the second data unit is output with the system clock, the buffer 16 is used to synchronize the time when the valid signal of the received data is output with the system clock, and the XOR 17 is used to synchronize the time when the error identification signal is output with the system clock, thereby achieving synchronous alignment of the output second data unit, the valid signal of the received data and the error identification signal.

[0034] This article uses specific examples to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and its core ideas of this application. The above is only the preferred implementation method of this application. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concept and technical solution of the invention to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A conversion circuit for converting an RGMII interface to a GMII interface, characterized in that: include: RGMII interface, the receiving end signal of the RGMII interface includes receiving a first clock signal, a first data unit and a receiving control signal; A GMII interface, wherein a receiving end signal of the GMII interface includes a receiving second clock signal, a second data unit, a receiving data valid signal, and a receiving error identification signal; An IDDR module unit, wherein the input end of the IDDR module unit is connected to the RGMII interface, the output end of the IDDR module unit is connected to the GMII interface, and the IDDR module unit is used to convert the first data unit into a second data unit, and convert the receiving control signal into a receiving data valid signal and a receiving error identification signal.

2. The conversion circuit for converting an RGMII interface to a GMII interface according to claim 1, characterized in that: The first data unit includes: a first RGMII receive data signal, a second RGMII receive data signal, a third RGMII receive data signal and a fourth RGMII receive data signal; The second data unit includes: a first GMII receive data signal, a second GMII receive data signal, a third GMII receive data signal, a fourth GMII receive data signal, a fifth GMII receive data signal, a sixth GMII receive data signal, a seventh GMII receive data signal and an eighth GMII receive data signal; The IDDR module unit comprises: a first IDDR module (1), a second IDDR module (2), a third IDDR module (3), a fourth IDDR module (4), and a fifth IDDR module (5); the first IDDR module (1) has a first input terminal (D1), a second input terminal (C2), a first output terminal (Q1), and a second output terminal (Q2); the second IDDR module (2) has a third input terminal (D3), a fourth input terminal (C4), a third output terminal (Q3), and a fourth output terminal (Q4); the third IDDR module (3) has a fifth input terminal (D5), a sixth output terminal (Q6), a fourth fifth output terminal, and a sixth output terminal (Q6); the fourth IDDR module (4) has a seventh input terminal (D7), an eighth input terminal (C8), a seventh output terminal (Q7), and an eighth output terminal (Q8); the fifth IDDR module (5) has a ninth input terminal (D9), a fourth input terminal, a ninth output terminal (Q9), and a tenth output terminal (Q10); Wherein, the second input terminal (C2), the fourth input terminal (C4), the sixth input terminal (C6), the eighth input terminal (C8), and the tenth input terminal (C10) are all used to input the first clock signal; The first input terminal (D1) is used to input a fourth RGMII receiving data signal, the third input terminal (D3) is used to input a third RGMII receiving data signal, the fifth input terminal (D5) is used to input a second RGMII receiving data signal, the seventh input terminal (D7) is used to input a first RGMII receiving data signal, and the ninth input terminal (D9) is used to input a receiving control signal; The first output terminal (Q1) is used to output a fourth GMII receive data signal, the second output terminal (Q2) is used to output an eighth GMII receive data signal, the third output terminal (Q3) is used to output a third GMII receive data signal, the fourth output terminal (Q4) is used to output a seventh GMII receive data signal, the fifth output terminal (Q5) is used to output a second GMII receive data signal, the sixth output terminal (Q6) is used to output a sixth GMII receive data signal, the seventh output terminal (Q7) is used to output a first GMII receive data signal, and the eighth output terminal (Q8) is used to output a fifth GMII receive data signal; the ninth output terminal (Q9) is used to output a receive data valid signal, and the tenth output terminal (Q10) and the eleventh output terminal are also used to output a receive error identification signal.

3. The conversion circuit for converting the RGMII interface to the GMII interface according to claim 2, characterized in that: The RGMII interface is connected to a clock buffer module (11); an input end of the clock buffer module (11) is used to input the first clock signal; an output end of the clock buffer module (11) is connected to the second input end (C2), a fourth input end (C4), a sixth input end (C6), an eighth output end (Q8) and a tenth input end (C10); and an output end of the clock buffer module (11) is used to output a system clock.

4. The conversion circuit for converting the RGMII interface to the GMII interface according to claim 2, characterized in that: The RGMII interface is connected to a delay module unit, and the delay module unit is used to make the first data unit and the receiving control signal reach the corresponding IDDR module at the same time, so as to achieve synchronous alignment of the input first data unit and the receiving control signal; The delay module unit comprises: a first delay module (6), a second delay module (7), a third delay module (8), a fourth delay module (9) and a fifth delay module (10); Wherein: the input end of the first delay module (6) is used to input the fourth RGMII receive data signal, and the output end of the first delay module (6) is connected to the first input end (D1); the input end of the second delay module (7) is used to input the third RGMII receive data signal, and the output end of the second delay module (7) is connected to the third input end (D3); the input end of the third delay module (8) is used to input the second RGMII receive data signal, and the output end of the third delay module (8) is connected to the fifth input end (D5); the input end of the fourth delay module (9) is used to input the first RGMII receive data signal, and the output end of the fourth delay module (9) is connected to the seventh input end (D7); the input end of the fifth delay module (10) is used to input the receive control signal, and the output end of the fifth delay module (10) is connected to the ninth input end (D9).

5. The conversion circuit for converting the RGMII interface to the GMII interface according to claim 3, characterized in that: A plurality of data cache modules are also provided, wherein the first IDDR module (1), the second IDDR module (2), the third IDDR module (3), the fourth IDDR module (4) and the GMII interface are respectively provided with data cache modules, and the input ends of the plurality of data cache modules are also connected to the output end of the clock buffer module (11); the data cache modules are used to synchronize the outputted plurality of GMII received data signals with the system clock.

6. The conversion circuit for converting the RGMII interface to the GMII interface according to claim 3, characterized in that: The ninth output terminal (Q9) is connected to a buffer (16); the input terminal of the buffer (16) is also connected to the output terminal of the clock buffer module (11); the output terminal of the buffer (16) is used to output a received data valid signal; the buffer (16) is used to synchronize the output received data valid signal with the system clock.

7. The conversion circuit for converting the RGMII interface to the GMII interface according to claim 3, characterized in that: The ninth output terminal (Q9) and the tenth output terminal (Q10) are commonly connected to an XOR device (17); the input terminal of the XOR device (17) is also connected to the output terminal of the clock buffer module (11); the output terminal of the XOR device (17) is used to output a reception error identification signal; the XOR device (17) is used to synchronize the output reception error identification signal with the system clock.

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