Formation method of dynamic memory and dynamic memory

Abstract

The invention provides a method for forming a dynamic memory, which comprises the following steps of: etching a first substrate according to a first photoetching pattern to form a silicon column structure separated by a first groove; and forming a storage capacitor by taking the silicon column structure as a capacitor plate, and forming a vertical transfer gate structure above the silicon column structure. The method is simple in process step, can form a high-density trench capacitor as a storage capacitor, is high in integration density, can be compatible with a forming process of an image sensor, and is wide in applicability. Meanwhile, according to the scheme, the polycrystalline silicon grid electrode and the active region can be used as the connection of the word line and the bit line, and the traditional capacitance density limit is broken through.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a dynamic memory and the dynamic memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary byte is 1 or 0. The basic unit of DRAM is very simple. It is usually a transistor connected in series with a capacitor. The transistor is used to control the capacitor to store or erase electrons, thereby controlling the transmission of information. A DRAM basic unit can only store one byte of data. An existing DRAM storage unit is a memory circuit composed of a MOS tube and a capacitor, in which the MOS tube is used as a switch and the capacitor is used as a storage medium. DRAM capacitors are generally formed in a stacked or trenched manner. The advantages are that they occupy a small area, can achieve large capacity, and have a high density. However, its density is affected by metal wiring and has a density limit. As the amount of data input and output of chips increases, information chips require more and more DRAMs, but this will occupy a large area of ​​the chip. Therefore, higher requirements are placed on high-density DRAM design. Summary of the invention

[0003] The object of the present invention is to provide a method for forming a dynamic memory, comprising: Etching the first substrate according to the first photolithography pattern to form silicon pillar structures separated by first trenches; The silicon pillar structure is used as a capacitor plate to form a storage capacitor, and a vertical transfer gate structure is formed above the silicon pillar structure.

[0004] Furthermore, after the silicon pillar structures are formed, the method further includes: performing chemical mechanical polishing on the bottom of the first substrate until the silicon pillar structures are electrically isolated from each other.

[0005] Furthermore, a second substrate doped with a high concentration is provided, wherein the second substrate is located at the bottom of the first substrate and has a doping type opposite to that of the silicon pillar structure. When forming the silicon pillar structure, the first substrate is etched to a certain depth so that each silicon pillar structure is electrically isolated from each other to optimize the performance of the storage capacitor.

[0006] Furthermore, at least some of the upper portions of the silicon column structures are connected to each other via a connecting structure to provide support to prevent the silicon column structures from falling over.

[0007] Further, a hard mask layer is formed according to the first photolithography pattern, and the first substrate is etched according to the hard mask layer to form the connection structure, and the connection structure at least includes the hard mask layer or a combination of the hard mask layer and a portion of the first substrate.

[0008] Further, etching the first substrate according to the hard mask layer to form the connection structure includes: The first substrate is etched according to the hard mask layer, and the first trench and the silicon pillar structure are formed by adjusting the etching process conditions, while the hard mask layer or the combination of the hard mask layer and part of the first substrate forms the connection structure.

[0009] Further, etching the first substrate according to the hard mask layer to form the connection structure includes: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Etching the first dielectric layer and the first substrate at the bottom of the second trench to form a third trench; The third trench is widened on both sides by isotropic etching to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is used for protection so that the hard mask layer and a part of the first substrate form the connection structure.

[0010] Further, etching the first substrate according to the hard mask layer to form the connection structure includes: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Continue to etch the bottom of the first dielectric layer and the first substrate, and adjust the etching process conditions to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is protected so that the combination of the hard mask layer and part of the first substrate forms the connection structure.

[0011] Furthermore, after forming the first trench, the width of the bottom of the first trench is reduced through at least one epitaxial process to increase the capacitance value.

[0012] Furthermore, after the width of the bottom of the first trench is reduced by at least one epitaxial process, the width of the upper portion of the first trench is increased by etching again in a self-aligned manner through the first photolithography pattern, so as to optimize subsequent processes.

[0013] Further, forming a vertical transfer gate structure above the silicon pillar structure includes: forming a second dielectric layer on the surface of the first trench; Filling polysilicon in the second dielectric layer to form a polysilicon layer; According to the second photolithography pattern, the polysilicon layer and the first substrate are etched, and the surface of the polysilicon layer is made lower than the first substrate by controlling the etching selection ratio, so as to form a fifth trench; Filling the fifth trench with a dielectric to form a third dielectric layer, wherein the third dielectric layer forms a shallow trench isolation structure and an active area; According to the third photolithography pattern, etching the third dielectric layer on the sidewall of the active area to expose the silicon on the side of the active area to form a vertical transfer channel; A fourth dielectric layer is formed and filled with polysilicon to form a polysilicon gate.

[0014] Furthermore, the active area is used as a bit line of the dynamic memory.

[0015] Furthermore, the polysilicon gate is used as a word line of the dynamic memory.

[0016] The present invention also provides a dynamic memory, which is formed by adopting the above-mentioned method for forming the dynamic memory.

[0017] The present invention proposes a solution with simple process steps and capable of forming high-density trench capacitors as storage capacitors. The solution has high integration density and is compatible with the formation process of image sensors and has wide applicability. At the same time, the solution can use polysilicon gates and active areas as connections between word lines and bit lines, breaking through the traditional capacitance density limit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0019] Figure 1 A schematic diagram of shape combinations of different photolithography patterns in an embodiment of the present invention; Figure 2~Figure 13 Schematic diagram of the structure of the dynamic memory in different embodiments of the present invention.

[0020] In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout different drawings. Implementation

[0021] The object of the present invention is to provide a method for forming a dynamic memory, which may specifically include the following steps: Step S100: According to the first photolithography pattern A (such as Figure 1 As shown in FIG. 1 , the first substrate 100 is etched to form a silicon pillar structure 120 separated by the first trench 110. Figure 2 As shown; Step S200 : using the silicon pillar structure 120 as a capacitor plate to form a storage capacitor, and forming a vertical transfer gate structure (VTG) above the silicon pillar structure 120 .

[0022] Optionally, in the present invention, in order to realize the function of storage capacitor, each silicon pillar structure 120 as a capacitor plate should be in an electrically isolated state. The present invention does not limit the specific technical solution for electrically isolating each silicon pillar structure 120. For example, in an optional embodiment, after forming the silicon pillar structure 120, the bottom of the first substrate 100 can be subjected to chemical mechanical polishing (CMP) until each silicon pillar structure 120 is electrically isolated from each other. Figure 3 In another optional embodiment, a highly doped second substrate 200 may be provided outside the first substrate 100, as shown in FIG. Figure 4 As shown, the second substrate 200 is located at the lower part of the first substrate 100, and the doping type is opposite to that of the silicon pillar structure 120, that is, if the first substrate 100 is N-type doped, the second substrate 200 adopts high-concentration P-type doping; if the first substrate 100 is P-type doped, the second substrate 200 adopts high-concentration N-type doping. When the silicon pillar structure 120 is formed in step S100, the first substrate 100 is etched to a certain depth, for example, it can be into the second substrate 200, or close to the interface between the first substrate 100 and the second substrate 200. Due to the different doping types, the purpose of electrically isolating the silicon pillar structures 120 from each other is achieved to optimize the performance of the storage capacitor.

[0023] In an optional embodiment, at least part of the upper portions of the silicon pillar structures 120 formed in the present invention may be connected to each other via a connecting structure 121 to provide support strength in subsequent process steps to prevent the silicon pillar structures 120 from falling over.

[0024] Specifically, in one embodiment, in step S100, when etching to form the silicon pillar structure 120, a hard mask layer 300 can be first formed according to the first photolithography pattern A, and then the first substrate 100 is etched according to the hard mask layer 300, and the connecting structure 121 is formed while the silicon pillar structure 120 is formed, wherein the connecting structure 121 includes at least a partial structure of the hard mask layer 300, or simultaneously includes a combination of the hard mask layer 300 and a portion of the first substrate 100.

[0025] Preferably, the connection structure 121 can be formed according to the following steps: Step S111: etching the first substrate 100 according to the hard mask layer 300, and adjusting the etching process conditions to form the first trench 110 and the silicon pillar structure 120, and at the same time making the hard mask layer 300 or the combination of the hard mask layer 300 and a part of the first substrate 100 form the connection structure 121, such as Figure 5 or Figure 6 shown.

[0026] In order to realize the form of the connection structure 121, the preferred solution is to directly adjust the process conditions when etching to form the groove, such as using isotropic etching, so that the hard mask layer 300 between the silicon pillar structures 120 is retained, such as Figure 5 As shown in FIG. 1 , the connection structure 121 supporting the silicon pillar structure 120 is formed. When the support is no longer needed in the subsequent process steps, the hard mask layer 300 is also more convenient to remove. At the same time, a portion of the first substrate 100 under the hard mask layer 300 can also be retained, such as Figure 6 As shown, they together play the role of connecting support.

[0027] In another optional manner, the connection structure 121 may be formed by the following steps: Step S121: etching the first substrate 100 according to the hard mask layer 300 to form a second trench 130; Step S122: forming a first dielectric layer 131 on the surface of the second trench 130, such as Figure 7 As shown; Step S123: etching the first dielectric layer 131 and the first substrate 100 at the bottom of the second trench 130 to form a third trench 140. Figure 8 As shown; Step S124: using isotropic etching to widen the third trench 140 on both sides to form the first trench 110 and the silicon pillar structure 120, and at the same time, through the protection of the first dielectric layer 131, the combination of the hard mask layer 300 and a part of the first substrate 100 forms the connection structure 121, such as Fig. 9 shown.

[0028] Through the above steps, the hard mask layer 300 and the first substrate 100 thereunder can form the connection structure 121. After the etching process, preferably, the first dielectric layer 131 can be removed.

[0029] Likewise, optionally, the third trench 140 may not be formed, and the first dielectric layer 131 and the first substrate 100 at the bottom of the second trench 130 may be directly etched, such as the following steps: Step S131: etching the first substrate 100 according to the hard mask layer 300 to form a second trench 130; Step S132: forming a first dielectric layer 131 on the surface of the second trench 130; Step S133: Continue etching the bottom of the first dielectric layer 131 and the first substrate 100, and form the first groove 110 and the silicon pillar structure 120 by adjusting the etching process conditions. At the same time, through the protection of the first dielectric layer 131, the combination of the hard mask layer 300 and part of the first substrate 100 forms the connection structure 121.

[0030] Compared with the previous optional implementation, this method has a relatively poor etching effect, but it can also realize the connection structure 121 and provide strength support for the silicon pillar structure 120.

[0031] Preferably, in an embodiment, after forming the first trench 110 , the width of the bottom of the first trench 110 may be reduced by at least one epitaxial process, so that the capacitance value may be increased after the storage capacitor is subsequently formed.

[0032] Further, after the width of the bottom of the first trench 110 is reduced, the first photolithography pattern A (eg Figure 1 As shown in the figure, the first trench 110 is etched again in a self-aligned manner to increase the width of the upper portion of the first trench 110 to optimize subsequent processes.

[0033] In an optional implementation, in step S200, a vertical transfer gate structure (VTG) may be formed on the silicon pillar structure 120 by the following steps: Step S210: forming a second dielectric layer 111 on the surface of the first trench 110; Step S220: Fill the second dielectric layer 111 with polysilicon to form a polysilicon layer 112. Fig.10 As shown; Step S230: According to the second photolithography pattern B (such as Figure 1 As shown in FIG. 1 ), the polysilicon layer 112 and the first substrate 100 are etched, and the surface of the polysilicon layer 112 is made lower than the first substrate 100 by controlling the etching selection ratio, so as to form a fifth trench 140; Step S240: Fill the fifth trench 150 with dielectric to form a third dielectric layer 151, wherein the third dielectric layer 151 forms a shallow trench isolation (STI) structure and an active area (AA), such as Fig.11 As shown; Step S250: According to the third photolithography pattern C (such as Figure 1 As shown), the third dielectric layer 151 on the side wall of the active area (AA) is etched to expose the silicon on the side of the active area (AA) to form a vertical transfer channel, as shown in FIG. Fig.12 As shown; Step S260: forming a fourth dielectric layer 160 and filling it with polysilicon, according to a fourth photolithography pattern D (such as Figure 1 As shown) is etched to form a polysilicon gate 170, as shown Fig.13 shown.

[0034] On the basis of the above process steps, the present invention can also use the active area (AA) as the bit line of the dynamic memory; also optionally, the polysilicon gate 160 can be used as the word line of the dynamic memory.

[0035] On this basis, the present invention further provides a dynamic memory formed by the above-mentioned method for forming a dynamic memory.

[0036] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, in any case, the embodiments should be considered exemplary and non-restrictive. In addition, it is clear that the term "comprising" does not exclude other elements and steps, and the wording "a" does not exclude the plural. Multiple elements stated in a device claim may also be implemented by one element. The terms first, second, etc. are used to indicate names and do not indicate any particular order.

Claims

1. A method for forming a dynamic memory, characterized in that: include: Etching the first substrate according to the first photolithography pattern to form silicon pillar structures separated by first trenches; The silicon pillar structure is used as a capacitor plate to form a storage capacitor, and a vertical transfer gate structure is formed above the silicon pillar structure.

2. The method for forming a dynamic memory according to claim 1, wherein: After the silicon pillar structures are formed, the method further includes: performing chemical mechanical polishing on the bottom of the first substrate until the silicon pillar structures are electrically isolated from each other.

3. The method for forming a dynamic memory according to claim 1, wherein: A second substrate doped with a high concentration is provided. The second substrate is located at the bottom of the first substrate and has a doping type opposite to that of the silicon pillar structure. When forming the silicon pillar structure, the first substrate is etched to a certain depth so that the silicon pillar structures are electrically isolated from each other to optimize the performance of the storage capacitor.

4. The method for forming a dynamic memory according to claim 1, wherein: At least some of the upper portions of the silicon column structures are connected to each other via a connecting structure to provide support and prevent the silicon column structures from falling over.

5. The method for forming a dynamic memory according to claim 4, wherein: A hard mask layer is formed according to the first photolithography pattern, and the first substrate is etched according to the hard mask layer to form the connection structure, wherein the connection structure at least includes the hard mask layer or a combination of the hard mask layer and a portion of the first substrate.

6. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: The first substrate is etched according to the hard mask layer, and the first trench and the silicon pillar structure are formed by adjusting the etching process conditions, and the hard mask layer or the combination of the hard mask layer and part of the first substrate forms the connection structure.

7. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Etching the first dielectric layer and the first substrate at the bottom of the second trench to form a third trench; The third trench is widened on both sides by isotropic etching to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is used for protection so that the hard mask layer and a part of the first substrate form the connection structure.

8. The method for forming a dynamic memory according to claim 5, wherein: The etching the first substrate according to the hard mask layer to form the connection structure comprises: Etching the first substrate according to the hard mask layer to form a second trench; forming a first dielectric layer on the surface of the second groove; Continue to etch the bottom of the first dielectric layer and the first substrate, and adjust the etching process conditions to form the first trench and the silicon pillar structure. At the same time, the first dielectric layer is protected so that the combination of the hard mask layer and part of the first substrate forms the connection structure.

9. The method for forming a dynamic memory according to claim 1, wherein: After forming the first trench, the width of the bottom of the first trench is reduced by at least one epitaxial process to increase the capacitance value.

10. The method for forming a dynamic memory according to claim 9, wherein: After the width of the bottom of the first trench is reduced by at least one epitaxial process, the first photolithography pattern is self-alignedly etched again to increase the width of the upper portion of the first trench, so as to optimize subsequent processes.

11. The method for forming a dynamic memory according to claim 1, wherein: The forming of a vertical transfer gate structure above the silicon pillar structure comprises: forming a second dielectric layer on the surface of the first trench; Filling polysilicon in the second dielectric layer to form a polysilicon layer; According to the second photolithography pattern, the polysilicon layer and the first substrate are etched, and the surface of the polysilicon layer is made lower than the first substrate by controlling the etching selection ratio, so as to form a fifth trench; Filling the fifth trench with a dielectric to form a third dielectric layer, wherein the third dielectric layer forms a shallow trench isolation structure and an active area; According to the third photolithography pattern, etching the third dielectric layer on the sidewall of the active area to expose the silicon on the side of the active area to form a vertical transfer channel; A fourth dielectric layer is formed and filled with polysilicon to form a polysilicon gate.

12. The method for forming a dynamic memory according to claim 11, wherein: The active area is used as a bit line of the dynamic memory.

13. The method for forming a dynamic memory according to claim 11, wherein: The polysilicon gate is used as a word line of the dynamic memory.

14. A dynamic memory, characterized in that: The dynamic memory is formed by the method for forming the dynamic memory as described in claims 1 to 13.

Images