Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of transistors which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the word lines penetrate through the different layers and extend in the direction perpendicular to the substrate; the transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the side wall of the word line; the semiconductor layer is connected with the side walls of the first electrode and the second electrode, and is connected with at least one of the upper surface and the lower surface of the first electrode or the second electrode. According to the scheme provided by the embodiment, the semiconductor layer can be connected with the side walls of the first electrode and the second electrode, and is also connected with at least one of the upper surface and the lower surface of the first electrode or the second electrode, so that the contact area is increased, and the contact resistance is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] Taking DRAM as an example, the traditional known DRAM has multiple repeated "storage cells", each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to the binary data "1" and "0" respectively. The transistor is the switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people hope to make as many storage units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which reduce the contact resistance between a semiconductor layer and an electrode.

[0007] The present disclosure provides a semiconductor device, including:

[0008] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0009] A word line, extending through the different layers in a direction perpendicular to the substrate;

[0010] The transistor includes a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer is connected to the sidewalls of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode or the second electrode.

[0011] In some embodiments, the semiconductor layer is connected to an upper surface and a lower surface of the first electrode, and the semiconductor layer is connected to an upper surface and a lower surface of the second electrode.

[0012] In some embodiments, the semiconductor layer wraps a first end surface of the first electrode facing the word line, a region of the upper surface of the first electrode whose distance from the first end surface is less than or equal to a first preset distance, and a region of the lower surface of the first electrode whose distance from the first end surface is less than or equal to a second preset distance.

[0013] In some embodiments, the semiconductor layer wraps the second end surface of the second electrode facing the word line, as well as an area in the upper surface of the second electrode whose distance from the second end surface is less than or equal to a third preset distance, and an area in the lower surface of the second electrode whose distance from the second end surface is less than or equal to a fourth preset distance.

[0014] In some embodiments, the plurality of semiconductor layers of the plurality of transistors are spaced apart.

[0015] In some embodiments, the semiconductor device further comprises:

[0016] A first insulating layer, a first sacrificial layer, a first conductive layer, and a second sacrificial layer are alternately distributed from bottom to top in a direction vertical to the substrate;

[0017] A through hole is formed through each of the first insulating layers, each of the first sacrificial layers, each of the first conductive layers, and each of the second sacrificial layers, wherein the word line, a plurality of gate insulating layers surrounding the side walls of the word line, and a plurality of semiconductor layers surrounding the side walls of the gate insulating layers are sequentially distributed in the through hole from the inside to the outside.

[0018] In some embodiments, the diameter of the through hole corresponding to the first region of the first conductive layer is larger than the diameter of the through hole corresponding to the second region of the first insulating layer; the diameter of the through hole corresponding to the first region of the first conductive layer is smaller than the diameter of the through hole corresponding to the third region of the first sacrificial layer; the diameter of the through hole corresponding to the first region of the first conductive layer is smaller than the diameter of the through hole corresponding to the fourth region of the second sacrificial layer;

[0019] The first conductive layer exposes part of the sidewall and upper and lower surfaces in the through hole, and the first insulating layer exposes part of the sidewall and upper and lower surfaces in the through hole; the first sacrificial layer only exposes the sidewall in the through hole, and the second sacrificial layer only exposes the sidewall in the through hole;

[0020] The semiconductor layer is distributed on the sidewall of the first conductive layer, and is distributed on the entire region of the upper and lower surfaces of the first conductive layer exposed in the through hole.

[0021] In some embodiments, the semiconductor layer is also distributed on all or part of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the sidewall of the first insulating layer.

[0022] In some embodiments, the gate insulating layer is distributed on the surface of each of the semiconductor layers and is not distributed on the sidewall of the first insulating layer, and the gate insulating layers on the surfaces of the semiconductor layers of different layers are spaced apart from each other.

[0023] In some embodiments, the word line includes a second portion extending along the through hole, and a first portion located at a sidewall of each of the gate insulating layers.

[0024] In some embodiments, the contact area between the semiconductor layer and the first insulating layer is laterally etched to form a recessed area along the lateral direction, and the recessed area is provided with an isolation layer, and the isolation layer is distributed on the surface of the semiconductor layer and the surface of the gate insulating layer.

[0025] In some embodiments, the first electrode includes a first end face facing the word line and a second end face away from the word line, as well as a side surface connecting the first end face and the second end face. The semiconductor device also includes a capacitor, the capacitor includes a first pole and a second pole, the first electrode serves as the first pole of the capacitor, and the second pole surrounds the side surface of the first electrode.

[0026] In some embodiments, the semiconductor device further includes: a support layer extending in a direction perpendicular to the substrate, the support layer wrapping the second end surface of each first electrode and wrapping a region of the side surface close to the second end surface.

[0027] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments.

[0028] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, and a word line extending along a direction perpendicular to the substrate through the different layers, wherein the transistor comprises a first electrode and a second electrode, and the method for manufacturing the semiconductor device comprises:

[0029] A substrate is provided, and a plurality of stacked structures are formed on the substrate; each of the stacked structures comprises a stack of a first insulating layer and a first conductive layer, the first insulating layer is arranged on a side of the first conductive layer facing the substrate, the stacked structure further comprises a sacrificial layer, the sacrificial layer comprises at least one of the following: a first sacrificial layer arranged on a side of the first conductive layer facing the first insulating layer, and a second sacrificial layer arranged on a side of the first conductive layer away from the first insulating layer; the first conductive layer comprises a preset electrode pattern, the preset electrode pattern comprises a first electrode and a second electrode of the transistor to be formed;

[0030] Etching the stacked structure to form a through hole penetrating the plurality of stacked structures in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes each of the first conductive layers, and laterally etching the first conductive layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first insulating layer falls within the orthographic projection of the through hole located in the first conductive layer, and laterally etching the sacrificial layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first conductive layer falls within the orthographic projection of the through hole located in the sacrificial layer, and the through hole disconnects the first electrode and the second electrode in the preset electrode pattern;

[0031] Depositing a semiconductor film and a gate insulating film in the through hole in sequence to form a multi-layer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode, and the semiconductor layer is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode;

[0032] A word line is formed in the through hole.

[0033] In some embodiments, forming a word line in the through hole comprises:

[0034] Depositing a protective layer film in the through hole to form a protective layer, wherein the protective layer film is a conductive film;

[0035] Etching the protective layer in the through hole so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and the side wall of the through hole located in the first conductive layer exposes the protective layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer;

[0036] A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.

[0037] In some embodiments, etching the protective layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the gate insulating layer, and the sidewall of the through hole located in the first conductive layer exposes the protective layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole located in the first insulating layer comprises:

[0038] Etching the protective layer in the through hole by wet etching, so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and a portion of the protective layer is retained in the through hole located in the first insulating layer;

[0039] The semiconductor layer and the gate insulating layer located in the through hole of the first insulating layer are removed by wet etching.

[0040] In some embodiments, after the etching removes the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer and before depositing a gate electrode film in the through hole, the method further includes:

[0041] Depositing a gate insulating film in the through hole to form an isolation layer;

[0042] The isolation layer covering the side of the protection layer facing the through hole is removed by etching.

[0043] The disclosed embodiments include a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a word line extending through the different layers in a direction perpendicular to the substrate; the transistor includes a first electrode, a second electrode, and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer is connected to the sidewalls of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode or the second electrode. In the solution provided in this embodiment, the semiconductor layer can be connected to the sidewalls of the first electrode and the second electrode, and is also connected to at least one of the upper surface and the lower surface of the first electrode or the second electrode, thereby increasing the contact area and reducing the contact resistance.

[0044] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0045] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

[0047] Figure 1A A schematic plan view of a semiconductor device provided as an exemplary embodiment;

[0048] Figure 1B For along Figure 1A Schematic diagram of the aa' direction;

[0049] Figure 1C For along Figure 1A Schematic diagram of the bb' direction;

[0050] Figure 1D For along Figure 1A Schematic diagram of the cc' direction;

[0051] Figure 1E For along Figure 1A Schematic diagram of the dd' direction;

[0052] Figure 2A A cross-sectional view along the aa' direction after a stacked structure is formed provided by an exemplary embodiment;

[0053] Figure 2B A cross-sectional view along the bb' direction after a stacked structure is formed provided by an exemplary embodiment;

[0054] Figure 2C A cross-sectional view along the cc' direction after a stacked structure is formed according to an exemplary embodiment;

[0055] Figure 2D A cross-sectional view along the dd' direction after a stacked structure is formed provided by an exemplary embodiment;

[0056] Figure 3A A cross-sectional view along the aa' direction after a preset electrode pattern is formed provided by an exemplary embodiment;

[0057] Figure 3B A cross-sectional view along the bb' direction after a preset electrode pattern is formed provided by an exemplary embodiment;

[0058] Figure 3C A cross-sectional view along the cc' direction after a preset electrode pattern is formed provided by an exemplary embodiment;

[0059] Figure 3D A cross-sectional view along the dd' direction after a preset electrode pattern is formed provided by an exemplary embodiment;

[0060] Figure 3E A schematic diagram of a preset electrode pattern provided for an exemplary embodiment;

[0061] Figure 4A A cross-sectional view along the aa' direction after forming a third insulating layer provided for an exemplary embodiment;

[0062] Figure 4B A cross-sectional view along the bb' direction after forming a third insulating layer provided by an exemplary embodiment;

[0063] Figure 4C A cross-sectional view along the cc' direction after forming a third insulating layer provided by an exemplary embodiment;

[0064] Figure 4D A cross-sectional view along the dd' direction after forming a third insulating layer provided by an exemplary embodiment;

[0065] Figure 5AA cross-sectional view along the aa' direction after forming the second trench provided for an exemplary embodiment;

[0066] Figure 5B A cross-sectional view along the bb' direction after forming the second groove provided for an exemplary embodiment;

[0067] Figure 5C A cross-sectional view along the cc' direction after forming a second trench provided for an exemplary embodiment;

[0068] Figure 5D A cross-sectional view along the dd' direction after forming the second trench provided for an exemplary embodiment;

[0069] Fig. 6A A cross-sectional view along the aa' direction after forming a support layer provided by an exemplary embodiment;

[0070] Figure 6B A cross-sectional view along the bb' direction after forming a support layer provided by an exemplary embodiment;

[0071] Figure 6C A cross-sectional view along the cc' direction after forming a support layer provided by an exemplary embodiment;

[0072] Fig.6D A cross-sectional view along the dd' direction after forming a support layer provided by an exemplary embodiment;

[0073] Fig. 7A A cross-sectional view along the aa' direction after forming a fourth insulating layer and a first hard mask layer provided for an exemplary embodiment;

[0074] Figure 7B A cross-sectional view along the bb' direction after forming a fourth insulating layer and a first hard mask layer provided for an exemplary embodiment;

[0075] Figure 7C A cross-sectional view along the cc' direction after forming a fourth insulating layer and a first hard mask layer provided for an exemplary embodiment;

[0076] Fig.7D A cross-sectional view along the dd' direction after forming a fourth insulating layer and a first hard mask layer provided for an exemplary embodiment;

[0077] Fig. 8A A cross-sectional view along the aa' direction after forming a third trench provided for an exemplary embodiment;

[0078] Figure 8B A cross-sectional view along the bb' direction after forming a third trench provided for an exemplary embodiment;

[0079] Figure 8CA cross-sectional view along the cc' direction after forming a third trench provided for an exemplary embodiment;

[0080] Fig.8D A cross-sectional view along the dd' direction after forming a third trench provided for an exemplary embodiment;

[0081] Fig. 9A A cross-sectional view along the aa' direction after exposing the first sacrificial layer and the second sacrificial layer provided for an exemplary embodiment;

[0082] Fig. 9B A cross-sectional view along the bb' direction after the first sacrificial layer and the second sacrificial layer are exposed provided for an exemplary embodiment;

[0083] Figure 9B' A cross-sectional view along the bb' direction after exposing the first sacrificial layer and the second sacrificial layer provided for another exemplary embodiment;

[0084] Fig. 9C A cross-sectional view along the cc' direction after exposing the first sacrificial layer and the second sacrificial layer provided for an exemplary embodiment;

[0085] Fig.9D A cross-sectional view along the dd' direction after the first sacrificial layer and the second sacrificial layer are exposed is provided for an exemplary embodiment;

[0086] Fig. 10A A cross-sectional view along the aa' direction after the first conductive portion is exposed provided by an exemplary embodiment;

[0087] Fig. 10B A cross-sectional view along the bb' direction after the first conductive portion is exposed provided by an exemplary embodiment;

[0088] Fig. 10C A cross-sectional view along the cc' direction after the first conductive portion is exposed provided by an exemplary embodiment;

[0089] Fig. 10D A cross-sectional view along the dd' direction after the first conductive portion is exposed provided by an exemplary embodiment;

[0090] Fig.11A A cross-sectional view along the aa' direction after the first hard mask layer is removed by etching provided for an exemplary embodiment;

[0091] Fig. 11B A cross-sectional view along the bb' direction after the first hard mask layer is removed by etching provided for an exemplary embodiment;

[0092] Fig. 11C A cross-sectional view along the cc' direction after the first hard mask layer is removed by etching provided for an exemplary embodiment;

[0093] Fig.11D A cross-sectional view along the dd' direction after the first hard mask layer is removed by etching provided for an exemplary embodiment;

[0094] Fig. 12A A cross-sectional view along the aa' direction after forming a dielectric layer and a second pole provided by an exemplary embodiment;

[0095] Fig. 12B A cross-sectional view along the bb' direction after forming a dielectric layer and a second pole provided by an exemplary embodiment;

[0096] Fig. 12C A cross-sectional view along the cc' direction after forming a dielectric layer and a second pole provided by an exemplary embodiment;

[0097] Fig.12D A cross-sectional view along the dd' direction after forming a dielectric layer and a second pole provided by an exemplary embodiment;

[0098] Fig.13A A cross-sectional view along the aa' direction after forming a fourth trench provided for an exemplary embodiment;

[0099] Fig. 13B A cross-sectional view along the bb' direction after forming a fourth trench provided for an exemplary embodiment;

[0100] Fig. 13C A cross-sectional view along the cc' direction after forming a fourth trench provided for an exemplary embodiment;

[0101] Fig.13D A cross-sectional view along the dd' direction after forming a fourth trench provided for an exemplary embodiment;

[0102] Fig.14A A cross-sectional view along the aa' direction after forming the sixth insulating layer provided by an exemplary embodiment;

[0103] Fig. 14B A cross-sectional view along the bb' direction after forming the sixth insulating layer provided by an exemplary embodiment;

[0104] Fig. 14C A cross-sectional view along the cc' direction after forming a sixth insulating layer provided by an exemplary embodiment;

[0105] Fig.14D A cross-sectional view along the dd' direction after forming the sixth insulating layer provided by an exemplary embodiment;

[0106] Fig.15A A cross-sectional view along the aa' direction after an initial through hole is formed provided for an exemplary embodiment;

[0107] Fig. 15BA cross-sectional view along the bb' direction after an initial through hole is formed provided for an exemplary embodiment;

[0108] Fig. 15C A cross-sectional view along the cc' direction after forming an initial through hole provided by an exemplary embodiment;

[0109] Fig.15D A cross-sectional view along the dd' direction after an initial through hole is formed provided for an exemplary embodiment;

[0110] Fig.16A A cross-sectional view along the aa' direction after the first conductive layer is laterally etched provided for an exemplary embodiment;

[0111] Fig. 16B A cross-sectional view along the bb' direction after the first conductive layer is laterally etched provided for an exemplary embodiment;

[0112] Fig. 16C A cross-sectional view along the cc' direction after the first conductive layer is laterally etched provided for an exemplary embodiment;

[0113] Fig.16D A cross-sectional view along the dd' direction after the first conductive layer is laterally etched provided for an exemplary embodiment;

[0114] Fig.17A A cross-sectional view along the aa' direction after the first sacrificial layer and the second sacrificial layer are laterally etched, provided in accordance with an exemplary embodiment;

[0115] Fig. 17B A cross-sectional view along the bb' direction after the first sacrificial layer and the second sacrificial layer are laterally etched, provided in accordance with an exemplary embodiment;

[0116] Fig. 17C A cross-sectional view along the cc' direction after the first sacrificial layer and the second sacrificial layer are laterally etched, provided for an exemplary embodiment;

[0117] Fig.17D A cross-sectional view along the dd' direction after the first sacrificial layer and the second sacrificial layer are laterally etched, provided in accordance with an exemplary embodiment;

[0118] Fig.18A A cross-sectional view along the aa' direction after forming a semiconductor layer, a gate insulating layer and a protective layer provided for an exemplary embodiment;

[0119] Fig.18B A cross-sectional view along the bb' direction after forming a semiconductor layer, a gate insulating layer and a protective layer provided by an exemplary embodiment;

[0120] Fig.18C A cross-sectional view along the cc' direction after forming a semiconductor layer, a gate insulating layer and a protective layer provided by an exemplary embodiment;

[0121] Fig.18D A cross-sectional view along the dd' direction after forming a semiconductor layer, a gate insulating layer and a protective layer provided by an exemplary embodiment;

[0122] Fig.19A A cross-sectional view along the aa' direction after etching the protective layer provided by an exemplary embodiment;

[0123] Fig.19B A cross-sectional view along the bb' direction after etching the protective layer provided by an exemplary embodiment;

[0124] Fig.19C A cross-sectional view along the cc' direction after etching the protective layer provided by an exemplary embodiment;

[0125] Fig.19D A cross-sectional view along the dd' direction after etching the protective layer provided by an exemplary embodiment;

[0126] Fig. 20A A cross-sectional view along the aa' direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

[0127] Fig. 20B A cross-sectional view along the bb' direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

[0128] Fig. 20C A cross-sectional view along the cc' direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

[0129] Fig.20D A cross-sectional view along the dd' direction after etching the semiconductor layer and the gate insulating layer provided by an exemplary embodiment;

[0130] Fig.21A A cross-sectional view along the aa' direction after forming an isolation layer provided by an exemplary embodiment;

[0131] Fig. 21B A cross-sectional view along the bb' direction after forming an isolation layer provided by an exemplary embodiment;

[0132] Fig. 21C A cross-sectional view along the cc' direction after forming an isolation layer provided by an exemplary embodiment;

[0133] Fig.21D A cross-sectional view along the dd' direction after forming an isolation layer provided by an exemplary embodiment;

[0134] Fig.22A A cross-sectional view along the aa' direction after forming the second portion of the word line provided for an exemplary embodiment;

[0135] Fig. 22B A cross-sectional view along the bb' direction after forming the second portion of the word line provided for an exemplary embodiment;

[0136] Fig. 22C A cross-sectional view along the cc' direction after forming the second portion of the word line provided for an exemplary embodiment;

[0137] Fig.22D A cross-sectional view along the dd' direction after forming the second portion of the word line provided for an exemplary embodiment;

[0138] Fig.23A A cross-sectional view along the aa' direction after forming an eighth insulating layer and a ninth insulating layer provided for an exemplary embodiment;

[0139] Fig. 23B A cross-sectional view along the bb' direction after forming an eighth insulating layer and a ninth insulating layer provided by an exemplary embodiment;

[0140] Fig.23C A cross-sectional view along the cc' direction after forming an eighth insulating layer and a ninth insulating layer provided by an exemplary embodiment;

[0141] Fig.23D A cross-sectional view along the dd' direction after forming the eighth insulating layer and the ninth insulating layer is provided for an exemplary embodiment. DETAILED DESCRIPTION

[0142] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0143] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0144] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0145] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0146] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0147] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0148] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0149] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0150] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0151] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0152] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

[0153] In vertical transistors, a Schottky contact is generally formed between the oxide semiconductor source and drain electrodes and the semiconductor layer. At the same time, due to the existence of the Fermi level pinning effect, it is impossible to reduce the contact resistance by heavily doping the semiconductor layer. In addition, if the contact resistance is reduced by increasing the thickness of the source and drain electrodes to increase the electrode contact surface, the interlayer bending stress will increase and bring greater challenges to subsequent processes (larger aspect ratio).

[0154] In the embodiment of the present disclosure, by making the semiconductor layer contact with at least one of the upper surface or the lower surface of the electrode, the contact area between the semiconductor layer and the electrode is increased and the contact resistance is reduced.

[0155] Figure 1A A schematic plan view of a semiconductor device provided as an exemplary embodiment; Figure 1B For along Figure 1A The cross-sectional view along the aa' direction, Figure 1C For along Figure 1A Cross-sectional view along the bb' direction, Figure 1D For along Figure 1A Cross-sectional view along the cc' direction, Figure 1E For along Figure 1A Cross-sectional view along the dd' direction. Figure 1A Only the structure of the active region 300 where the transistor is located is shown, and the capacitor region 200 is not shown. The semiconductor device may be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

[0156] like Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E As shown, the present disclosure provides a semiconductor device, which may include:

[0157] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

[0158] A word line 40, penetrating through the different layers and extending in a direction perpendicular to the substrate 1;

[0159] The transistor includes a first electrode 51, a second electrode 52 and a semiconductor layer 23 surrounding the side wall of the word line 40; the semiconductor layer 23 is connected to the side walls of the first electrode 51 and the second electrode 52, and is connected to at least one of the upper surface and the lower surface of the first electrode 51 or the second electrode 52.

[0160] Among them, the upper surface of the first electrode 51 or the second electrode 52 is the surface facing away from the substrate 1, the lower surface of the first electrode 51 or the second electrode 52 is the surface facing the substrate 1, and the side wall of the first electrode 51 or the second electrode 52 is the surface connected between the upper surface and the lower surface.

[0161] In the solution provided in this embodiment, the semiconductor layer 23 can be connected to the side walls of the first electrode 51 and the second electrode 52, and can also be connected to at least one of the upper surface and the lower surface of the first electrode 51 or the second electrode 52, thereby increasing the contact area and reducing the contact resistance.

[0162] In some embodiments, the semiconductor layer 23 may be connected to the upper surface and the lower surface of the first electrode 51, and the semiconductor layer 23 may be connected to the upper surface and the lower surface of the second electrode 52. In the solution of this embodiment, the semiconductor layer 23 is connected to the upper surface and the lower surface of the first electrode 51 and the second electrode 52, which can increase the contact area as much as possible and further reduce the contact resistance. Here, the semiconductor layer 23 is connected to the upper surface and the lower surface of the first electrode 51 and the second electrode 52, which means that the semiconductor layer 23 is in contact with the upper surface and the lower surface of the first electrode 51 and the second electrode 52.

[0163] In some embodiments, the semiconductor layer 23 may wrap the first end surface of the first electrode 51 facing the word line 40, and the region of the upper surface of the first electrode 51 whose distance from the first end surface is less than or equal to the first preset distance, and the region of the lower surface of the first electrode 51 whose distance from the first end surface is less than or equal to the second preset distance. In this embodiment, the semiconductor layer 23 may wrap the end surface of the first electrode 51 and the upper and lower surfaces adjacent to the end surface, so as to facilitate the formation of the semiconductor layer through a single manufacturing process and simplify the process.

[0164] In some embodiments, the first preset distance may be equal to the second preset distance. However, the first preset distance may not be equal to the second preset distance. When the first preset distance and the second preset distance are equal, the process can be simplified.

[0165] In some embodiments, the semiconductor layer 23 can wrap the second end surface of the second electrode 52 facing the word line 40, as well as an area on the upper surface of the second electrode 52 whose distance from the second end surface is less than or equal to a third preset distance, and an area on the lower surface of the second electrode 52 whose distance from the second end surface is less than or equal to a fourth preset distance.

[0166] In some embodiments, the third preset distance may be equal to the fourth preset distance, but is not limited thereto, and the third preset distance may not be equal to the fourth preset distance. When the third preset distance and the fourth preset distance are equal, the process can be simplified.

[0167] In some embodiments, the semiconductor layers 23 of the transistors may be arranged at intervals, that is, the semiconductor layers 23 of the transistors are physically disconnected from each other, thereby eliminating parasitic MOS transistors between the layers.

[0168] In some embodiments, the semiconductor device may further include a gate electrode 26, and the gate electrode 26 of transistors of different layers may be a part of the word line 40. It is understandable that before and after the word line 40 is formed, there is no need to separately manufacture the gate electrode 26, and after the word line 40 is manufactured, a part of the word line 40 serves as the gate electrode 26.

[0169] In some embodiments, along a direction perpendicular to the substrate 1, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be located in different conductive film layers.

[0170] In some embodiments, the transistor may further include: a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23 , and the gate insulating layer 24 may surround a sidewall of the word line 40 .

[0171] In some embodiments, the semiconductor device may further include:

[0172] A first insulating layer 8, a first sacrificial layer 9, a first conductive layer 10 and a second sacrificial layer 11 are alternately distributed from bottom to top in a direction perpendicular to the substrate 1;

[0173] A through hole K1 is formed through each of the first insulating layers 8, each of the first sacrificial layers 9, each of the first conductive layers 10, and each of the second sacrificial layers 11. The word line 40, a plurality of gate insulating layers 24 surrounding the sidewalls of the word line 40, and a plurality of semiconductor layers 23 surrounding the sidewalls of the gate insulating layers 24 are sequentially distributed in the through hole K1 from the inside to the outside. The solution provided in this embodiment can form the semiconductor layers 23, gate insulating layers 24, and word lines 40 of a plurality of transistors through a single process, thereby simplifying the process.

[0174] In some embodiments, the diameter of the through hole K1 corresponding to the first region of the first conductive layer 10 is larger than the diameter of the through hole K1 corresponding to the second region of the first insulating layer 8; the diameter of the through hole K1 corresponding to the first region of the first conductive layer 10 is smaller than the diameter of the through hole K1 corresponding to the third region of the first sacrificial layer 9; the diameter of the through hole K1 corresponding to the first region of the first conductive layer 10 is smaller than the diameter of the through hole K1 corresponding to the fourth region of the second sacrificial layer 11;

[0175] The first conductive layer 10 exposes part of the sidewall and upper and lower surfaces in the through hole K1, and the first insulating layer 8 exposes part of the sidewall and upper and lower surfaces in the through hole; the first sacrificial layer 9 only exposes the sidewall in the through hole, and the second sacrificial layer 11 only exposes the sidewall in the through hole;

[0176] The semiconductor layer 23 is distributed on the sidewalls of the first conductive layer 10 , and distributed on the entire region of the upper and lower surfaces of the first conductive layer 10 exposed in the through hole K1 .

[0177] In some embodiments, the semiconductor layer 23 is distributed on the sidewall of the first sacrificial layer 9 exposed from the through hole K1 , and is distributed on the sidewall of the second sacrificial layer 11 exposed from the through hole K1 .

[0178] In some embodiments, the semiconductor layer 23 is also distributed on all or part of the upper and lower surfaces of the first insulating layer 8 exposed in the through hole K1 and is not distributed on the sidewall of the first insulating layer 8 .

[0179] In some embodiments, the gate insulating layer 24 is distributed on the surface of each semiconductor layer 23 and is not distributed on the sidewall of the first insulating layer 8 . The gate insulating layers 24 on the surfaces of the semiconductor layers 23 of different layers are spaced apart from each other, that is, physically disconnected.

[0180] In some embodiments, the word line 40 may include a second portion 402 extending along the through hole, and a first portion 401 located on a sidewall of each of the gate insulating layers 24 .

[0181] In some embodiments, the contact area between the semiconductor layer 23 and the first insulating layer 8 is laterally etched to form a recessed area A1 along the lateral direction, and the recessed area A1 is provided with an isolation layer 19 . The isolation layer 19 can be distributed on the surface of the semiconductor layer 23 and the surface of the gate insulating layer 24 .

[0182] In some embodiments, the semiconductor device may be a memory cell array, wherein the memory cell array includes a plurality of memory cells, and the memory cells include transistors. Figure 1A As shown, the transistors in the same layer form a memory cell array distributed along the first direction X and the second direction Y respectively. Each layer may also include: a bit line 30 connected to the second electrode 52 of the transistors in the same column in one layer. Figure 1A It is shown that each layer includes four rows and two columns of storage units, but the embodiments of the present disclosure are not limited thereto. Each layer may include storage units with other numbers of rows and columns, for example, may include only one storage unit.

[0183] In some embodiments, the second electrodes 52 of the transistors of the memory cells of two adjacent columns are connected to the same bit line 30. At this time, the semiconductor layers 23 of the transistors of the memory cells of two adjacent columns are arranged on the upper surface and the lower surface of the same bit line, and the second sacrificial layer 11 arranged on the upper surface of the bit line 30 and the first layer 9 arranged on the lower surface of the bit line 30 are arranged between the semiconductor layers 23 of the transistors of the memory cells of two adjacent columns, that is, the semiconductor layers 23 of the transistors of the memory cells of two adjacent columns are spaced apart from each other by the first sacrificial layer 9, and spaced apart from each other by the second sacrificial layer 11.

[0184] In some embodiments, the second electrode 52 of the transistor may be a part of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular. The branch may be a plurality of branches on one sidewall of the bit line, or a plurality of branches on both sidewalls at the same time, and each branch will form a transistor or a storage unit.

[0185] In some embodiments, the bit lines 30 may extend along the second direction Y.

[0186] In some embodiments, the first electrode 51 may extend along a first direction X.

[0187] The stacked transistor can be applied in multiple memory scenarios, such as the traditional 1T structure, 2T structure, structure with capacitor or structure without capacitor in DRAM scenario, or can be applied in 4T or 6T memory cell scenario in SRAM.

[0188] In some embodiments, the first electrode 51 may include a first end face facing the word line 40 and a second end face away from the word line 40, as well as a side surface connecting the first end face and the second end face. The semiconductor device may also include a capacitor, the capacitor including a first pole 41 and a second pole 42, the first electrode 51 may serve as the first pole 41 of the capacitor, and the second pole 42 surrounds the side surface of the first electrode 51.

[0189] In some embodiments, the capacitor may further include: a dielectric layer 43 disposed between the first electrode 41 and the second electrode 42. The dielectric layer 43 surrounds the side surface of the first electrode 51. The dielectric layer 43 is connected to the first sacrificial layer 9 and the second sacrificial layer 11. Figure 1B As shown, one end surface of the first sacrificial layer 9 is connected to the dielectric layer 43, and the other end surface is connected to the semiconductor layer 23. The second sacrificial layer 11 is similar, with one end surface of the second sacrificial layer 11 connected to the dielectric layer 43, and the other end surface connected to the semiconductor layer 23.

[0190] In some embodiments, the semiconductor device may further include: a support layer 45 extending in a direction perpendicular to the substrate 1, the support layer 45 wrapping the second end surface of each first electrode 51, and wrapping the area of ​​the side surface of the first electrode 51 close to the second end surface. The support layer 45 forms a plate-shaped film layer extending in a direction perpendicular to the substrate 1, which can be formed before manufacturing the capacitor to provide support for the subsequent manufacturing process of forming the capacitor. The support layer 45 wraps part of the side surface of the first electrode 51, which can enhance the support performance of the support layer 45.

[0191] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0192] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0193] 1) A first insulating film, a first sacrificial layer film, a first conductive film, and a second sacrificial layer film are sequentially deposited on a substrate 1 to form a plurality of stacked structures, each stacked structure comprising a first insulating layer 8, a first sacrificial layer 9, a first conductive layer 10, and a second sacrificial layer 11 arranged sequentially, such as FIG. 2A to FIG. 2D As shown, Figure 2A is the cross-sectional view along the aa' direction, Figure 2B is the cross-sectional view along the bb' direction, Figure 2C is the cross-sectional view along the cc' direction, Figure 2D It is a cross-sectional view along the dd' direction.

[0194] The orthographic projections of the first insulating layer 8 , the first sacrificial layer 9 , the first conductive layer 10 , and the second sacrificial layer 11 in a direction parallel to the substrate 1 overlap.

[0195] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer with a dielectric constant K<3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0196] In some embodiments, the first sacrificial layer film and the second sacrificial layer film may be a low-K dielectric layer and a high-K dielectric layer, and insulating materials with low stress between the first conductive film and easy etching may be selected, including but not limited to ALOx.

[0197] In some embodiments, the first conductive film may be a conductive material as follows:

[0198] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0199] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0200] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0201] FIG. 2A to FIG. 2D The stacked structure shown in the figure includes four first insulating layers 8, three first sacrificial layers 9, three first conductive layers 10 and three second sacrificial layers 11, which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0202] 2) patterning the stacked structure so that each of the first conductive layers 10 forms a preset electrode pattern;

[0203] The patterning of the stacked structure may include:

[0204] Depositing a second insulating film to form a second insulating layer 13;

[0205] The stacked structure is etched from the top layer to the bottom layer using a dry etching method to form a plurality of first grooves, wherein the plurality of first grooves enable the first conductive layer 10 to form a preset electrode pattern, wherein the preset electrode pattern may include a first conductive portion 121 and a second conductive portion 122, wherein the first conductive portion 121 may extend along a first direction X, and the second conductive portion 122 may extend along a second direction Y, such as Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, Figure 3A is the cross-sectional view along the aa' direction, Figure 3B is the cross-sectional view along the bb' direction, Figure 3C is the cross-sectional view along the cc' direction, Figure 3D is the cross-sectional view along the dd' direction, Figure 3ESchematic diagram of a preset electrode pattern of the first conductive layer 10. The preset electrode pattern and the pattern of the plurality of first grooves are complementary, that is, the pattern of the preset electrode pattern and the pattern of the first grooves are combined to form the shape of the first conductive layer 10 in step 1).

[0206] The first conductive portion 121 may subsequently form a first electrode 51 of a transistor, and the second conductive portion 122 may form a second electrode 52 of a transistor, and further, form a bit line 30 .

[0207] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive portion 122 may form the bit line 30 .

[0208] Figure 3E The preset electrode pattern shown is only an example, and the preset electrode pattern may be other shapes.

[0209] The second insulating film may be an insulating film layer different from the first insulating film, including but not limited to silicon nitride (SiN).

[0210] 3) forming a third insulating layer 14;

[0211] The forming of the third insulating layer 14 may include:

[0212] Depositing a third insulating film on the substrate having the aforementioned structure by ALD to form a first insulating sublayer;

[0213] The third insulating film filling the plurality of first grooves is coated by SOD method, and annealed to form a second insulating sublayer; the annealing treatment can make the coated third insulating film dense; the second insulating sublayer and the first insulating sublayer constitute the third insulating layer 14;

[0214] The third insulating layer 14 is ground flat so that the third insulating layer 14 is flush with the second insulating layer 13, and the third insulating layer 14 fills the first groove formed in step 2. Figure 4A , Figure 4B , Figure 4C and Figure 4D As shown, Figure 4A is the cross-sectional view along the aa' direction, Figure 4B is the cross-sectional view along the bb' direction, Figure 4C is the cross-sectional view along the cc' direction, Figure 4D It is a cross-sectional view along the dd' direction.

[0215] The above method of forming the third insulating layer 14 is only an example, and the third insulating layer 14 may be formed by other methods as long as it can fill the first trench.

[0216] The material of the second insulating film is different from that of the third insulating film, so that the second insulating layer 13 can be used as a stop layer when the third insulating layer 14 is ground flat.

[0217] The third insulating film and the first insulating film may be made of the same material or different materials, and both may be Low-K materials. In some embodiments, the third insulating film includes but is not limited to silicon oxide, such as silicon dioxide (SiO2).

[0218] 4) forming a second trench;

[0219] The forming of the second trench may include:

[0220] After forming the third insulating layer 14, dry etching is performed from the top layer to the bottom layer of the stacked structure to form a second groove to expose the end surface of the first conductive portion 121 away from the second conductive portion 122;

[0221] The first insulating layer 8, the first sacrificial layer 9, and the second sacrificial layer 11 exposed in the second trench are laterally etched in the second trench by a first preset length to expose a side surface whose distance from the end surface of the first conductive portion 121 is less than or equal to the first preset length, that is, the end surface of the first conductive portion 121 and the side surface adjacent to the end surface and whose distance is less than or equal to the first preset length are exposed. Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown, Figure 5A is the cross-sectional view along the aa' direction, Figure 5B is the cross-sectional view along the bb' direction, Figure 5C is the cross-sectional view along the cc' direction, Figure 5D The purpose of the lateral etching is to enhance the supporting performance of the supporting layer 45 formed subsequently.

[0222] In some embodiments, the lateral etching may be performed using vapor phase etching.

[0223] In some embodiments, the ratio of the first preset length to the length of the first conductive layer 10 along the aa′ direction may be less than or equal to 5%.

[0224] 5) forming a support layer 45;

[0225] The forming of the support layer 45 may include: depositing a support layer film in the second groove to form the support layer 45, wherein the support layer 45 fills the second groove and wraps the exposed end surface and side wall of the first conductive portion 121;

[0226] The support layer 45 is ground flat so that the support layer 45 is flush with the topmost first insulating layer 8. Fig. 6A , Figure 6B , Figure 6C and Fig.6D As shown, Fig. 6A is the cross-sectional view along the aa' direction, Figure 6B is the cross-sectional view along the bb' direction, Figure 6C is the cross-sectional view along the cc' direction, Fig.6D It is a cross-sectional view along the dd' direction. When the support layer 45 is polished flat, the second insulating layer 13 is removed.

[0227] In an exemplary embodiment, the support layer film may be made of the same material as the second insulating film.

[0228] 6) forming a fourth insulating layer 15 and a first hard mask layer 61;

[0229] The forming of the fourth insulating layer 15 and the first hard mask layer 61 may include:

[0230] Depositing a fourth insulating film on the substrate 1 forming the above structure to form a fourth insulating layer 15; for example, the fourth insulating film may be deposited by ALD;

[0231] Deposit a first hard mask film to form a first hard mask layer 61, such as Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, Fig. 7A is the cross-sectional view along the aa' direction, Figure 7B is the cross-sectional view along the bb' direction, Figure 7C is the cross-sectional view along the cc' direction, Fig.7D For example, the first hard mask film may be deposited by low pressure chemical vapor deposition (LPCVD).

[0232] In some embodiments, the fourth insulating film may be an insulating film layer different from the first insulating film, such as including but not limited to SiN.

[0233] In some embodiments, the first hard mask layer 61 may include, for example, but not limited to, polysilicon.

[0234] 7) forming a third trench;

[0235] The forming of the third trench may include:

[0236] The third insulating layer 14 located in the capacitor region 200 is removed by dry etching from the top layer (here, the first hard mask layer 61) of the stacked structure to the bottom layer to form a third trench. At this time, there is no third insulating layer 14 between the first conductive portions 121 of the same layer located in the capacitor region 200. Fig. 8A , Figure 8B , Figure 8C and Fig.8D As shown, Fig. 8A is the cross-sectional view along the aa' direction, Figure 8B is the cross-sectional view along the bb' direction, Figure 8C is the cross-sectional view along the cc' direction, Fig.8D It is a cross-sectional view along the dd' direction.

[0237] 8) exposing the first sacrificial layer 9 and the second sacrificial layer 11 located in the capacitor region 200;

[0238] The exposing of the first sacrificial layer 9 and the second sacrificial layer 11 located in the capacitor region 200 may include:

[0239] The sidewall of the third trench close to the second conductive portion 122 is laterally etched by a preset distance to form a groove relative to the fourth insulating layer 15. When the first insulating layer 8 is subsequently removed by wet etching, the groove structure is more conducive to etching;

[0240] The first insulating layer 8 located in the capacitor region 200 and between the first conductive portion 121 of the adjacent layer, as well as the first insulating layer 8 located in the capacitor region 200 and between the first conductive portion 121 and the substrate 1, and the first insulating layer 8 located in the capacitor region 200 and between the first conductive portion 121 and the fourth insulating layer 15 are removed by wet etching to expose the lower surface (the surface close to the substrate 1 side) of the first sacrificial layer 9 located in the capacitor region 200 and the upper surface (the surface away from the substrate 1 side) of the second sacrificial layer 11, so as to subsequently remove the first sacrificial layer 9 and the second sacrificial layer 11 located in the capacitor region 200, as shown in FIG. Fig. 9A , Figure 9B' , Fig. 9C and Fig.9D As shown, Fig. 9A is the cross-sectional view along the aa' direction, Figure 9B' is the cross-sectional view along the bb' direction, Fig. 9C is the cross-sectional view along the cc' direction, Fig.9D It is a cross-sectional view along the dd' direction.

[0241] In other embodiments, the sidewall of the third trench close to the second conductive portion 122 may not be laterally etched by a preset distance, and the first insulating layer 8 located in the capacitor region 200 and between the first conductive portions 121 of adjacent layers may be directly removed by wet etching. Fig. 9A , Fig. 9B , Fig. 9C and Fig.9D As shown, in the subsequent embodiments, description is made by taking an example that the sidewall of the third trench close to the second conductive portion 122 is not laterally etched by a preset distance.

[0242] 9) exposing the first conductive portion 121 located in the capacitor region 200;

[0243] The exposing the first conductive portion 121 located in the capacitor region 200 may include: removing the first sacrificial layer 9 and the second sacrificial layer 11 located in the capacitor region 200 by wet lateral etching, exposing the first conductive portion 121 located in the capacitor region 200 and covered by the first sacrificial layer 9 and the second sacrificial layer 11, such as Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D As shown, Fig. 10A is the cross-sectional view along the aa' direction, Fig. 10B is the cross-sectional view along the bb' direction, Fig. 10C is the cross-sectional view along the cc' direction, Fig. 10D The exposed portion of the first conductive portion 121 can be used as the first electrode 41 of the capacitor, and subsequently a dielectric layer 43 and a second electrode 42 can be formed in sequence on the exposed region of the first electrode 41 to complete the manufacturing of the capacitor.

[0244] 10) Etching and removing the first hard mask layer 61, such as Fig.11A , Fig. 11B , Fig. 11C and Fig.11D As shown, Fig.11A is the cross-sectional view along the aa' direction, Fig. 11B is the cross-sectional view along the bb' direction, Fig. 11C is the cross-sectional view along the cc' direction, Fig.11D It is a cross-sectional view along the dd' direction.

[0245] In some embodiments, the first hard mask layer 61 may be removed by wet etching.

[0246] 11) forming a dielectric layer 43, a second electrode 42, a second conductive layer 7, and a fifth insulating layer 16;

[0247] The forming of the dielectric layer 43, the second electrode 42, the second conductive layer 7 and the fifth insulating layer 16 may include:

[0248] A dielectric film and a conductor material are sequentially deposited on the substrate 1 forming the above structure to form a dielectric layer 43 and a second electrode 42 respectively, wherein the dielectric layer 43 covers the exposed area of ​​the conductive layer 12;

[0249] A second conductive film is deposited to form a second conductive layer 7 covering the second electrode 42 and filling the third groove; the second conductive layer 7 is connected to the second electrode 42, and the second conductive layer 7 can be grounded, thereby realizing capacitor grounding.

[0250] The second conductive layer 7 is ground flat, and a fifth insulating film is deposited to form a fifth insulating layer 16, wherein the fifth insulating layer 16 covers the second conductive layer 7. Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D As shown, Fig. 12A is the cross-sectional view along the aa' direction, Fig. 12B is the cross-sectional view along the bb' direction, Fig. 12C is the cross-sectional view along the cc' direction, Fig.12D The fifth insulating layer 16 can be used as a stop layer for subsequently grinding the sixth insulating layer 17 flat.

[0251] The dielectric layer 43 serves as a dielectric between the capacitor electrodes, and the second electrode 42 serves as an electrode of the capacitor.

[0252] In some embodiments, the dielectric film and the conductor material may be deposited by atomic layer deposition (ALD).

[0253] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0254] In some embodiments, the conductor material includes but is not limited to at least one of the following or a combination thereof:

[0255] Metals or alloys, for example, metals containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc., and metal alloys containing the aforementioned metals;

[0256] Alternatively, it can be a metal oxide, metal nitride, metal silicide, metal carbide, etc., such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (Al-doped ZnO, AZO), iridium oxide (IrOx), ruthenium oxide (RuOx) and other metal oxide conductive materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN) and other metal nitride materials.

[0257] In some embodiments, the second conductive film includes but is not limited to metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as Poly-GiSe, etc.

[0258] In some embodiments, the fifth insulating film includes but is not limited to SiN.

[0259] The second pole 42 may surround the side wall of the first conductive portion 121 , and the second pole 42 is insulated from the first conductive portion 121 by the dielectric layer 43 .

[0260] 12) forming a fourth groove;

[0261] The forming of the fourth trench may include: using dry etching to sequentially etch away the fifth insulating layer 16, the second conductive layer 7, the second electrode 42, the dielectric layer 43 and the fourth insulating layer 15 starting from the fifth insulating layer 16 in the active area 300 to form a fourth trench, such as Fig.13A , Fig. 13B , Fig. 13C and Fig.13D As shown, Fig.13A is the cross-sectional view along the aa' direction, Fig. 13B is the cross-sectional view along the bb' direction, Fig. 13C is the cross-sectional view along the cc' direction, Fig.13D The substrate may include a capacitor region 200 and an active region 300, and a transistor is subsequently formed in the active region 300. Since a word line 40, a gate electrode 26, etc. are to be formed in this region later, the second conductive layer 7 and the second electrode 42 in this region are removed by forming the fourth trench to avoid affecting the transistor.

[0262] 13) forming a sixth insulating layer 17;

[0263] The forming of the sixth insulating layer 17 may include: depositing a sixth insulating film on the substrate formed with the above structure and grinding it flat to form the sixth insulating layer 17 filling the fourth trench; the sixth insulating layer 17 is flush with the fifth insulating layer 16, such as Fig.14A , Fig. 14B , Fig. 14C and Fig.14D As shown, Fig.14A is the cross-sectional view along the aa' direction, Fig. 14B is the cross-sectional view along the bb' direction, Fig. 14C is the cross-sectional view along the cc' direction, Fig.14D It is a cross-sectional view along the dd' direction.

[0264] In some embodiments, the sixth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0265] 14) forming a seventh insulating layer 18 and an initial through hole K0;

[0266] The forming of the seventh insulating layer 18 and the initial through hole K0 may include:

[0267] A seventh insulating film is deposited on the substrate having the above structure to form a seventh insulating layer 18 , and the seventh insulating layer 18 covers the fifth insulating layer 16 and the sixth insulating layer 17 ; the seventh insulating layer 18 serves as a stop layer when the word line 40 is subsequently polished.

[0268] The stacked structure is etched by dry etching to form a plurality of initial through holes K0 penetrating the stacked structure, wherein the side walls of the initial through holes K0 expose each of the first conductive layers 10, and the apertures of the initial through holes K0 in different layers are substantially consistent, and the initial through holes K0 do not disconnect the first conductive layer 10, and all regions of the first conductive layer 10 remain connected, such as Fig.15A , Fig. 15B , Fig. 15C and Fig.15D As shown, Fig.15A is the cross-sectional view along the aa' direction, Fig. 15B is the cross-sectional view along the bb' direction, Fig. 15C is the cross-sectional view along the cc' direction, Fig.15D It is a cross-sectional view along the dd' direction.

[0269] The initial through hole K0 may extend in a direction perpendicular to the substrate 1 . The initial through hole K0 includes a second initial sub-hole K12 located in the first conductive layer 10 and a first sub-hole K11 located in the first insulating layer 8 , the first sacrificial layer 9 and the second sacrificial layer 11 .

[0270] In some embodiments, the orthographic projection of the initial through hole K0 on a plane parallel to the substrate 1 may be a circle or an ellipse, but is not limited thereto, and may be a square, a hexagon, or the like.

[0271] In some embodiments, the seventh insulating film includes but is not limited to SiN.

[0272] 15) Laterally etching the first conductive layer 10;

[0273] The lateral etching of the first conductive layer 10 may include: etching the first conductive layer 10 in a direction away from the initial through hole K0, which may be understood as lateral etching, so as to expand the second initial sub-hole K12 of the initial through hole K0 located in the first conductive layer 10 in a direction away from the initial through hole K0 to form a second sub-hole K12', and the first insulating layer 8, the first sacrificial layer 9 and the second sacrificial layer 11 are hardly affected by the etching, so that on a plane parallel to the substrate 1, the orthographic projection of the first sub-hole K11 located in the first insulating layer 8, the first sacrificial layer 9 and the second sacrificial layer 11 falls within the orthographic projection of the second sub-hole K12' located in the first conductive layer 10, and so that the first conductive layer 10 forms a first electrode 51 and a second electrode 52 separated from each other; Fig.16A , Fig. 16B , Fig. 16C and Fig.16D As shown, Fig.16A is the cross-sectional view along the aa' direction, Fig. 16B is the cross-sectional view along the bb' direction, Fig. 16C is the cross-sectional view along the cc' direction, Fig.16D It is a cross-sectional view along the dd' direction.

[0274] A plurality of the first sub-holes K11 and a plurality of the second sub-holes K12' constitute a through hole K1, and the through hole K1 forms a plurality of dumbbell-shaped structures, such as forming a plurality of two types of holes with different aperture sizes. The aperture of the second sub-hole K12' located in the first conductive layer 10 is larger than the aperture of the first sub-hole K11 located in the first insulating layer 8, the first sacrificial layer 9, and the second sacrificial layer 11.

[0275] In some embodiments, wet etching can be used to select an acid solution with a high etching selectivity ratio for the first insulating layer 8, the first sacrificial layer 9, and the second sacrificial layer 11 to the first conductive layer 10, and the first conductive layer 10 is laterally etched to a first preset thickness L1 in a direction away from the initial through hole K0. Due to the high etching selectivity, the first insulating layer 8, the first sacrificial layer 9, and the second sacrificial layer 11 are almost not etched.

[0276] 16) Laterally etching the first sacrificial layer 9 and the second sacrificial layer 11;

[0277] The lateral etching of the first sacrificial layer 9 and the second sacrificial layer 11 may include: etching the first sacrificial layer 9 and the second sacrificial layer 11 in a direction away from the through hole K1, which can be understood as lateral etching, etching the first sacrificial layer 9 in a direction away from the through hole K1 by a second preset thickness L2, and etching the second sacrificial layer 11 in a direction away from the through hole K1 by a third preset thickness L3, wherein the second preset thickness L2 is greater than the first preset thickness L1, and the third preset thickness L3 is greater than the first preset thickness L1; and retaining a portion of the first sacrificial layer 9 and the second sacrificial layer 11 between adjacent through holes K1, that is, avoiding communication between adjacent through holes K1, resulting in connection of semiconductor layers formed in subsequent adjacent through holes K1, such as Fig.17A , Fig. 17B , Fig. 17C and Fig.17D As shown, Fig.17A is the cross-sectional view along the aa' direction, Fig. 17B is the cross-sectional view along the bb' direction, Fig. 17C is the cross-sectional view along the cc' direction, Fig.17D In addition, when the first sacrificial layer 9 and the second sacrificial layer 11 are laterally etched, a portion of the first sacrificial layer 9 and the second sacrificial layer 11 is retained, and the dielectric layer 43 is not exposed, so as to avoid the subsequent semiconductor layer being connected to the dielectric layer 43 .

[0278] In the present embodiment, by etching the first sacrificial layer 9 and the second sacrificial layer 11, compared with the scheme without setting the first sacrificial layer 9 and the second sacrificial layer 11, the contact surface between the subsequently deposited semiconductor layer and the first electrode 51 and the second electrode 52 may include not only the side walls perpendicular to the direction of the substrate 1, but also the upper and lower surfaces parallel to the direction of the substrate 1, thereby increasing the contact surface between the semiconductor layer and the first electrode 51 and the second electrode 52.

[0279] In some embodiments, the second preset thickness L2 may be equal to the third preset thickness L3, but is not limited thereto, and the second preset thickness L2 and the third preset thickness L3 may not be equal.

[0280] 17) forming a semiconductor layer 23, a gate insulating layer 24 and a protective layer 25;

[0281] The forming of the semiconductor layer 23, the gate insulating layer 24 and the protective layer 25 may include:

[0282] A semiconductor film and a gate insulating film are sequentially deposited on the side wall of the through hole K1 to form a semiconductor layer 23 and a gate insulating layer 24;

[0283] A protective layer film is deposited on the through hole K1 to form a protective layer 25, such as Fig.18A , Fig.18B , Fig.18C and Fig.18D As shown, Fig.18A is the cross-sectional view along the aa' direction, Fig.18B is the cross-sectional view along the bb' direction, Fig.18C is the cross-sectional view along the cc' direction, Fig.18D The protection layer 25 is used as a protection layer for the semiconductor layer 23 on the side wall of the through hole K1 in the first conductive layer 10 when the semiconductor layer 23 and the gate insulating layer 24 on the side wall of the through hole K1 in the first insulating layer 8 and the seventh insulating layer 18 are subsequently etched.

[0284] In an exemplary embodiment, the material of the protective layer film may be a conductive material, for example, consistent with the material of the subsequent gate electrode film, so that after etching away the semiconductor layer 23 and the gate insulating layer 24 on the side walls of the through hole K1 of the first insulating layer 8 and the seventh insulating layer 18, the protective layer 25 does not need to be removed before depositing the gate electrode film, and the gate electrode film can be directly deposited, and the protective layer 25 and the deposited gate electrode film together serve as the gate electrode of the final device. However, the embodiments of the present disclosure are not limited thereto, and the material of the protective layer film may be inconsistent with the gate electrode film.

[0285] In an exemplary embodiment, the semiconductor film, the gate insulating film and the protective layer film may be deposited by ALD.

[0286] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 2 eV.

[0287] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0288] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0289] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0290] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0291] In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0292] In an exemplary embodiment, the protective layer film may be one or more of the following different types of materials:

[0293] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0294] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0295] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0296] 18) The protection layer 25 distributed on the side walls of the through hole K1 located in the first insulating layer 8 , the sixth insulating layer 17 , and the seventh insulating layer 18 is removed.

[0297] The method of removing the protective layer 25 distributed on the sidewalls of the through hole K1 located in the first insulating layer 8, the sixth insulating layer 17, and the seventh insulating layer 18 may include: removing the protective layer 25 distributed on the sidewalls of the through hole K1 located in the first insulating layer 8, the sixth insulating layer 17, and the seventh insulating layer 18, and the protective layer 25 located on the surface of the gate insulating layer 23 away from the substrate by wet etching. At this time, the protective layer 25 is only distributed on the sidewalls of the through hole K1 located in the first conductive layer 10, such as Fig.19A , Fig.19B , Fig.19C and Fig.19D As shown, Fig.19A is the cross-sectional view along the aa' direction, Fig.19B is the cross-sectional view along the bb' direction, Fig.19C is the cross-sectional view along the cc' direction, Fig.19D It is a cross-sectional view along the dd' direction.

[0298] 19) The semiconductor layer 23 and the gate insulating layer 24 distributed on the side walls of the through hole K1 located in the first insulating layer 8 , the sixth insulating layer 17 , and the seventh insulating layer 18 are removed.

[0299] Removing the semiconductor layer 23 and the gate insulating layer 24 distributed on the side walls of the through hole K1 located in the first insulating layer 8, the sixth insulating layer 17, and the seventh insulating layer 18 may include: removing the semiconductor layer 23 and the gate insulating layer 24 distributed on the side walls of the through hole K1 located in the first insulating layer 8, the sixth insulating layer 17, and the seventh insulating layer 18 by wet etching, at this time, the side walls of the through hole K1 located in the first insulating layer 8, the sixth insulating layer 17, and the seventh insulating layer 18 have no semiconductor layer 23 and the gate insulating layer 24, and the semiconductor layer 23 and the gate insulating layer 24 on the side walls of the through hole K1 located in the first conductive layer 10 are partially etched away, forming a lateral recessed area A1, as shown in FIG. Fig. 20A , Fig. 20B , Fig. 20C and Fig.20D As shown, Fig. 20A is the cross-sectional view along the aa' direction, Fig. 20B is the cross-sectional view along the bb' direction, Fig. 20C is the cross-sectional view along the cc' direction, Fig.20D is a cross-sectional view along the dd' direction. Part of the protection layer 25 is etched away during the process, and part of the protection layer 25 is still retained to cover the gate insulating layer 24, and the retained protection layer 25 serves as the first part 401 of the word line 40. In this embodiment, the semiconductor layer 23 between the layers is removed, so that the parasitic MOS tube between the layers can be eliminated and the stability of the device can be improved.

[0300] 20) forming an isolation layer 19;

[0301] The forming of the isolation layer 19 may include: depositing an isolation layer film on the through hole K1 to form the isolation layer 19, wherein the isolation layer 19 fills the recessed area A1 to avoid exposing the semiconductor layer 23;

[0302] The isolation layer 19 covering the side of the protective layer 25 facing the through hole K1 is removed by etching. The protective layer 25 and the gate electrode film deposited subsequently serve as the gate electrode. Therefore, the isolation layer 19 covering the surface of the protective layer 25 is removed to avoid affecting the resistance of the gate electrode. Fig.21A , Fig. 21B , Fig. 21C and Fig.21D As shown, Fig.21A is the cross-sectional view along the aa' direction, Fig. 21B is the cross-sectional view along the bb' direction, Fig. 21C is the cross-sectional view along the cc' direction, Fig.21D is a cross-sectional view along the dd' direction. The isolation layer 19 can be removed by dry etching. In this embodiment, the isolation layer 19 can isolate the semiconductor layer 23 and the gate electrode 26 deposited subsequently.

[0303] In an exemplary embodiment, the isolation layer film may be deposited by ALD.

[0304] In an exemplary embodiment, the isolation layer film may include but is not limited to silicon oxide, such as SiO2.

[0305] 21) The second portion 402 of the word line 40 is formed.

[0306] Forming the second portion 402 of the word line 40 may include: depositing a gate electrode film in the through hole K1, and grinding to form the second portion 402 of the word line 40, such as Fig.22A , Fig. 22B , Fig. 22C and Fig.22D As shown, Fig.22A is the cross-sectional view along the aa' direction, Fig. 22B is the cross-sectional view along the bb' direction, Fig. 22C is the cross-sectional view along the cc' direction, Fig.22D is a cross-sectional view along the dd' direction. The second portion 402 of the word line 40 fills the through hole K1. The seventh insulating layer 18 is used as a stop layer during grinding, that is, the surface of the second portion 402 of the word line 40 away from the substrate 1 is flush with the surface of the seventh insulating layer 18 away from the substrate 1. The second portion 402 of the word line 40 and the first portion 401 of the word line 40 (that is, the previously retained holding layer 25) together form the word line 40.

[0307] In one exemplary embodiment, the gate electrode thin film may be deposited by ALD.

[0308] In an exemplary embodiment, the gate electrode film may be one or more of the following different types of materials:

[0309] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0310] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0311] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0312] 22) An eighth insulating layer 20 and a ninth insulating layer 21 are formed.

[0313] The forming of the eighth insulating layer 20 and the ninth insulating layer 21 may include: depositing an eighth insulating film and a ninth insulating film in sequence on the substrate having the aforementioned structure to form the eighth insulating layer 20 and the ninth insulating layer 21, such as Fig.23A , Fig. 23B , Fig.23C and Fig.23D As shown, Fig.23A is the cross-sectional view along the aa' direction, Fig. 23B is the cross-sectional view along the bb' direction, Fig.23C is the cross-sectional view along the cc' direction, Fig.23D It is a cross-sectional view along the dd' direction.

[0314] In some embodiments, the ninth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0315] In some embodiments, the eighth insulating layer 20 may be used as a stop layer for subsequent operations, and the eighth insulating film may be an insulating film layer different from the ninth insulating film, such as including but not limited to SiN.

[0316] The solution provided in this embodiment increases the contact area between the semiconductor layer 23 and the first electrode 51 and the second electrode 52, reduces the contact resistance between the semiconductor layer 23 and the first electrode 51 and the second electrode 52, and can also remove parasitic MOS tubes to increase device stability.

[0317] In another exemplary embodiment, a sacrificial layer may be formed only on one side of the first conductive layer 10, that is, only a first sacrificial layer 9 or a second sacrificial layer 11 may be formed. In this embodiment, the semiconductor layer 23 is connected to the upper surface or the lower surface of the first electrode 51 and the second electrode 52. Compared with a solution in which the semiconductor layer only contacts the side walls of the first electrode 51 and the second electrode 52, the solution of this embodiment also increases the contact area and can still reduce the contact resistance.

[0318] The present disclosure also provides an electronic device, including the semiconductor device of the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0319] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, and a word line extending along a direction perpendicular to the substrate through the different layers, wherein the transistor comprises a first electrode and a second electrode, and the method for manufacturing the semiconductor device comprises:

[0320] A substrate is provided, and a plurality of stacked structures are formed on the substrate; each of the stacked structures comprises a stack of a first insulating layer and a first conductive layer, the first insulating layer is arranged on a side of the first conductive layer facing the substrate, the stacked structure further comprises a sacrificial layer, the sacrificial layer comprises at least one of the following: a first sacrificial layer arranged on a side of the first conductive layer facing the first insulating layer, and a second sacrificial layer arranged on a side of the first conductive layer away from the first insulating layer; the first conductive layer comprises a preset electrode pattern, the preset electrode pattern comprises a first electrode and a second electrode of the transistor to be formed;

[0321] Etching the stacked structure to form a through hole penetrating the plurality of stacked structures in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes each of the first conductive layers, and laterally etching the first conductive layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first insulating layer falls within the orthographic projection of the through hole located in the first conductive layer, and laterally etching the sacrificial layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first conductive layer falls within the orthographic projection of the through hole located in the sacrificial layer, and the through hole disconnects the first electrode and the second electrode in the preset electrode pattern;

[0322] Depositing a semiconductor film and a gate insulating film in the through hole in sequence to form a multi-layer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode, and the semiconductor layer is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode;

[0323] A word line is formed in the through hole.

[0324] The manufacturing method of the semiconductor device provided in this embodiment sets a sacrificial layer on at least one of the upper and lower surfaces of the first conductive layer and removes it, so that the semiconductor layer can contact at least one of the upper and lower surfaces of the first conductive layer, thereby increasing the contact area between the semiconductor layer and the first conductive layer and reducing the contact resistance.

[0325] In some embodiments, forming a word line in the through hole may include:

[0326] Depositing a protective layer film in the through hole to form a protective layer, wherein the protective layer film is a conductive film;

[0327] Etching the protective layer in the through hole so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and the side wall of the through hole located in the first conductive layer exposes the protective layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer;

[0328] A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.

[0329] In some embodiments, etching the protective layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the gate insulating layer, and the sidewall of the through hole located in the first conductive layer exposes the protective layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole located in the first insulating layer comprises:

[0330] Etching the protective layer in the through hole by wet etching, so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and a portion of the protective layer is retained in the through hole located in the first insulating layer;

[0331] The semiconductor layer and the gate insulating layer located in the through hole of the first insulating layer are removed by wet etching.

[0332] In some embodiments, after the etching removes the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer and before depositing a gate electrode film in the through hole, the method may further include:

[0333] Depositing a gate insulating film in the through hole to form an isolation layer;

[0334] The isolation layer covering the side of the protection layer facing the through hole is removed by etching.

[0335] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, extending through the different layers in a direction perpendicular to the substrate; The transistor includes a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer is connected to the sidewalls of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode or the second electrode.

2. The semiconductor device according to claim 1, wherein: The semiconductor layer is connected to the upper surface and the lower surface of the first electrode, and the semiconductor layer is connected to the upper surface and the lower surface of the second electrode.

3. The semiconductor device according to claim 1, wherein: The semiconductor layer wraps the first end face of the first electrode facing the word line, a region of the upper surface of the first electrode whose distance from the first end face is less than or equal to a first preset distance, and a region of the lower surface of the first electrode whose distance from the first end face is less than or equal to a second preset distance.

4. The semiconductor device according to claim 1, wherein: The semiconductor layer wraps the second end face of the second electrode facing the word line, a region of the upper surface of the second electrode whose distance from the second end face is less than or equal to a third preset distance, and a region of the lower surface of the second electrode whose distance from the second end face is less than or equal to a fourth preset distance.

5. The semiconductor device according to claim 1, wherein: The plurality of semiconductor layers of the plurality of transistors are arranged at intervals.

6. The semiconductor device according to claim 1, wherein: The transistor further comprises a gate insulating layer; The semiconductor device further comprises: A first insulating layer, a first sacrificial layer, a first conductive layer, and a second sacrificial layer are alternately distributed from bottom to top in a direction vertical to the substrate; A through hole is formed through each of the first insulating layers, each of the first sacrificial layers, each of the first conductive layers, and each of the second sacrificial layers, wherein the word line, a plurality of gate insulating layers surrounding the side walls of the word line, and a plurality of semiconductor layers surrounding the side walls of the gate insulating layers are sequentially distributed in the through hole from the inside to the outside.

7. The semiconductor device according to claim 6, characterized in that The diameter of the through hole corresponding to the first region of the first conductive layer is larger than the diameter of the through hole corresponding to the second region of the first insulating layer; the diameter of the through hole corresponding to the first region of the first conductive layer is smaller than the diameter of the through hole corresponding to the third region of the first sacrificial layer; the diameter of the through hole corresponding to the first region of the first conductive layer is smaller than the diameter of the through hole corresponding to the fourth region of the second sacrificial layer; The first conductive layer exposes part of the sidewall and upper and lower surfaces in the through hole, and the first insulating layer exposes part of the sidewall and upper and lower surfaces in the through hole; the first sacrificial layer only exposes the sidewall in the through hole, and the second sacrificial layer only exposes the sidewall in the through hole; The semiconductor layer is distributed on the sidewall of the first conductive layer, and is distributed on the entire region of the upper and lower surfaces of the first conductive layer exposed in the through hole.

8. The semiconductor device according to claim 7, characterized in that The semiconductor layer is also distributed on all or part of the upper and lower surfaces of the first insulating layer exposed in the through hole and is not distributed on the sidewall of the first insulating layer.

9. The semiconductor device according to claim 7, characterized in that The gate insulating layer is distributed on the surface of each semiconductor layer and is not distributed on the side wall of the first insulating layer. The gate insulating layers on the surfaces of the semiconductor layers of different layers are spaced apart from each other.

10. The semiconductor device according to claim 9, characterized in that The word line includes a second portion extending along the through hole, and a first portion located at a sidewall of each gate insulating layer.

11. The semiconductor device according to claim 7, wherein: The contact area between the semiconductor layer and the first insulating layer is laterally etched to form a recessed area along the lateral direction. The recessed area is provided with an isolation layer, and the isolation layer is distributed on the surface of the semiconductor layer and the surface of the gate insulating layer.

12. The semiconductor device according to claim 7, wherein: The first electrode includes a first end face facing the word line and a second end face away from the word line, as well as a side surface connecting the first end face and the second end face. The semiconductor device also includes a capacitor, which includes a first pole and a second pole. The first electrode serves as the first pole of the capacitor, and the second pole surrounds the side surface of the first electrode.

13. The semiconductor device according to claim 12, characterized in that The semiconductor device further includes: a support layer extending in a direction perpendicular to the substrate, wherein the support layer wraps around the second end surface of each of the first electrodes and wraps around a region of the side surface close to the second end surface.

14. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 13.

15. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate, and a word line extending along a direction perpendicular to the substrate through the different layers, the transistor comprises a first electrode and a second electrode, and the manufacturing method of the semiconductor device comprises: A substrate is provided, and a plurality of stacked structures are formed on the substrate; each of the stacked structures comprises a stack of a first insulating layer and a first conductive layer, the first insulating layer is arranged on a side of the first conductive layer facing the substrate, the stacked structure further comprises a sacrificial layer, the sacrificial layer comprises at least one of the following: a first sacrificial layer arranged on a side of the first conductive layer facing the first insulating layer, and a second sacrificial layer arranged on a side of the first conductive layer away from the first insulating layer; the first conductive layer comprises a preset electrode pattern, the preset electrode pattern comprises a first electrode and a second electrode of the transistor to be formed; Etching the stacked structure to form a through hole penetrating the plurality of stacked structures in a direction perpendicular to the substrate, wherein the sidewall of the through hole exposes each of the first conductive layers, and laterally etching the first conductive layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first insulating layer falls within the orthographic projection of the through hole located in the first conductive layer, and laterally etching the sacrificial layer so that, on a plane parallel to the substrate, the orthographic projection of the through hole located in the first conductive layer falls within the orthographic projection of the through hole located in the sacrificial layer, and the through hole disconnects the first electrode and the second electrode in the preset electrode pattern; Depositing a semiconductor film and a gate insulating film in the through hole in sequence to form a multi-layer semiconductor layer and a gate insulating layer of the transistor, wherein the semiconductor layer is connected to the first electrode and the second electrode, and the semiconductor layer is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode; A word line is formed in the through hole.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The forming of a word line in the through hole comprises: Depositing a protective layer film in the through hole to form a protective layer, wherein the protective layer film is a conductive film; Etching the protective layer in the through hole so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and the side wall of the through hole located in the first conductive layer exposes the protective layer; etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer; A gate electrode film is deposited in the through hole, and the gate electrode film fills the through hole to form the word line.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: Etching the protection layer in the through hole so that the sidewall of the through hole located in the first insulating layer exposes the gate insulating layer, and the sidewall of the through hole located in the first conductive layer exposes the protection layer; Etching and removing the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer comprises: Etching the protective layer in the through hole by wet etching, so that the side wall of the through hole located in the first insulating layer exposes the gate insulating layer, and a portion of the protective layer is retained in the through hole located in the first insulating layer; The semiconductor layer and the gate insulating layer located in the through hole of the first insulating layer are removed by wet etching.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: After the etching removes the semiconductor layer and the gate insulating layer in the through hole of the first insulating layer, and before depositing a gate electrode film in the through hole, the method further includes: Depositing a gate insulating film in the through hole to form an isolation layer; The isolation layer covering the side of the protection layer facing the through hole is removed by etching.

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