Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device and a preparation method thereof and electronic equipment. The semiconductor device includes a substrate, a landing pad, a first interconnect layer, a capacitor, a plurality of interlayer dielectric layers, a contact plug, and a second interconnect layer. The substrate includes an array region having a first transistor and a peripheral region having a second transistor. The landing pad is located in the array region and electrically connected with the first transistor. The first interconnection layer is located in the peripheral area and electrically connected with the second transistor. The capacitor is located in the array region and electrically connected with the first transistor through the landing pad. The plurality of interlayer dielectric layers cover the first interconnection layer and are provided with contact holes exposing a part of the first interconnection layer, and the maximum aperture of the contact holes in the bottom layer of the plurality of interlayer dielectric layers is larger than the minimum aperture of the contact holes in the top layer of the plurality of interlayer dielectric layers. The contact plug is filled in the contact hole and contacts the first interconnection layer. And the second interconnection layer is positioned on the plurality of interlayer dielectric layers and is in contact with the contact plug. The semiconductor device can improve the contact resistance between the contact plug and the first interconnection layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor device and a method for manufacturing the same, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory. Compared with static memory, DRAM memory has the advantages of simpler structure, lower manufacturing cost and higher capacity density. With the development of technology, DRAM memory is increasingly used.

[0003] In order to store or read data information, the interconnection structure is an indispensable structure in DRAM memory. Usually, the interconnection layer leads out the signal by connecting to the contact plug in the device. However, the contact resistance between the contact plug and the conductive structure of the interconnection layer is relatively large, which reduces the yield of the semiconductor device. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a semiconductor device is provided, comprising: a substrate, comprising an array region and a peripheral region surrounding the array region, the array region comprising a first transistor, and the peripheral region comprising a second transistor; a landing pad, located in the array region and electrically connected to the first transistor; a first interconnect layer, located in the peripheral region and electrically connected to the second transistor; a capacitor, located in the array region and electrically connected to the first transistor through the landing pad; a plurality of interlayer dielectric layers, the plurality of interlayer dielectric layers covering the first interconnect layer, the plurality of interlayer dielectric layers having contact holes, the contact holes exposing a portion of the first interconnect layer, the maximum aperture of the contact hole in the bottom layer among the plurality of interlayer dielectric layers being larger than the minimum aperture of the contact hole in the top layer among the plurality of interlayer dielectric layers; a contact plug, filled in the contact hole and contacting the first interconnect layer; a second interconnect layer, located on the plurality of interlayer dielectric layers, a portion of the second interconnect layer contacting the contact plug.

[0005] In some embodiments, the diameter of the contact hole at the bottom increases first and then decreases, or the diameter increases gradually.

[0006] In some embodiments, the plurality of interlayer dielectric layers include the same material as the capacitor dielectric layer in the capacitor.

[0007] In some embodiments, the plurality of interlayer dielectric layers include: a first interlayer dielectric layer, covering the first interconnect layer, the first interlayer dielectric layer being a nitrogen-containing insulating material and serving as a bottom layer; a second interlayer dielectric layer, located on the first interlayer dielectric layer, the second interlayer dielectric layer being a relatively high-density oxygen-containing insulating material and serving as an intermediate layer; and a third interlayer dielectric layer, located on the second interlayer dielectric layer, the third interlayer dielectric layer being a relatively low-density oxygen-containing insulating material and serving as a top layer.

[0008] According to a second aspect of an embodiment of the present disclosure, a method for preparing a semiconductor device is provided, comprising: providing a substrate, the substrate comprising an array area and a peripheral area surrounding the array area, the array area comprising a first transistor, and the peripheral area comprising a second transistor; forming a landing pad electrically connected to the first transistor on the array area, and forming a first interconnection layer electrically connected to the second transistor on the peripheral area; forming a capacitor in the array area, the capacitor being electrically connected to the first transistor through the landing pad; forming a plurality of interlayer dielectric layers covering the first interconnection layer, and forming a contact hole penetrating the plurality of interlayer dielectric layers in the peripheral area, the contact hole exposing a portion of the first interconnection layer, the maximum aperture of the contact hole in the bottom layer among the plurality of interlayer dielectric layers being larger than the minimum aperture of the contact hole in the top layer among the plurality of interlayer dielectric layers; forming a contact plug in the contact hole; forming a second interconnection layer on the plurality of interlayer dielectric layers, a portion of the second interconnection layer contacting the contact plug.

[0009] In some embodiments, the plurality of interlayer dielectric layers include the same material as the capacitor dielectric layer in the capacitor, and the two are formed simultaneously.

[0010] In some embodiments, the plurality of interlayer dielectric layers include a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, wherein forming a capacitor and forming the plurality of interlayer dielectric layers include: forming a stack covering a landing pad and a first interconnect layer, the stack including a plurality of support layers and a sacrificial layer located between adjacent support layers; patterning the stack located on the array region to form a capacitor hole, wherein the capacitor hole exposes the landing pad; forming a first electrode layer on an inner wall of the capacitor hole; removing the sacrificial layer located on the array region, and removing a portion of the stack located on the peripheral region while retaining the plurality of support layers located on the peripheral region; The bottom layer in the layer; forming a capacitor dielectric layer, a second electrode layer and a capacitor cover layer stacked in sequence on the first electrode layer, the capacitor dielectric layer, the second electrode layer and the capacitor cover layer also sequentially cover the bottom layer in the multiple supporting layers on the peripheral area; removing the second electrode layer and the capacitor cover layer on the peripheral area, retaining the bottom layer and the capacitor dielectric layer in the multiple supporting layers, and respectively forming a first interlayer dielectric layer and a second interlayer dielectric layer; forming a third interlayer dielectric layer, the third interlayer dielectric layer covers the second interlayer dielectric layer and the capacitor cover layer, wherein the portion covering the capacitor cover layer constitutes an insulating layer covering the capacitor.

[0011] In some embodiments, forming a plurality of interlayer dielectric layers covering the first interconnect layer and forming a contact hole penetrating the plurality of interlayer dielectric layers in the peripheral region comprises: depositing a nitrogen-containing insulating material on the first interconnect layer to form a first interlayer dielectric layer; depositing a relatively high-density oxygen-containing insulating material on the first interlayer dielectric layer to form a second interlayer dielectric layer; depositing a relatively low-density oxygen-containing insulating material on the second interlayer dielectric layer to form a third interlayer dielectric layer; etching the third interlayer dielectric layer through a first dry etching process until the second interlayer dielectric layer is exposed, continuing to etch the second interlayer dielectric layer through a second dry etching process until the first interlayer dielectric layer is exposed, and then continuing to etch the first interlayer dielectric layer through a third dry etching process until the first interconnect layer is exposed to form the contact hole; wherein the first dry etching process comprises a C-containing x F y gas, the second dry etching process includes a chlorine-containing gas, and the third dry etching process includes a C x F y and C x H y F z of mixed gases.

[0012] In some embodiments, after etching the first interlayer dielectric layer through a third dry etching process, the method further includes: performing isotropic etching through a wet etching process.

[0013] In some embodiments, the third dry etching process further includes argon gas.

[0014] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including: a processing device; and a storage device electrically connected to the processing device, wherein the storage device includes the above-mentioned semiconductor device.

[0015] In an embodiment of the present disclosure, a semiconductor device and a preparation method are provided, in which the contact area between the contact plug and the first interconnection layer is increased by making the maximum aperture of the contact hole in the bottom layer among multiple interlayer dielectric layers larger than the minimum aperture of the contact hole in the top layer among multiple interlayer dielectric layers, thereby reducing the contact resistance between the contact plug and the first interconnection layer and improving the performance of the interconnection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment;

[0017] Figure 2 is based on Figure 1 A partial enlarged schematic diagram of the middle C area;

[0018] Figure 3 is a schematic structural diagram of a semiconductor device according to yet another exemplary embodiment;

[0019] Figure 4 is based on Figure 3 A partial enlarged schematic diagram of the D area in the middle;

[0020] Figure 5 is a process flow chart of a method for preparing a semiconductor device according to an exemplary embodiment;

[0021] Figures 6 to 22 is a cross-sectional view showing a process of manufacturing a semiconductor device according to an exemplary embodiment;

[0022] Fig.23 The diagram is a schematic structural diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0023] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0024] The present disclosure is described in more detail in the following paragraphs with reference to the accompanying drawings by way of example. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0025] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0026] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0028] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0029] Figure 1 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment. Figure 2 is based on Figure 1 A partial enlarged schematic diagram of the C area in the middle. Figure 3 is a schematic structural diagram of a semiconductor device according to yet another exemplary embodiment. Figure 4 is based on Figure 3 A partial enlarged schematic diagram of the D area in the middle. Figure 5 The invention is a process flow chart of a method for manufacturing a semiconductor device according to an exemplary embodiment. Figures 6 to 22 is a cross-sectional view of a semiconductor device manufacturing process according to an exemplary embodiment. Figures 1 to 22 Semiconductor devices and their manufacturing processes are described.

[0030] Reference Figure 1 and attached Figure 2 As shown, the semiconductor device includes a substrate 200, a first interconnection layer 100, a plurality of interlayer dielectric layers 300, a contact plug 400, a second interconnection layer (not shown in the figure), a landing pad 500, and a capacitor 600. The substrate 200 includes an array region 220 and a peripheral region 230 surrounding the array region 220, the array region 220 includes a first transistor (not shown in the figure), and the peripheral region 230 includes a second transistor 210. The semiconductor device may be a dynamic random access memory (DRAM) or other memory.

[0031] Please continue to refer to the attached Figure 1 and attached Figure 2 The first interconnect layer 100 can be arranged on the peripheral area 230 of the substrate 200 and electrically connected to the device located in the substrate 200, such as the second transistor 210. The first interconnect layer 100 can include a plurality of conductive wires of different shapes, such as tungsten, titanium nitride, etc. Each conductive wire can be electrically connected to the second transistor 210 to provide a path for a data signal or a control signal.

[0032] The second transistor 210 includes a gate structure 211, a drain region and a source region, which are electrically connected to the first interconnect layer 100 through a gate contact plug (not shown in the figure), a drain contact plug 212, and a source contact plug 213, that is, they are electrically connected to a plurality of conductive lines. The first interconnect layer 100 is located above the second transistor 210, and the first interconnect layer 100 includes a conductive layer 120 and a dielectric layer 110 located between the conductive layers 120, such as silicon oxide or silicon nitride, which isolates the conductive layers 120 from each other. Part of the conductive layer 120 of the first interconnect layer 100 contacts and is electrically conductive with the drain contact plug 212. Part of the conductive layer 120 in the first interconnect layer 100 contacts and is electrically conductive with the source contact plug 213.

[0033] Please continue to refer to the attached Figure 1 and attached Figure 2 , multiple interlayer dielectric layers 300 cover the first interconnection layer 100. That is, multiple interlayer dielectric layers 300 are stacked in sequence on the first interconnection layer 100. Multiple interlayer dielectric layers 300 have contact holes 340, and the depth direction of the contact holes 340 is perpendicular to the first interconnection layer 100, and at least penetrates the multiple interlayer dielectric layers 300, so that the contact holes 340 expose a part of the first interconnection layer 100, for example, a first contact hole is formed at the first interconnection layer portion connected to the drain contact plug 212, and a second contact hole is formed at the first interconnection layer portion connected to the source contact plug 213.

[0034] Please continue to refer to the attached Figure 1 , 2 And attached Fig. 20 , the maximum aperture D1 of the contact hole 340 in the bottom layer among the multiple interlayer dielectric layers 300 is greater than the minimum aperture D2 of the contact hole 340 in the top layer among the multiple interlayer dielectric layers 300. It should be noted that the bottom layer among the multiple interlayer dielectric layers 300 may represent a layer in contact with the first interconnect layer 100, that is, the bottom layer among the multiple interlayer dielectric layers 300. The top layer among the multiple interlayer dielectric layers 300 may represent a layer away from the first interconnect layer 100, which is in contact with the second interconnect layer, that is, the top layer among the multiple interlayer dielectric layers 300.

[0035] In the embodiment of the present disclosure, the thickness dimension of the top layer among the plurality of interlayer dielectric layers 300 is greater than the sum of the thickness dimensions of the remaining layers among the plurality of interlayer dielectric layers 300. For example, if the number of the plurality of interlayer dielectric layers 300 is two, the thickness of the interlayer dielectric layer 300 away from the first interconnect layer 100 is greater than the thickness of the interlayer dielectric layer 300 directly in contact with the first interconnect layer 100. For another example, if the number of the plurality of interlayer dielectric layers 300 is three, the thickness of the interlayer dielectric layer 300 located at the top layer is greater than the sum of the thicknesses of the two interlayer dielectric layers 300 located therebelow. For another example, if the number of the plurality of interlayer dielectric layers 300 is four, the thickness of the interlayer dielectric layer 300 located at the top layer is greater than the sum of the thicknesses of the three interlayer dielectric layers 300 located therebelow.

[0036] Please continue to refer to the attached Figure 1 and attached Figure 2 , the contact plug 400 is filled in the contact hole 340 and contacts the first interconnection layer 100. The second interconnection layer (not shown in the figure) is located on the multiple interlayer dielectric layers 300, and a part of the second interconnection layer contacts the contact plug 400. Like the first interconnection layer 100, the second interconnection layer includes a plurality of conductive wires of different shapes, such as tungsten and titanium nitride, each conductive wire contacts the contact plug 400 at a different position, providing a path for data signals or control signals. The contact plug 400 can be tungsten and / or titanium nitride. The second interconnection layer can be at least one of tungsten, copper, titanium nitride, and tantalum nitride.

[0037] In the present embodiment, the maximum aperture D2 of the contact hole 340 in the bottom layer among the plurality of interlayer dielectric layers 300 is greater than the minimum aperture D1 of the contact hole 340 in the top layer among the plurality of interlayer dielectric layers 300, so that the aperture of the contact hole 340 located in the bottom layer among the plurality of interlayer dielectric layers 300 tends to increase relative to the aperture of the contact hole 340 located in the top layer among the plurality of interlayer dielectric layers 300. By forming the contact hole 340 in a lock shape in the plurality of interlayer dielectric layers 300 above the first interconnection layer 100, further, a bowl-shaped morphology facing downward can be formed by over-etching in the first interconnection layer 100, thereby increasing the area of ​​the conductive layer 120 of the first interconnection layer 100 exposed by the contact hole, thereby increasing the contact area between the contact plug 400 and the conductive layer 120 of the first interconnection layer 100, thereby reducing the contact resistance between the contact plug 400 and the conductive layer 120 of the first interconnection layer 100, thereby improving the performance of the interconnection structure and improving the yield of the semiconductor device.

[0038] Please continue to refer to the attached Figure 1 and attached Figure 2As a possible implementation, the multiple interlayer dielectric layers 300 include, for example, three layers: a first interlayer dielectric layer 310, a second interlayer dielectric layer 320, and a third interlayer dielectric layer 330. The first interlayer dielectric layer 310 covers the first interconnect layer 100, and the first interlayer dielectric layer 310 is the bottom layer. The second interlayer dielectric layer 320 is located on the first interlayer dielectric layer 310, and the second interlayer dielectric layer 320 is the middle layer. The third interlayer dielectric layer 330 is located on the second interlayer dielectric layer 320, and the third interlayer dielectric layer 330 is the top layer. The maximum aperture of the contact hole 340 in the first interlayer dielectric layer 310 is greater than the minimum aperture of the contact hole 340 in the third interlayer dielectric layer 330. As before, of course, it is not limited to this, and the minimum aperture of the contact hole 340 in the first interlayer dielectric layer 310 can also be greater than the minimum aperture of the contact hole 340 in the third interlayer dielectric layer 330, so that the contact hole 340 at the bottom tends to increase, thereby improving the device performance. Similarly, as shown later Figure 3 and Figure 4 The multiple interlayer dielectric layers 300 may also include two layers, or more layers.

[0039] Please refer to the attached Figure 1 and attached Figure 2 For example, the aperture of the contact hole 340 at the bottom may first increase and then decrease, or the aperture may gradually increase, forming a bowl-shaped morphology at the bottom contact, thereby increasing the contact area between the contact plug 400 and the first interconnect layer 100 and reducing the contact resistance of the contact plug 400. At the same time, a constriction is formed in the interlayer dielectric layer 300 above the first interconnect layer 100 to expand the windows between adjacent contact plugs 400, between adjacent first interconnect layers 100, or between adjacent contact plugs 400 and the first interconnect layer 100.

[0040] Please continue to refer to the attached Figures 1 to 2 , and attached Figures 19 to 20 As an example, the contact hole 340 may have an aperture that first increases and then decreases in the bottom layer, that is, the contact hole 340 may have an aperture that first increases and then decreases in the first interlayer dielectric layer 310. For example, the bottom wall of the contact hole 340 exposes the first interconnect layer 100, and the sidewall of the contact hole 340 exposes the first interlayer dielectric layer 310. The sidewall profile of the contact hole 340 is arc-shaped. In the direction toward the first interconnect layer 100, the aperture has an aperture that first increases and then decreases, so as to ensure that there is no gap when the contact plug 400 at the bottom is filled, thereby reducing the contact resistance of the contact plug 400.

[0041] Of course, in other embodiments, the aperture of the contact hole in the first interlayer dielectric layer 310 may also show a trend of gradually increasing (not shown in the figure), and the sidewall profile of the contact hole 340 is arc-shaped, and the aperture gradually increases in the direction toward the first interconnection layer 100, thereby maximizing the contact area between the contact plug 400 and the conductive layer 120 and reducing the contact resistance between the contact plug 400 and the conductive layer 120.

[0042] Please continue to refer to the attached Figure 1 and attached Figure 2 As an example, the aperture of the contact hole 340 in the second interlayer dielectric layer 320 may be gradually increased, and the sidewall profile is arc-shaped. When gradually increasing, it can be connected with the contact hole 340 part in the bottom first interlayer dielectric layer 310, ensuring that the overall morphology of the contact hole at the bottom is first increased and then decreased, or the aperture is gradually increased. At this time, the aperture of the contact hole 340 at the connection position of the second interlayer dielectric layer 320 and the first interlayer dielectric layer 310 is the maximum aperture of the contact hole 340 in the second interlayer dielectric layer 320, and the aperture of the contact hole 340 at the connection position of the second interlayer dielectric layer 320 and the first interlayer dielectric layer 310 is greater than the aperture of the contact hole 340 at the connection position of the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330, thereby ensuring that the aperture of the contact hole 340 in the first interlayer dielectric layer 310 is greater than the aperture of the contact hole 340 in the third interlayer dielectric layer 330. Of course, in other embodiments, the diameter of the contact hole 340 in the second interlayer dielectric layer 320 may also increase first and then decrease, which is similar to the bottom first interlayer dielectric layer 310 .

[0043] Please continue to refer to the attached Figure 1 and attached Figure 2 As an example, the contact hole 340 has a gradually decreasing aperture in the top layer, that is, the third interlayer dielectric layer 330. The thickness of the third interlayer dielectric layer 330 is greater than the sum of the thicknesses of the first interlayer dielectric layer 310 and the second interlayer dielectric layer 320. The third interlayer dielectric layer 330 has a high aspect ratio. When etching the third interlayer dielectric layer 330, the closer to the second interlayer dielectric layer 320, the smaller the aperture of the contact hole 340, and the aperture of the contact hole 340 is the smallest at the connection position between the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330.

[0044] Please continue to refer to the attached Figures 1 to 2 , and attached Figures 19 to 20The contact hole 340 also extends into the first interconnection layer 100, and the bottom wall of the contact hole 340 exposes the first interconnection layer 100. When exposing the surface of the conductive layer 120 in the first interconnection layer 100, it can continue to over-etch a portion of the conductive layer downward, so that the bottom wall profile can be arc-shaped, exposing the surface of the conductive layer 120 to the greatest extent, increasing the contact area between the contact plug 400 and the conductive layer 120, and reducing the contact resistance between the contact plug 400 and the conductive layer 120.

[0045] In the present embodiment, the first interlayer dielectric layer 310 includes a nitrogen-containing insulating material, for example, the material of the first interlayer dielectric layer 310 includes silicon nitride (SiN), but is not limited thereto. The second interlayer dielectric layer 320 and the third interlayer dielectric layer 330 include oxygen-containing insulating materials, and the density of the second interlayer dielectric layer 320 is greater than the density of the third interlayer dielectric layer 330. The material of the second interlayer dielectric layer 320 may include hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the third interlayer dielectric layer 330 includes silicon oxide (SiO2). Exemplarily, among the plurality of interlayer dielectric layers 300, for example, the second interlayer dielectric layer 320 may be the same material as the capacitor dielectric layer 620 in the capacitor 600.

[0046] In this embodiment, the density of the second interlayer dielectric layer 320 is greater than that of the third interlayer dielectric layer 330. During etching, the second interlayer dielectric layer 320 can be used as an etching stop layer to increase the etching selectivity between the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330 and the first interlayer dielectric layer 310, so that the aperture of the third interlayer dielectric layer 330 remains almost unchanged and stays on the first interlayer dielectric layer 310. After that, the first interlayer dielectric layer 310 is continuously etched. Under the premise of not over-etching the conductive layer 120 of the first interconnection layer 100, the aperture in the first interlayer dielectric layer 310 can be enlarged, and at the same time, the aperture of the contact hole 340 at the connection position between the second interlayer dielectric layer 320 and the first interlayer dielectric layer 310 is made larger than the aperture of the contact hole 340 at the connection position between the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330.

[0047] Please return to the attached Figure 1 , the landing pad 500 array area 220, the landing pad 500 can be located on the substrate 200 and electrically connected to the first transistor in the substrate 200. The landing pad 500 and the first interconnect layer 100 can be located at the same horizontal position, and the landing pad 500 includes a plurality of conductive pads made of materials such as tungsten and / or titanium nitride, and adjacent landing pads 500 are isolated from each other by the dielectric layer 100.

[0048] Please return to the attached Figure 1 , and attached Fig.12 , the capacitor 600 is located in the array area 220, can be located above the landing pad 500, and is electrically connected to the first transistor through the landing pad 500 to store and read data. The capacitor 600 includes a first electrode layer 610, a capacitor dielectric layer 620, a second electrode layer 630 and a capacitor cover layer 640. The capacitor 600 can be a cylinder or a pillar capacitor. In the embodiment of the present disclosure, the first electrode layer 610 and the second electrode layer 630 can be, for example, titanium nitride electrodes, and the capacitor dielectric layer 620 is a high-K dielectric layer, such as at least one of hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The multiple interlayer dielectric layers 300 contain the same material as the capacitor dielectric layer 620 in the capacitor, for example, the middle layer in the three interlayer dielectric layers, and the second interlayer dielectric layer 320 is made of the same material as the capacitor dielectric layer 620. For example, when preparing the semiconductor device in the embodiment of the present disclosure, the high-K dielectric layer can be deposited in the array area 220 and the peripheral area 230 at the same time, and the part located in the array area 220 is used as the capacitor dielectric layer 620, and the part located in the peripheral area 230 is used as the second interlayer dielectric layer 320, so that the etching selectivity of the first interlayer dielectric layer 310, the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330 in the peripheral area 230 is different, and the opening size of the second interlayer dielectric layer 320 with high-k dielectric can be fixed to avoid short circuits between adjacent contact plugs, and the bottom of the contact plug 400 and the first interconnection layer 100 can be contacted to form a bowl-shaped morphology facing down to increase the contact area with the first interconnection layer 100 and reduce the contact resistance of the contact plug 400.

[0049] Please refer to the attached Figure 3 and attached Figure 4 , a schematic diagram of the structure of a semiconductor device shown in another exemplary embodiment is shown. In this embodiment, the plurality of interlayer dielectric layers 300 include: a first interlayer dielectric layer 310 and a second interlayer dielectric layer 320. The first interlayer dielectric layer 310 covers the first interconnect layer 100, and the first interlayer dielectric layer 310 is the bottom layer. The second interlayer dielectric layer 320 is located on the first interlayer dielectric layer 310, the second interlayer dielectric layer 320 is the top layer, and the thickness of the second interlayer dielectric layer 320 is greater than the thickness of the first interlayer dielectric layer 310.

[0050] The first interlayer dielectric layer 310 and the second interlayer dielectric layer 320 both contain oxygen insulating materials, and the density of the first interlayer dielectric layer 310 is greater than that of the second interlayer dielectric layer 320. In this embodiment, the density of the second interlayer dielectric layer 320 is relatively small, and the density of the first interlayer dielectric layer 310 is relatively large, so that the etching rates of the first interlayer dielectric layer 310 and the second interlayer dielectric layer 320 can be increased. When forming the contact hole 340 located in the first interlayer dielectric layer 310, the diameter of the contact hole 340 in the first interlayer dielectric layer 310 can be enlarged without over-etching the conductive layer 120 of the first interconnection layer 100, thereby increasing the area of ​​the conductive layer 120 exposed by the contact hole 340, and further increasing the contact area between the contact plug 400 and the conductive layer 120 of the first interconnection layer 100.

[0051] In this embodiment, the material of the first interlayer dielectric layer 310 may include hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). The material of the second interlayer dielectric layer 320 includes silicon oxide (SiO2).

[0052] The present disclosure also provides a method for preparing a semiconductor device. Figure 5 , the preparation method comprises the following steps:

[0053] S10: providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region, the array region comprising a first transistor, and the peripheral region comprising a second transistor;

[0054] S20: forming a landing pad electrically connected to the first transistor on the array region, and forming a first interconnect layer electrically connected to the second transistor on the peripheral region;

[0055] S30: forming a capacitor in the array region, wherein the capacitor is electrically connected to the first transistor through the landing pad;

[0056] S40: forming a plurality of interlayer dielectric layers covering the first interconnect layer, and forming contact holes penetrating the plurality of interlayer dielectric layers in the peripheral region, wherein the contact holes expose a portion of the first interconnect layer, and wherein the maximum aperture of the contact holes in the bottom layer among the plurality of interlayer dielectric layers is greater than the minimum aperture of the contact holes in the top layer among the plurality of interlayer dielectric layers;

[0057] S50: forming a contact plug in the contact hole;

[0058] S60: forming a second interconnect layer on the plurality of interlayer dielectric layers, wherein a portion of the second interconnect layer contacts the contact plug.

[0059] It should be understood that Figure 5 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 5 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0060] Reference Figure 5 As shown, a substrate 200 is provided. The substrate 200 includes an array area 220 and a peripheral area 230. Word lines (not shown in the figure), bit lines (not shown in the figure), and first transistors (not shown in the figure) coupled to the word lines and bit lines are formed in the array area 220, and a plurality of second transistors 210 are formed in the peripheral area to form a logic control circuit, which addresses each memory cell in the array area 220 by passing through the word lines and bit lines of the array area 220, and turns on the first transistors, which are electrically connected to the capacitor 600, to perform data reading, writing or access.

[0061] Reference Figure 5 and attached Figure 6 As shown, a landing pad 500 electrically connected to the first transistor is formed on the array region 220, and a first interconnection layer 100 electrically connected to the second transistor 210 is formed on the peripheral region 230. The landing pad 500 and the first interconnection layer 100 can be formed at the same time, and after the conductive layer 120 in the adjacent landing pads 500 and the first interconnection layer 100 is formed, the dielectric layer 110 is formed to isolate each other.

[0062] Reference Figure 5 and attached Figure 6 As shown, a capacitor 600 is formed in the array region 220, and the capacitor 600 is electrically connected to the first transistor through the landing pad 500. As an example, one of the plurality of interlayer dielectric layers 300 is made of the same material as the capacitor dielectric layer of the capacitor, and the two are formed simultaneously. For example, the plurality of interlayer dielectric layers 300 include a first interlayer dielectric layer 310, a second interlayer dielectric layer 320, and a third interlayer dielectric layer 330, and the second interlayer dielectric layer 320 is formed synchronously with the capacitor dielectric layer of the capacitor.

[0063] Please continue to refer to the attached Figure 6 As shown, specifically, a stack 700 covering the landing pad 500 and the first interconnect layer 100 is formed, and the stack 700 includes a plurality of support layers 710 and a sacrificial layer 720 located between adjacent support layers 710; the bottom layers of the plurality of support layers 710 are filled with adjacent landing pads 500. In this embodiment, the number of layers of the support layer 710 is three, and the number of layers of the sacrificial layer 720 is two. The material of the support layer 710 includes silicon nitride, and the material of the sacrificial layer 720 is silicon oxide. Afterwards, the stack 700 located on the array area 220 is patterned to form a capacitor hole 730, and the capacitor hole 730 exposes the landing pad 500.

[0064] Please refer to the attached Figure 7 and attached Figure 8 , a first electrode layer 610 is formed on the inner wall of the capacitor hole 730 ; illustratively, a first electrode material layer 611 is formed, the first electrode material layer 611 covers the inner wall of the capacitor hole 730 , and extends outside the capacitor hole 730 to cover the top surface of the stack 700 .

[0065] Please refer to the attached Figure 8 , the first electrode material layer 611 located on the top surface of the stack 700 is removed, and the first electrode material layer 611 remaining in the capacitor hole 730 constitutes the first electrode layer 610.

[0066] Afterwards, please refer to the attached Fig. 9 , the sacrificial layer 720 located on the array region 220 is removed, and part of the stacked layers located on the peripheral region 230 is removed, and the bottom layer among the plurality of support layers 710 located on the peripheral region is retained. The bottom layer among the plurality of support layers 710 located on the peripheral region is retained to be used as the bottom layer of the plurality of interlayer dielectric layers 300. That is, the bottom layer of the plurality of support layers 710 retained on the peripheral region 230 is used as the first interlayer dielectric layer 310.

[0067] Afterwards, please refer to the attached Figures 10 to 12 , a capacitor dielectric layer 620, a second electrode layer 630 and a capacitor cover layer 640 are sequentially stacked on the first electrode layer 610. The capacitor dielectric layer 620, the second electrode layer 630 and the capacitor cover layer 640 also sequentially cover the bottom layer of the multiple supporting layers located on the peripheral area 230, that is, the capacitor dielectric layer 620, the second electrode layer 630 and the capacitor cover layer 640 sequentially cover the first interlayer dielectric layer 310. The thickness of the capacitor dielectric layer 620 located on the peripheral area 230 may be greater than the thickness of the capacitor dielectric layer 620 located on the first electrode layer 610.

[0068] Please refer to the attached Fig.13 , remove the second electrode layer 630 and the capacitor cap layer 640 located on the peripheral area 230, and retain the bottom layer and the capacitor dielectric layer 620 in the multiple support layers 710 to form the first interlayer dielectric layer 310 and the second interlayer dielectric layer 320 respectively. At this time, the first interlayer dielectric layer 310 is a nitrogen-containing insulating material, which is silicon nitride. The second interlayer dielectric layer 310 is a relatively high-density oxygen-containing insulating material, which is hafnium silicon oxide (HfSiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0069] Please continue to refer to the attached Fig.14, forming a third interlayer dielectric layer 330 , the third interlayer dielectric layer 330 covers the second interlayer dielectric layer 320 , and the third interlayer dielectric layer 330 may be a relatively low-density oxygen-containing insulating material including silicon oxide.

[0070] Please continue to refer to the attached Fig.14 , illustratively, the third interlayer dielectric layer 330 also covers the capacitor capping layer 640, wherein the portion covering the capacitor capping layer 640 constitutes an insulating layer covering the capacitor 600. This facilitates forming a contact hole exposing the capacitor capping layer 640 in the array region, and when the contact plug is filled, it contacts the capacitor capping layer 640, and the capacitor 600 is electrically connected to the second interconnection layer through the contact plug.

[0071] In this embodiment, the first interlayer dielectric layer 310 and the bottom layer in the support layer 710 are formed simultaneously, the second interlayer dielectric layer 320 and the capacitor dielectric layer 620 are formed simultaneously, and the third interlayer dielectric layer 330 and the insulating layer covering the capacitor cover layer 640 are formed simultaneously. As another example, the multiple layers in the array area 220 and the interlayer dielectric layer in the peripheral area can be formed separately. Specifically, when removing the film layer located on the peripheral area 230, the second electrode layer 630, the capacitor cover layer 640, the capacitor dielectric layer 620 and the bottom layer in the multiple support layers 710 are removed simultaneously. Afterwards, the insulating material layer is re-deposited, and the nitrogen-containing insulating material is deposited on the first interconnect layer 100 to form the first interlayer dielectric layer 310. Afterwards, a relatively high-density oxygen-containing insulating material is deposited on the first interlayer dielectric layer 310 to form a second interlayer dielectric layer 320. Finally, a relatively low-density oxygen-containing insulating material is deposited on the second interlayer dielectric layer 320 to form a third interlayer dielectric layer 330. The third interlayer dielectric layer 330 also covers the capacitor cover layer 640, wherein the portion covering the capacitor cover layer 640 constitutes an insulating layer covering the capacitor 600.

[0072] Afterwards, please refer to the attached Fig.15 and attached Fig.16 , the third interlayer dielectric layer 330 is etched by a first dry etching process until the second interlayer dielectric layer 320 is exposed. The first dry etching process includes a C x F y The gas, such as CF 4 gas, uses the second interlayer dielectric layer 320 as an etching stop layer to etch the second interlayer dielectric layer 320 until the top surface of the first interlayer dielectric layer 310 is etched to form a first middle hole 350 .

[0073] Please refer to the attached Fig.17 and attached Fig.18, the second interlayer dielectric layer 320 is further etched through a second dry etching process until the first interlayer dielectric layer 310 is exposed, so as to form a second intermediate hole 360 ​​in the first interlayer dielectric layer 310. The second dry etching process includes a chlorine-containing gas. For example, the chlorine-containing gas in the second dry etching process may include Cl2 and / or CHCl2. The flow rate of the chlorine-containing gas in the second dry etching process is 15sccm to 40sccm, such as 20sccm, 28sccm, 32sccm, and the etching time is 5min to 10min, such as 6min, 8min, 9min. The chlorine-containing gas increases the etching selectivity of the second interlayer dielectric layer 320 and the third interlayer dielectric layer 330, and increases the etching selectivity of the second interlayer dielectric layer 320 and the first interlayer dielectric layer 310. On the premise of increasing the aperture of the second intermediate hole 360, it can also ensure that the critical size of the first intermediate hole 350 is not damaged.

[0074] Afterwards, please refer to the attached Fig.19 and attached Fig. 20 , the first interlayer dielectric layer 310 is further etched through a third dry etching process until the first interconnection layer 100 is exposed to form a third middle hole 370, and the third middle hole 370 extends to the conductive layer 120 of the first interconnection layer 100. The third middle hole 370, the second middle hole 360 ​​and the first middle hole 350 form a contact hole 340.

[0075] The third dry etching process includes C x F x and C x H y F z A mixed gas, such as a mixed gas of CF4 and CHF3, is used to etch the first dielectric layer 310 with CF4 as the main gas. At the same time, the polymer produced by CHF3 during etching can play a protective role, and the expected morphology can be better formed. The gas flow rate of the mixed gas is 20sccm to 50sccm, such as 30sccm and 45sccm, and the etching time is 3min to 8min, such as 4min and 5min. Among them, C x F y The gas flow rate can be selected within the range of 20sccm to 50sccm. x H y F zIt can also be selected within the range of gas flow rate of 20 sccm to 50 sccm. The gas flow rate of the etching process can be increased compared to that of the second dry etching process, while the etching time is shortened, thereby opening up the etching selectivity ratio of the second interlayer dielectric layer 320 to the third interlayer dielectric layer 330, the first interlayer dielectric layer 310, and the conductive layer 120 of the first interconnection layer 100, and etching the first interlayer dielectric layer 310 while keeping the critical size of the second middle hole 360 ​​unchanged.

[0076] Afterwards, the conductive layer 120 of the first interconnection layer 100 is overetched by 2 nm to 3 nm, so that the contact hole 340 extends into the conductive layer 120 of the first interconnection layer 100, and the bottom wall profile of the contact hole 340 is arc-shaped, thereby increasing the exposed area of ​​the first interconnection layer 110. For example, in the third dry etching process, argon (Ar) is also included, and when the first interlayer dielectric layer 310 is nearly completely etched, the C x F x and C x H y F z The flow rate of the mixed gas is increased, the flow rate of the Ar gas is increased (or the flow rate of the Ar gas is kept unchanged), and the first interlayer dielectric layer 310 and the conductive layer 120 of the first interconnect layer 100 are physically etched by the Ar gas, and a portion of the conductive layer 120 of the first interconnect layer 100 is etched so that the bottom wall profile of the contact hole 340 is arc-shaped. It should be noted that the bottom wall profile of the contact hole 340 can be understood as the profile of the contact hole 340 in the first interconnect layer 100, and can also be understood as the profile of the contact hole 340 in the first interlayer dielectric layer 310 and the first interconnect layer 100. In some other embodiments, based on the expected profile of the contact hole, the first dry etching process, the second dry etching process, and the third dry etching process all contain Ar gas, and the first interlayer dielectric layer 310, the second interlayer dielectric layer 320, and the third interlayer dielectric layer 330 are physically etched.

[0077] Exemplarily, after etching the first interlayer dielectric layer by the third dry etching process, the first interlayer dielectric layer 310 is isotropically etched by a wet etching process. Exemplarily, at an etching temperature of 70° C. to 120° C., the first interlayer dielectric layer 310 is isotropically etched by hot phosphoric acid, and the first interlayer dielectric layer 310 and the first interconnection layer 100 are further etched along the previous profile to form a larger profile, while the opening size of the upper third dielectric layer 330 and the second dielectric layer 320 remains almost unchanged, that is, the first interlayer dielectric layer 310 exposed in the third middle hole 370 is laterally etched and the conductive layer 120 of the first interconnection layer 100 is isotropically etched to increase the size of the contact hole 340 located in the first interlayer dielectric layer 310 and the first interconnection layer 100. Moreover, in this embodiment, the etching process is performed at an etching temperature of 70°C to 120°C, for example, 80°C, 90°C, and an etching time of 1min to 5min, for example, 1min, 2min. The combination of the etching temperature and the etching time can obtain an etching rate ratio of 2:1 between the first interlayer dielectric layer 310 and the conductive layer 120 of the first interconnection layer 100, which can reduce excessive etching of the conductive layer 120 and also ensure that the aperture of the contact hole 340 located in the third interlayer dielectric layer 330 remains unchanged.

[0078] After that, please refer to the attached Fig.21 and attached Fig. 22 A contact plug 400 is formed in the contact hole 340. Specifically, a metal conductive material, such as tungsten and / or titanium nitride, can be deposited in the contact hole 340 through a deposition process to form a contact plug. The bottom wall of the contact plug 400 is in contact with the first interconnect layer 100 (i.e., the conductive layer 120), and there is a relatively large contact area between the two.

[0079] Afterwards, a second interconnection layer is formed on multiple interlayer dielectric layers 300, specifically on the top layer of multiple interlayer dielectric layers 300, for example, on the third interlayer dielectric layer 330. The second interconnection layer is similar to the first interconnection layer 100 and includes multiple conductive lines of different shapes. A portion of the second interconnection layer contacts the contact plug 400.

[0080] Please refer to the attached Fig.23 The present disclosure also provides an electronic device 1 having a storage function, the electronic device comprising a processor 2 and a storage device 3 electrically connected to the processor, the storage device comprising the above Figures 1 to 22The semiconductor device 4 described in the embodiment of the present invention. The electronic device may be a terminal device, such as a personal computer, a mobile phone, a tablet computer, a consumer electronics product, such as a smart home appliance, an autonomous driving device, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, or a server, a data center, etc. The memory device 3 may be, for example, a dynamic random access memory (DRAM). The storage function in the electronic device 1 may be implemented by these memory devices 3.

[0081] In some embodiments, the processor 2 and the memory 3 can be two independent chips to form an independent memory. In other embodiments, the memory 3 and the processor 2 can also be integrated into the same chip to form an embedded memory. Figures 1 to 22 The described semiconductor device 4 can solve the same technical problem and achieve the same expected effect.

[0082] The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims. Each embodiment or implementation method in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other.

Claims

1. A semiconductor device, characterized in that: include: A substrate, comprising an array region and a peripheral region surrounding the array region, wherein the array region comprises a first transistor and the peripheral region comprises a second transistor; a landing pad, located in the array region and electrically connected to the first transistor; a first interconnect layer, located in the peripheral region and electrically connected to the second transistor; a capacitor, the capacitor being located in the array region and electrically connected to the first transistor through the landing pad; A plurality of interlayer dielectric layers, the plurality of interlayer dielectric layers covering the first interconnection layer, the plurality of interlayer dielectric layers having contact holes therein, the contact holes exposing a portion of the first interconnection layer, the maximum aperture of the contact holes at the bottom layer in the plurality of interlayer dielectric layers being larger than the minimum aperture of the contact holes at the top layer in the plurality of interlayer dielectric layers; a contact plug filled in the contact hole and contacting the first interconnection layer; The second interconnection layer is located on the plurality of interlayer dielectric layers, and a portion of the second interconnection layer contacts the contact plug.

2. The semiconductor device according to claim 1, wherein: The aperture of the contact hole at the bottom shows a trend of first increasing and then decreasing, or the aperture shows a trend of gradually increasing.

3. The semiconductor device according to claim 1, wherein: The plurality of interlayer dielectric layers include the same material as that of the capacitor dielectric layer in the capacitor.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The plurality of interlayer dielectric layers include: a first interlayer dielectric layer, covering the first interconnect layer, wherein the first interlayer dielectric layer is a nitrogen-containing insulating material and serves as the bottom layer; A second interlayer dielectric layer, located on the first interlayer dielectric layer, the second interlayer dielectric layer is a relatively high-density oxygen-containing insulating material and serves as an intermediate layer; The third interlayer dielectric layer is located on the second interlayer dielectric layer. The third interlayer dielectric layer is a relatively low-density oxygen-containing insulating material and serves as the top layer.

5. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region, the array region comprising a first transistor, and the peripheral region comprising a second transistor; forming a landing pad electrically connected to the first transistor on the array region, and forming a first interconnect layer electrically connected to the second transistor on the peripheral region; forming a capacitor in the array region, the capacitor being electrically connected to the first transistor through the landing pad; forming a plurality of interlayer dielectric layers covering the first interconnect layer, and forming contact holes penetrating the plurality of interlayer dielectric layers in the peripheral region, wherein the contact holes expose a portion of the first interconnect layer, and wherein the maximum aperture of the contact holes at the bottom layer among the plurality of interlayer dielectric layers is greater than the minimum aperture of the contact holes at the top layer among the plurality of interlayer dielectric layers; forming a contact plug in the contact hole; A second interconnection layer is formed on the plurality of interlayer dielectric layers, a portion of the second interconnection layer contacts the contact plug.

6. The preparation method according to claim 5, characterized in that: The plurality of interlayer dielectric layers contain the same material as the capacitor dielectric layer in the capacitor, and the two are formed simultaneously.

7. The preparation method according to claim 6, characterized in that: The plurality of interlayer dielectric layers include a first interlayer dielectric layer, a second interlayer dielectric layer, and a third interlayer dielectric layer, wherein forming the capacitor and forming the plurality of interlayer dielectric layers include: forming a stack covering the landing pad and the first interconnect layer, the stack comprising a plurality of support layers and a sacrificial layer between adjacent support layers; Patterning the stacked layer on the array region to form a capacitor hole, wherein the capacitor hole exposes the landing pad; forming a first electrode layer on the inner wall of the capacitor hole; Removing the sacrificial layer located on the array region, and removing a portion of the stacked layers located on the peripheral region while retaining a bottom layer among a plurality of supporting layers located on the peripheral region; Forming a capacitor dielectric layer, a second electrode layer and a capacitor cover layer stacked in sequence on the first electrode layer, wherein the capacitor dielectric layer, the second electrode layer and the capacitor cover layer also sequentially cover the bottom layer of the plurality of support layers located on the peripheral area; removing the second electrode layer and the capacitor cover layer on the peripheral area, retaining the bottom layer and the capacitor dielectric layer among the plurality of support layers, and forming the first interlayer dielectric layer and the second interlayer dielectric layer respectively; The third interlayer dielectric layer is formed, and the third interlayer dielectric layer covers the second interlayer dielectric layer and the capacitor cover layer, wherein the portion covering the capacitor cover layer constitutes an insulating layer covering the capacitor.

8. The preparation method according to any one of claims 5 to 7, characterized in that: Forming a plurality of interlayer dielectric layers covering the first interconnect layer, and forming contact holes penetrating the plurality of interlayer dielectric layers in the peripheral region comprises: Depositing a nitrogen-containing insulating material on the first interconnect layer to form a first interlayer dielectric layer; Depositing a relatively high-density oxygen-containing insulating material on the first interlayer dielectric layer to form a second interlayer dielectric layer; Depositing a relatively low-density oxygen-containing insulating material on the second interlayer dielectric layer to form a third interlayer dielectric layer; Etching the third interlayer dielectric layer through a first dry etching process until the second interlayer dielectric layer is exposed, continuing to etch the second interlayer dielectric layer through a second dry etching process until the first interlayer dielectric layer is exposed, and then continuing to etch the first interlayer dielectric layer through a third dry etching process until the first interconnection layer is exposed, so as to form the contact hole; Wherein, the first dry etching process includes a C-containing x F y gas, the second dry etching process includes a chlorine-containing gas, and the third dry etching process includes a C x F y and C x H y F z of mixed gases.

9. The preparation method according to claim 8, characterized in that: After etching the first interlayer dielectric layer through the third dry etching process, the method further includes: The isotropic etching is performed by a wet etching process.

10. The preparation method according to claim 8, characterized in that: The third dry etching process also includes argon gas.

11. An electronic device, characterized in that: include: Processing device; as well as A memory device electrically connected to the processing device, wherein the memory device comprises the semiconductor device according to any one of claims 1 to 4.

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