Chip trimming function test method, device, equipment and medium

Abstract

The invention discloses a chip trimming function testing method and device, equipment and a medium, and relates to the technical field of chip testing. The method is applied to automatic test equipment and comprises the following steps: configuring a universal input / output interface for a to-be-tested chip; executing a chip test mode according to a test signal in the general input / output interface, and obtaining serial data sent by the automatic test equipment; and determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction. According to the technical scheme, the test method can be simplified, and the test time can be shortened.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip trimming function testing method, device, equipment and medium. Background Art

[0002] With the rapid development of the integrated circuit industry, the requirements for chip testing are becoming more and more stringent. How to complete chip testing more quickly and accurately is an issue that must be considered in testing. Currently, when the chip is tested on the ATE (Automatic Test Equipment) machine after tape-out, the trim data is written to the trim register through various communication protocols. The operation is too cumbersome and increases the time cost of testing.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a chip trimming function test method, device, equipment and medium, which can simplify the test process and shorten the test time. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a chip trimming function testing method, which is applied to an automated testing device, comprising:

[0006] Configure the general input / output interface for the chip to be tested;

[0007] Execute a chip test mode according to a test signal in the universal input / output interface, and obtain serial data sent by the automated test equipment;

[0008] The data flow direction of the serial data is determined according to a preset data format, and the serial data is written into a trim register based on the data flow direction.

[0009] Optionally, configuring a general input / output interface for the chip to be tested includes:

[0010] A first general input / output interface is configured for the chip to be tested; the first general input / output interface is used to provide a reference clock signal for the automated testing equipment and the chip to be tested;

[0011] A second universal input / output interface is configured for the chip to be tested; the second universal input / output interface is used to provide a test data signal;

[0012] A third general input / output interface is configured for the chip to be tested; the third general input / output interface is used to provide an enable signal for the chip test mode;

[0013] A fourth general input / output interface is configured for the chip to be tested; the fourth general input / output interface is used to provide an indication signal for the trimming register to indicate whether to store data in a memory.

[0014] Optionally, executing a chip test mode according to a test signal in the universal input / output interface includes:

[0015] If it is detected that the enable signal corresponding to the third general input / output interface is pulled high, triggering entry into the chip test mode;

[0016] Correspondingly, after writing the serial data into the trimming register based on the data flow direction, the method further includes:

[0017] When the serial data is successfully written into the trimming register, the enable signal corresponding to the third general input / output interface is pulled low.

[0018] Optionally, the chip trimming function testing method further includes:

[0019] respectively setting a flag bit of a first preset byte length, a data bit of a second preset byte length, and an address bit of a third preset byte length;

[0020] The preset data format is determined by the flag bit, the data bit and the address bit in sequence starting from the highest bit.

[0021] Optionally, determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trim register based on the data flow direction includes:

[0022] The data flow direction of the serial data is determined according to a preset data format, and when the value corresponding to the flag bit meets a preset condition, the serial data is written into a trim register based on the data flow direction.

[0023] Optionally, after determining the data flow direction of the serial data according to a preset data format and writing the serial data into the trimming register based on the data flow direction, the method further includes:

[0024] Determining whether there is a storage instruction to write the data in the trim register into the memory;

[0025] When the storage instruction exists, the indication signal corresponding to the fourth general input / output interface is pulled high.

[0026] Optionally, the chip trimming function testing method further includes:

[0027] Monitor whether there is a trimming register to be operated;

[0028] If the trimming register to be operated currently exists, then for the trimming register to be operated, the process jumps again to the step of executing the chip test mode according to the test signal in the universal input / output interface until all data are written into the trimming register to be operated.

[0029] In a second aspect, the present application discloses a chip trimming function testing device, which is applied to automated testing equipment, comprising:

[0030] An interface configuration module, used to configure a general input / output interface for the chip to be tested;

[0031] A test execution module, used to execute a chip test mode according to a test signal in the universal input / output interface, and obtain serial data sent by the automated test equipment;

[0032] The data storage module is used to determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction.

[0033] In a third aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the chip trimming function testing method as described above.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the chip trimming function testing method as described above.

[0035] The present application provides a chip trimming function testing method, which is applied to automated testing equipment, including: configuring a universal input / output interface for a chip to be tested; executing a chip test mode according to a test signal in the universal input / output interface, and obtaining serial data sent by the automated testing equipment; determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction.

[0036] The beneficial technical effect of the present application is: by configuring the universal input / output interface of the automated test equipment, generating the corresponding input stimulus, directly writing the test data sent by the automated test equipment into the register group corresponding to the chip, simplifying the writing operation of the automated test equipment to the internal register during the test. In addition, the use of the universal input / output interface does not have strict requirements for the clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0037] In addition, the present application provides a chip trimming function testing device, equipment and storage medium, which correspond to the above-mentioned chip trimming function testing method and have the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0039] Figure 1 A flow chart of a chip trimming function testing method disclosed in this application;

[0040] Figure 2 A timing diagram of a test process disclosed in the present application;

[0041] Figure 3 A timing diagram of a test process disclosed in the present application;

[0042] Figure 4 A chip adjustment function test architecture diagram disclosed in this application;

[0043] Figure 5 A schematic diagram of a chip adjustment function test flow disclosed in this application;

[0044] Figure 6 This is a schematic diagram of the structure of a chip trimming function testing device disclosed in this application;

[0045] Figure 7 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] When the chip is trimmed on the ATE machine after tape-out, the test data on the GPIO (General-Purpose IOports) cannot be saved for use in the next ATE test, so the last test data is written into the corresponding register. The current market solutions are to write registers through various communication protocols, such as I2C (Integrated Circuit) protocol: a two-wire protocol, writing data to registers through SCL (Serial Clock) and SDA (Serial Data); SPI (Serial Peripheral Interface) protocol: a four-wire protocol, writing data to registers through SCLK clock line, CS (Chip Select), MOSI (Master Output / Slave Input), MISO (Master Input / Slave Output). Or store data in memory through BIST (Built-in Self-Test), and then load data into trim registers by powering off and then powering on.

[0048] When writing trim registers using the communication protocol, the ATE machine needs to strictly comply with the various requirements of the communication protocol itself to generate correct stimuli, such as the conditions for starting communication, the conditions for ending communication, and the timing requirements during communication, etc. Obviously, using I2C / SPI to write trim registers is still a bit complicated for ATE machines.

[0049] For BIST to write trim registers, the process requires the ATE machine to generate test signals, and then the chip is decoded and the data is stored in the memory. Note that this is stored in the memory, not directly writing the data into the trim register, which requires the chip to be powered off and then powered on to load the data into the trim register. This method is no more troublesome and increases the time cost of testing.

[0050] To this end, the present application provides a chip trimming function testing solution that can simplify the testing process and shorten the testing time.

[0051] The embodiment of the present invention discloses a chip trimming function testing method, see Figure 1 As shown, applied to automated testing equipment, the method includes:

[0052] Step S11: configuring a general input / output interface for the chip to be tested.

[0053] In the embodiment of the present application, GPIO is configured by the ATE machine to generate corresponding input stimulus. In a specific implementation, four GPIO interfaces are configured and used. Specifically, they include:

[0054] A first general input / output interface is configured for the chip to be tested; the first general input / output interface is used to provide a reference clock signal for the automated testing equipment and the chip to be tested;

[0055] A second universal input / output interface is configured for the chip to be tested; the second universal input / output interface is used to provide a test data signal;

[0056] A third general input / output interface is configured for the chip to be tested; the third general input / output interface is used to provide an enable signal for the chip test mode;

[0057] A fourth general input / output interface is configured for the chip to be tested; the fourth general input / output interface is used to provide an indication signal for the trimming register to indicate whether to store data in a memory.

[0058] Table 1 shows the test signals and function descriptions corresponding to the four GPIO interfaces:

[0059] Table 1

[0060]

[0061] Step S12: Execute a chip test mode according to the test signal in the universal input / output interface, and obtain serial data sent by the automatic test equipment.

[0062] In the embodiment of the present application, when the ATE tester pulls Ten high, it will enter the chip test mode. Specifically, if it is detected that the enable signal corresponding to the third general input / output interface is pulled high, it triggers the entry into the chip test mode. It should be pointed out that after entering the chip test mode, a Tclk reference clock signal is given, and there is no great requirement for the clock rate, and the clock frequency can be selected arbitrarily.

[0063] For example, Figure 2 , Figure 3 The following is a timing diagram based on the GPIO interface. Figure 2 In the , Data_in and addr_in are the address and data to be input to the chip, which will be converted to Tdata; data_o and addr_o are the data obtained after the chip decodes. When Ten becomes 0, R is cleared and the function will be reset. Figure 3 In the example, when unlock becomes 1, the data is automatically written into the memory. According to the content in the figure, during the period when the enable signal Ten is pulled high, the test data signal Tdata transmits data according to the rising and falling edges provided by the reference clock signal Tclk, and there is no strict timing requirement.

[0064] Step S13: determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trim register based on the data flow direction.

[0065] In the embodiment of the present application, the ATE sends the serial data for testing, and the data is transmitted according to the data flow direction. The data flow direction is determined based on a preset data format, and the ATE machine must follow the preset data format when sending the serial data.

[0066] In a specific implementation, the specific process of determining the preset data format includes: respectively setting a flag bit of a first preset byte length, a data bit of a second preset byte length, and an address bit of a third preset byte length; starting from the highest bit, determining the preset data format in sequence through the flag bit, the data bit, and the address bit.

[0067] Table 2 shows the preset data format, where the format is as follows, starting from the high bit: 1 bit flag bit R, N bits data bit S, and M bits address bit T.

[0068] Table 2

[0069]

[0070] Among them, the flag bit R is a flag bit used to characterize the start of data transmission. It should be pointed out that after the data flow direction of the serial data is determined according to the preset data format, the step of writing the serial data into the trim register based on the data flow direction can be triggered only when and only when the value corresponding to the flag bit meets the preset conditions. For example, the value of the R bit must be 1, indicating that the data starts to be sent. For the receiver, the highest bit of the register group receives the flag bit signal, and the data will be locked until the Ten signal is invalid and unlocked. That is, the data of the R bit represents the start (for ATE) / end (for the chip) of the data. In this way, the automatic locking of the R bit can effectively avoid confusion in the data flow.

[0071] The data bit S is used to represent the data to be written into the trim register; the address bit T is used to represent the trim register address.

[0072] Furthermore, when the serial data is written into the trim register based on the data flow direction, the data flow direction is: R->S highest bit...->S lowest bit->T highest bit...->T lowest bit. Figure 4 The figure shows a schematic diagram of the writing operation architecture of the internal register / memory during the test of the ATE machine.

[0073] It should be noted that after the data is successfully written into the trim register, Ten is pulled low. Specifically, when the serial data is successfully written into the trim register, the enable signal corresponding to the third general input / output interface is pulled low.

[0074] In the embodiment of the present application, the aforementioned steps are repeatedly performed for all trim registers that need to be operated until all trim registers that need to be operated are written. Specifically, it is monitored whether there are trim registers to be operated; if there are trim registers to be operated, the step of executing the chip test mode according to the test signal in the universal input / output interface is jumped again for the trim registers to be operated until all the trim registers to be operated are written with data.

[0075] In addition, in a feasible implementation, if the data in the trim register needs to be written into the memory, unlock can be pulled high. If not, this step is not performed. Specifically, it is determined whether there is a storage instruction to write the data in the trim register into the memory; when the storage instruction exists, the indication signal corresponding to the fourth general input / output interface is pulled high. In this way, the writing operation of the ATE machine to the memory during testing can also be simplified.

[0076] like Figure 5 The figure shows the steps of chip trim function test. The process starts with ATM (Analog test mode) test, and then writes the data in ATM test mode directly into the corresponding Trim register through GPIO port. In this process, all registers that need to be operated are judged until all trim registers that need to be operated are written. If the data in trim register needs to be written into memory, just pull unlock high. If not, do not execute this step. The process ends.

[0077] The present application provides a chip trimming function testing method, which is applied to automated testing equipment, including: configuring a universal input / output interface for a chip to be tested; executing a chip test mode according to a test signal in the universal input / output interface, and obtaining serial data sent by the automated testing equipment; determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction.

[0078] The beneficial technical effect of the present application is: by configuring the universal input / output interface of the automated test equipment, generating the corresponding input stimulus, directly writing the test data sent by the automated test equipment into the register group corresponding to the chip, simplifying the writing operation of the automated test equipment to the internal register during the test. In addition, the use of the universal input / output interface does not have strict requirements for the clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0079] Correspondingly, the present application also discloses a chip trimming function test device, which is applied to automated testing equipment, see Figure 6 As shown, the device comprises:

[0080] An interface configuration module 11, used to configure a general input / output interface for the chip to be tested;

[0081] A test execution module 12, configured to execute a chip test mode according to a test signal in the universal input / output interface and obtain serial data sent by the automated test equipment;

[0082] The data storage module 13 is used to determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction.

[0083] Among them, for more specific working processes of the above-mentioned modules, please refer to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0084] It can be seen that the above-mentioned scheme of this embodiment is applied to automated testing equipment, including: configuring a universal input / output interface for the chip to be tested; executing a chip test mode according to a test signal in the universal input / output interface, and obtaining serial data sent by the automated testing equipment; determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trim register based on the data flow direction.

[0085] The beneficial technical effect of the present application is: by configuring the universal input / output interface of the automated test equipment, generating the corresponding input stimulus, directly writing the test data sent by the automated test equipment into the register group corresponding to the chip, simplifying the writing operation of the automated test equipment to the internal register during the test. In addition, the use of the universal input / output interface does not have strict requirements for the clock rate and timing, which can effectively improve the test speed, shorten the test time, and avoid the inconvenience caused by various protocol specifications.

[0086] Furthermore, the present application also discloses an electronic device. Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment, and the content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0087] Figure 7 The present invention is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip trimming function test method disclosed in any of the aforementioned embodiments.

[0088] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0089] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222 and data 223, etc. The data 223 may include various data. The storage method may be temporary storage or permanent storage.

[0090] The operating system 221 is used to manage and control the hardware devices and computer program 222 on the electronic device 20, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the chip trimming function test method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0091] Furthermore, the embodiments of the present application also disclose a computer-readable storage medium, wherein the computer-readable storage medium mentioned here includes a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a magnetic disk or an optical disk, or any other form of storage medium known in the technical field. Wherein, when the computer program is executed by the processor, the aforementioned chip trimming function test method is implemented. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0092] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0093] The steps of the chip trimming function test method or algorithm described in conjunction with the embodiments disclosed herein can be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0094] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The above is a detailed introduction to a chip trimming function testing method, device, equipment and medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A chip trimming function testing method, characterized in that: Applied to automated test equipment, including: Configure the general input / output interface for the chip to be tested; Execute a chip test mode according to a test signal in the universal input / output interface, and obtain serial data sent by the automated test equipment; The data flow direction of the serial data is determined according to a preset data format, and the serial data is written into a trim register based on the data flow direction.

2. The chip trimming function testing method according to claim 1, characterized in that: The step of configuring a general input / output interface for the chip to be tested includes: A first general input / output interface is configured for the chip to be tested; the first general input / output interface is used to provide a reference clock signal for the automated testing equipment and the chip to be tested; A second universal input / output interface is configured for the chip to be tested; the second universal input / output interface is used to provide a test data signal; A third general input / output interface is configured for the chip to be tested; the third general input / output interface is used to provide an enable signal for the chip test mode; A fourth general input / output interface is configured for the chip to be tested; the fourth general input / output interface is used to provide an indication signal for the trimming register to indicate whether to store data in a memory.

3. The chip trimming function testing method according to claim 2, characterized in that: The step of executing a chip test mode according to a test signal in the universal input / output interface comprises: If it is detected that the enable signal corresponding to the third general input / output interface is pulled high, triggering entry into the chip test mode; Correspondingly, after writing the serial data into the trimming register based on the data flow direction, the method further includes: When the serial data is successfully written into the trimming register, the enable signal corresponding to the third general input / output interface is pulled low.

4. The chip trimming function testing method according to claim 1, characterized in that: Also includes: respectively setting a flag bit of a first preset byte length, a data bit of a second preset byte length, and an address bit of a third preset byte length; The preset data format is determined by the flag bit, the data bit and the address bit in sequence starting from the highest bit.

5. The chip trimming function testing method according to claim 4, characterized in that: Determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trim register based on the data flow direction, including: The data flow direction of the serial data is determined according to a preset data format, and when the value corresponding to the flag bit meets a preset condition, the serial data is written into a trim register based on the data flow direction.

6. The chip trimming function testing method according to claim 2, characterized in that: After determining the data flow direction of the serial data according to a preset data format and writing the serial data into a trimming register based on the data flow direction, the method further includes: Determining whether there is a storage instruction to write the data in the trim register into the memory; When the storage instruction exists, the indication signal corresponding to the fourth general input / output interface is pulled high.

7. The chip trimming function testing method according to any one of claims 1 to 6, characterized in that: Also includes: Monitor whether there is a trimming register to be operated; If the trimming register to be operated currently exists, then for the trimming register to be operated, the process jumps again to the step of executing the chip test mode according to the test signal in the universal input / output interface until all data are written into the trimming register to be operated.

8. A chip trimming function testing device, characterized in that: Applied to automated test equipment, including: An interface configuration module, used to configure a general input / output interface for the chip to be tested; A test execution module, used to execute a chip test mode according to a test signal in the universal input / output interface, and obtain serial data sent by the automated test equipment; The data storage module is used to determine the data flow direction of the serial data according to a preset data format, and write the serial data into the trimming register based on the data flow direction.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory; wherein the memory is used to store a computer program, and the computer program is loaded and executed by the processor to implement the chip trimming function testing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein the computer program, when executed by a processor, implements the chip trimming function testing method as described in any one of claims 1 to 7.

Images