Task scheduling method and device, equipment and medium

Abstract

The invention discloses a task scheduling method and device, equipment and a medium, and relates to the technical field of chips. The task scheduling method is executed by a TDU and comprises the steps of obtaining a target task descriptor based on a main core doorbell triggering behavior; when it is determined that the target task descriptor meets a descriptor sending condition, generating a task issuing request according to the target task descriptor; and arbitrating the task issuing request based on the target arbiter to obtain a request arbitration result, and performing task distribution according to the request arbitration result. According to the technical scheme provided by the embodiment of the invention, the tasks can be directly distributed without using a core, and the operation complexity of task scheduling is also reduced while the delay between the tasks is reduced.

Description

Technical Field

[0001] The present invention relates to the field of AI chip technology, and in particular to a task scheduling method, device, equipment and medium. Background Art

[0002] With the rapid development of the Internet era, the AI ​​(Artificial Intelligence) field has an increasing demand for high-speed processing of large model calculations and complex model derivation, which has led to the emergence of high-performance AI computing chips. Such chips often use a multi-core architecture, with different cores processing different tasks, which can significantly improve computing efficiency.

[0003] At present, the task scheduling of chips is mainly realized by software scheduling, that is, a core is used for task detection and management. The core is responsible for task allocation, status query and algorithm, etc. It needs to constantly query the completion status of the execution unit and cannot handle other matters during task execution. In addition, the core detects and dispatches tasks, which will cause large task time delays. In addition, there are some scheduling technologies that calculate which execution unit a task is submitted to based on the resources and threads of the execution unit, or the execution time of each execution unit, and finally dispatch the task by the core, which has a high degree of software operation complexity. Summary of the invention

[0004] The present invention provides a task scheduling method, device, equipment and medium to solve the problems of large delay between tasks and high operation complexity in software-implemented task scheduling in AI chips.

[0005] According to one aspect of the present invention, a task scheduling method is provided, which is executed by a TDU, and includes: Based on the doorbell triggering behavior of the main core, obtain the target task descriptor; When it is determined that the target task descriptor meets the descriptor sending condition, a task sending request is generated according to the target task descriptor; Issue a request based on the target arbitrator arbitration task, obtain the request arbitration result, and dispatch tasks according to the request arbitration result; According to the arbitration result of the request, tasks are assigned, including: When the arbitration result of the request is to support task dispatching, and it is determined that there is a target chip number and / or a target core number according to the task dispatching request, dispatching the task to the target scheduled unit based on the target chip number and / or the target core number; When the arbitration result is that task dispatch is not supported, determine and save the tasks that have not been dispatched by arbitration; shield the subsequent scheduling requests of the target scheduled unit, and shield the target arbitrator to wait until the status of the target scheduled units are all changed to idle before dispatching tasks.

[0006] Optionally, before issuing a request based on the arbitration task of the target arbitrator and obtaining the requested arbitration result, the following is further included: Obtain the status data of the scheduled unit; When it is determined based on the scheduled unit status data that at least one target scheduled unit is idle, a task issuing request is sent to the target arbitrator.

[0007] Optionally, a request is issued based on the arbitration task of the target arbitrator to obtain the arbitration result of the request, including: When the state of the target scheduled unit is idle, the request arbitration result is obtained that the target scheduled unit supports task dispatching; When the sending granularity of the task sending request is not a single granularity and the target scheduled unit status is not all idle, the request arbitration result is that the target scheduled unit does not support task dispatching.

[0008] Optionally, wait until the status of all target scheduling units changes to idle before dispatching tasks, including: Determine the dispatch order of tasks that have not been dispatched by arbitration in the order of dispatch granularity from small to large; When the states of the target scheduled units corresponding to the target tasks not issued by the current arbitration are all changed to idle, tasks are dispatched to the target scheduled units corresponding to the target tasks not issued by the current arbitration.

[0009] Optionally, according to the arbitration result of the request, the task is assigned, which also includes: When it is determined that the target chip number and the target core number are not specified according to the task issuing request, a currently idle scheduled unit is identified based on the scheduled unit state data; Selecting a target scheduled unit from the currently idle scheduled units to dispatch tasks to the target scheduled unit; The target scheduled unit includes: a communication core, and / or a computing core group.

[0010] Optionally, when it is determined that the target task descriptor meets the descriptor sending condition, a task sending request is generated according to the target task descriptor, including: When the target task descriptor is a cross-chip type descriptor, the target task descriptor is sent to the slave chip task scheduling unit so that the slave chip task scheduling unit performs task dispatching; Obtain task completion write-back data from the chip task scheduling unit, and write the task completion write-back data into the main memory.

[0011] According to another aspect of the present invention, there is provided a task scheduling device, which is configured in a TDU and includes: A descriptor acquisition module is used to obtain the target task descriptor based on the doorbell triggering behavior of the main core; A task sending request generating module is used to generate a task sending request according to the target task descriptor when it is determined that the target task descriptor meets the descriptor sending condition; The task issuing module is used to issue a request based on the target arbitrator arbitration task, obtain the request arbitration result, and perform task dispatch according to the request arbitration result; The task dispatching module is specifically used to dispatch tasks to the target scheduled unit based on the target chip number and / or the target core number when the arbitration result of the request is to support task dispatching and it is determined that there is a target chip number and / or a target core number according to the task dispatching request; when the arbitration result of the request is not to support task dispatching, determine and save the tasks that have not been dispatched by arbitration; shield the subsequent scheduling requests of the target scheduled unit, and shield the target arbitrator to wait until the status of the target scheduled units are all changed to idle before dispatching tasks.

[0012] According to another aspect of the present invention, there is provided an electronic device, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the task scheduling method described in any embodiment of the present invention.

[0013] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the task scheduling method described in any embodiment of the present invention when executed.

[0014] The technical solution of the embodiment of the present invention obtains the target task descriptor based on the doorbell triggering behavior of the main core, so that when it is determined that the target task descriptor meets the descriptor sending condition, a task issuing request is generated according to the target task descriptor, and then the arbitration task issuing request is based on the target arbitrator to obtain the request arbitration result, and the task is dispatched according to the request arbitration result. In this solution, task scheduling is implemented by hardware, the chip core is liberated, and when the chip is integrated with multiple sub-chips, the consistency problem between the main core and the slave core is simplified to between the main core and the TDU. When the TDU is used for scheduling, the delay between tasks can be significantly reduced, and the core does not need to be directly responsible for dispatching tasks. It only needs to adjust tasks and handle exceptions according to the feedback task status after configuring the TDU, which can reduce the complexity of software operation, solve the problem of large delay between tasks and high operation complexity in the task scheduling in the chip implemented by software, and can dispatch tasks directly without using the core, while reducing the delay between tasks and reducing the operation complexity of task scheduling.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flowchart of a task scheduling method provided in Embodiment 1 of the present invention.

[0018] Figure 2 A flowchart of a task scheduling method provided in Embodiment 2 of the present invention.

[0019] Figure 3 A schematic diagram of a cross-chip task scheduling process provided in Embodiment 2 of the present invention.

[0020] Figure 4 A schematic diagram of data flow for task scheduling at a multi-core group granularity provided in the second embodiment of the present invention.

[0021] Figure 5 A schematic diagram of arbitration logic for multi-task sending requests provided in Embodiment 2 of the present invention.

[0022] Figure 6 A structural diagram of a task scheduling device provided in Embodiment 3 of the present invention.

[0023] Figure 7 A schematic diagram of the structure of an electronic device that can be used to implement an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the term "target" and the like in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] Embodiment 1: Figure 1 This is a flowchart of a task scheduling method provided in Embodiment 1 of the present invention. This embodiment is applicable to task scheduling of a single AI chip and multiple AI chips. The method can be executed by a task scheduling device. The task scheduling device can be implemented in the form of hardware and / or software. The task scheduling device can be configured in an electronic device. Figure 1 As shown, the method includes: Step 110: Based on the doorbell triggering behavior of the main core, obtain the target task descriptor.

[0027] Among them, the main core doorbell triggering behavior can be a doorbell operation performed by the main core of the integrated chip to the TDU (Task Dispatch Unit). TDU can receive task requests from the upper-level unit, parse the task requests, and schedule tasks according to the type, priority, core group resources and other information of the task, becoming an important component in the multi-core system. Multiple chips (can be referred to as die) can be integrated in the integrated chip. The main core in the integrated chip can start the TDU by ringing the doorbell and is responsible for writing the task descriptor to the main memory. The target task descriptor can be the task descriptor currently written to the main memory by the main core. Exemplarily, the target task descriptor is a string of data, including but not limited to the task type, task description field, and task granularity.

[0028] In the embodiment of the present invention, the main core of the chip can write the target task descriptor into the main memory, and start the TDU by ringing the doorbell, so that the TDU can actively read the target task descriptor from the main memory.

[0029] Optionally, the main memory may store the target task descriptor in a local task queue, waiting for the TDU to read it. After the TDU reads the target task descriptor, it stores it in its own pre-stored queue.

[0030] Exemplarily, the TDU can use multiple pre-fetch queues to store target task descriptors. Specifically, the TDU can store the current target task descriptor in a pre-storage queue corresponding to the number of the current doorbell pressed by the main core to facilitate the handling of abnormal situations.

[0031] Step 120: When it is determined that the target task descriptor meets the descriptor sending condition, a task sending request is generated according to the target task descriptor.

[0032] The descriptor sending condition may be a preset condition for sending the target task descriptor. The task sending request may be a request for sending a task to a scheduled unit in the chip.

[0033] In an embodiment of the present invention, the acquired descriptor sending conditions can be pre-configured in the TDU, so that after parsing the target task descriptor, it is determined whether the target task descriptor meets the descriptor sending conditions, and then when it is determined that the target task descriptor meets the descriptor sending conditions, a task sending request is generated according to the target task descriptor.

[0034] Step 130: Issue a request based on the target arbitrator arbitration task, obtain the request arbitration result, and distribute the task according to the request arbitration result.

[0035] The target arbitrator may be a component set inside the TDU to arbitrate whether a task sending request is passed. Optionally, there are multiple target arbitrators set inside the TDU, and the specific number is consistent with the number of scheduled units, that is, each scheduled unit corresponds to a target arbitrator. Exemplarily, the target arbitrators corresponding to the same type of scheduled units in a chip can be integrated into one arbitrator. The arbitration result of the request may be the arbitration result of the target arbitrator on the task sending request.

[0036] In an embodiment of the present invention, the task issuance request can be arbitrated based on the target arbitrator, and the request arbitration result can be output, so that the task corresponding to the task issuance request can be issued according to the request arbitration result, or the request arbitration result can be temporarily saved and the task can be issued when the task issuance conditions are met.

[0037] Optionally, TDU supports in-order delivery and out-of-order submission, that is, TDU can read the descriptors in the task queue, parse and deliver them in order, and when the subsequent task ends, it can write the answer word to the main memory without the need for the previous task in the same queue to end.

[0038] The technical solution of the embodiment of the present invention obtains the target task descriptor based on the doorbell triggering behavior of the main core, so that when it is determined that the target task descriptor meets the descriptor sending condition, a task issuing request is generated according to the target task descriptor, and then the arbitration task issuing request is based on the target arbitrator to obtain the request arbitration result, and the task is dispatched according to the request arbitration result. In this scheme, task scheduling is implemented by hardware to liberate the chip core, and when the chip is integrated with multiple sub-chips, the consistency problem between the main core and the slave core is simplified to between the main core and the TDU. When the TDU is used for scheduling, the delay between tasks can be significantly reduced. The core does not need to be directly responsible for dispatching tasks. It only needs to adjust tasks and handle exceptions according to the feedback task status after configuring the TDU, which can reduce the complexity of software operation, solve the problem of large delay between tasks and high operation complexity in the software implementation of task scheduling in AI chips, and can dispatch tasks directly without using the core, reducing the delay between tasks while also reducing the operational complexity of task scheduling.

[0039] Embodiment 2: Figure 2 This is a flowchart of a task scheduling method provided in the second embodiment of the present invention. This embodiment is specific based on the above embodiment and provides a specific optional implementation method of sending a task issuance request to the target arbitrator before obtaining the arbitration result of the request based on the arbitration task issuance request of the target arbitrator. Figure 2 As shown, the method includes: Step 210: Based on the doorbell triggering behavior of the main core, obtain the target task descriptor.

[0040] Step 220: When it is determined that the target task descriptor meets the descriptor sending condition, a task sending request is generated according to the target task descriptor.

[0041] Step 230: Obtain status data of the scheduled unit.

[0042] The scheduled unit status data may be used to characterize the status of the scheduled unit in the chip. For example, the status of the scheduled unit may be busy or idle.

[0043] In the embodiment of the present invention, the status of the scheduled unit can be monitored in real time to obtain the status data of the scheduled unit.

[0044] Step 240: When it is determined based on the scheduled unit status data that at least one target scheduled unit is idle, a task delivery request is sent to the target arbitrator.

[0045] The target scheduled unit may be a scheduled unit to which the task corresponding to the target task descriptor needs to be sent.

[0046] In an embodiment of the present invention, the state of the scheduled unit in the chip can be determined through the scheduled unit state data to further determine the state of the target scheduled unit. When a task needs to be sent to multiple target scheduled units and at least one target scheduled unit is idle, it can be determined that the task sending request can participate in arbitration, and then the task sending request is sent to the target arbitrator.

[0047] Step 250: Issue a request based on the arbitration task of the target arbitrator, obtain the request arbitration result, and distribute the task according to the request arbitration result.

[0048] In an optional embodiment of the present invention, obtaining a request arbitration result based on the target arbitrator arbitration task issuance request may include: when the state of the target scheduled unit is idle, obtaining the request arbitration result is that the target scheduled unit supports task dispatching; when the issuance granularity of the task issuance request is not a single granularity, and the state of the target scheduled unit is not all idle, obtaining the request arbitration result is that the target scheduled unit does not support task dispatching.

[0049] In an embodiment of the present invention, the granularity of the target scheduled unit may be a single granularity or a non-single granularity (i.e., multiple granularities). When the granularity of the target scheduled unit is a single granularity, it indicates that the number of target scheduled units is one. When the state of this target scheduled unit is idle, the request arbitration result of the target arbitrator is that the target scheduled unit supports task dispatching. When the granularity of the target scheduled unit is a non-single granularity, it indicates that the number of target scheduled units is multiple. When the states of the target scheduled units are all idle, the request arbitration result of the target arbitrator is that the target scheduled unit supports task dispatching. When the sending granularity of the task sending request is not a single granularity, and the states of the target scheduled units are not all idle, the request arbitration result of the target arbitrator is that the target scheduled unit does not support task dispatching.

[0050] In an optional embodiment of the present invention, task dispatching is performed according to the result of request arbitration, which may include: when the result of request arbitration is to support task dispatching, and according to the task issuance request, when it is determined that there is a target chip number and / or a target core number, dispatching the task to the target scheduled unit based on the target chip number and / or the target core number; when the result of request arbitration is not to support task dispatching, determining and saving the tasks that have not been issued by arbitration; shielding subsequent scheduling requests of the target scheduled unit, and shielding the target arbitrator to wait until the status of the target scheduled units are all changed to idle before dispatching the task.

[0051] The target chip number may be the chip number to which the task needs to be sent. The target core number may be the core number of the communication core in the chip to which the task needs to be sent. The arbitration unsent task may be a task that cannot be sent when the target called unit is busy.

[0052] In an embodiment of the present invention, if the result of the request arbitration is to support task dispatching, the task dispatching request is parsed to obtain the target chip number and / or the target core number, and then based on the target chip number and / or the target core number, the corresponding target called unit is identified, and the task corresponding to the task dispatching request is dispatched to the target scheduled unit. If the result of the request arbitration is not to support task dispatching, the task that cannot be dispatched at present is regarded as an arbitration undispatched task and is saved, thereby shielding the subsequent dispatching request of the target scheduled unit, and the corresponding arbitrator will no longer arbitrate until the state of the target scheduled unit is changed to idle, and then the task is dispatched to the target called unit.

[0053] In an optional embodiment of the present invention, waiting for the states of all target scheduled units to change to idle before performing task dispatching may include: determining the dispatching order of the tasks not dispatched by arbitration in the order of dispatching granularity from small granularity to large granularity; and dispatching tasks to the target scheduled units corresponding to the target tasks not dispatched by the current arbitration when the states of all target scheduled units corresponding to the target tasks not dispatched by the current arbitration are changed to idle.

[0054] The target task that has not been issued by arbitration at present may be a task that can be issued currently among the tasks that have not been issued by arbitration.

[0055] In an embodiment of the present invention, the order of issuing granularity from small granularity to large granularity (i.e., single granularity, double granularity, triple granularity, ...) can be used as the dispatching order of the arbitration unissued tasks to guide the dispatching of the arbitration unissued tasks in sequence. After determining the current arbitration unissued target task, wait for the target scheduled units corresponding to the current arbitration unissued target task to change to idle status, and then dispatch tasks to the target scheduled units corresponding to the current arbitration unissued target task.

[0056] In an optional embodiment of the present invention, task dispatching is performed according to the request arbitration result, and may also include: when it is determined that the target chip number and the target core number are not specified according to the task issuance request, the current idle scheduled unit is identified based on the scheduled unit status data; a target scheduled unit is selected from the current idle scheduled unit to dispatch the task to the target scheduled unit; wherein the target scheduled unit may include: a communication core, and / or a computing core group.

[0057] The currently idle scheduled unit may be a scheduled unit that is currently idle. The communication core may be a component in a chip that performs data processing transactions, and the transmission mode is unicast. The computing core group may be an array composed of multiple cores for data computing, and the transmission mode is broadcast.

[0058] In an embodiment of the present invention, the task issuance request can be parsed to determine whether the target chip number and the target core number are specified in the target task descriptor. If the target chip number and the target core number are not specified, the current idle scheduled unit can be further determined through the scheduled unit status data, and then the target scheduled unit can be selected from the current idle scheduled unit to dispatch the task to the target scheduled unit.

[0059] In an optional embodiment of the present invention, when it is determined that the target task descriptor satisfies the descriptor sending conditions, a task dispatching request is generated according to the target task descriptor, which may include: when the target task descriptor is a cross-chip type descriptor, sending the target task descriptor to the slave chip task scheduling unit to dispatch the task in the slave chip task scheduling unit; obtaining the task completion write-back data from the slave chip task scheduling unit, and writing the task completion write-back data into the main memory.

[0060] The cross-chip type descriptor may be a task descriptor that needs to be transmitted across chips. The slave chip task scheduling unit may be a task scheduling unit in the slave chip. In the integrated chip, one of the multiple sub-chips may be selected as the master chip, and the other chips may be selected as slave chips. The task completion write-back data may be the write-back data of the task execution result of the slave chip task scheduling unit.

[0061] In an embodiment of the present invention, the type of the acquired target task descriptor can be judged. If the target task descriptor is a cross-chip type descriptor, the target task descriptor is sent to the slave chip task scheduling unit, and then the task is dispatched through the slave chip task scheduling unit. The slave chip task scheduling unit executes the dispatched task and records the execution result, generates task write-back data, and feeds it back to the TDU of the master chip. The TDU of the master chip writes the task completion write-back data into the main memory. The working principle of the TDU in the slave chip is the same as that of the master chip TDU, which will not be repeated here.

[0062] In a specific example, the flowchart of cross-chip task scheduling is as follows: Figure 3 As shown. Figure 3 As shown, the integrated chip has two dies, each of which has a TDU. The main core of the main die is responsible for configuring and starting the TDU. The main TDU reads and dispatches descriptors, and can dispatch tasks to the communication core and computing core group of the die. The tasks of the slave die are dispatched to the corresponding communication core and computing core group by sending the complete task descriptor information to the slave TDU, that is, TDU (agent). When the task of the slave die is completed, the slave TDU sends the answer word to the main TDU for further processing, and then the main TDU writes it back to the main memory space of the main die.

[0063] For example, there are multiple pre-fetch queues in the TDU responsible for storing descriptors, multiple arbitrators responsible for arbitration, and multiple distribution modules responsible for sending the arbitrated tasks to the corresponding computing core groups or communication cores. The TDU supports multi-core group granularity scheduling, and can dispatch the same task to multiple core groups or cores. After all computing core groups or communication cores have completed, the corresponding task status will be written to the answer word, and the answer word will be written back to the main memory.

[0064] TDU supports the main core to specify the computing core group or communication core in which the TDU sends the task by filling in the die number (i.e., target chip number) and target core number in the descriptor. TDU also supports not specifying a specific die number or target core number in the task descriptor. TDU selects a core group or core for task dispatch based on the idle state of the computing core group and the communication core. For multi-granularity task scheduling, the die number can be not specified, and tasks can be dispatched based on the idle state of each die.

[0065] For example, if each integrated chip has two dies, and each die has one computing core group and two communication cores, the task scheduling data flow at the multi-core group granularity is as follows: Figure 4 As shown. Figure 4 As shown, TDU reads the target task descriptor locally according to the doorbell number, completes the task prefetch, and further stores it in the prefetch queue for storage, thereby parsing the bit field information (task granularity and task type, etc.) of the target task descriptor, and then determines whether the target task descriptor meets the sending conditions (such as whether the core group is idle, blocking in the queue, dependencies, etc.). When the sending conditions are met, it determines whether the task is dispatched to the computing core group or the communication core according to the task type. If the task type is computing, the task is executed by the computing core group, and TDU determines which core group to send it to based on the die number. If the task type is communication, the task is executed by the communication core, and TDU determines which communication core to send it to based on the die number and the target core number, and then the corresponding queue sends a request to the corresponding arbitrator, and the core arbitrator selects the task and sends it to the corresponding communication core, or the core group arbitrator selects the task and sends it to the corresponding computing core group. When TDU sends tasks, there are several situations: there are 7 situations for dispatching communication cores, including communication core 0 of the master die, communication core 1 of the master die, communication core 0 of the slave die, communication core 1 of the slave die, two communication cores of the master die, two cores of the slave die, and four cores of all dies. There are 3 situations for dispatching computing core groups, including the computing core group of the master die, the computing core group of the slave die, and two computing core groups of all dies. The corresponding relationship between the scheduled unit and the distribution module can be seen in Figure 4 .

[0066] For example, a die number of 00 means no die is specified and the task can be executed in any unit of a die, 01 means die0, 10 means die1, and 11 means both die are executed. A target core number of 00 means no specific communication core is specified and any communication core can be selected to dispatch the task, 01 means specifying communication core 0, 10 means specifying communication core 1, and 11 means both communication cores in a die are executed.

[0067] In a specific example, there are two types of multi-core granularities, namely, a two-core granularity with two communication cores in one die as a group, and a four-core granularity with four cores of all dies as a group.

[0068] Requests of each granularity can participate in arbitration when at least one of the cores in the corresponding group class is idle (multiple cores in a group of n cores are not all busy), and send the task issuance request to the corresponding target arbitrator for arbitration. When the arbitrated multi-granularity request targets (i.e., target communication cores) are all idle, TDU directly sends the task. When the arbitrated multi-granularity request targets are not all idle, TDU will temporarily save the arbitration result and generate a shielding signal to shield the requests within the range. The corresponding arbitrator will no longer arbitrate and wait until the corresponding cores are all idle to issue tasks. When a core is busy, TDU will no longer arbitrate single-core requests to the core, but will only continue to arbitrate requests from other cores. TDU temporarily saves up to three arbitration results, namely the two communication cores of the current die, the two cores of the slave die, and four core granularities. The order of issuing the corresponding arbitration unissued tasks is: first check whether the two-core granularity with a smaller granularity is saved, and then issue the two-core granularity task. When all four cores are idle, send the four-core task, until all saved granularities are issued, and then new requests can continue to be arbitrated.

[0069] The TDU in this solution is configured with multiple groups of arbitrators and distribution modules. Each computing core group or communication core corresponds to an arbitrator and distribution module, which can ensure the fairness of arbitration and record the status of each computing core group or communication core separately. TDU will not read a queue descriptor at the same time, but can read different queues at the same time.

[0070] Figure 5 This is a schematic diagram of arbitration logic for multi-task request issuance provided by Embodiment 2 of the present invention. Figure 5 As shown in the figure, TDU receives multiple task dispatching requests and parses the corresponding task descriptors. The execution order of the arbitration results is ①→②→③→④. The specific contents are as follows: ① is the first arbitrated: the single-core request of the communication core 0 of the main die. The TDU detects that the core is idle and directly dispatches the tasks of the queue to the communication core 0 of the main die, and then no longer accepts the single-core group request of the communication core 0 of the main die.

[0071] ② The second arbitration: from the single core request of the communication core 0 of the die, TDU directly issues the task and then no longer accepts tasks from this core group.

[0072] ③ is the third arbitration: the two-core request of the main die. At this time, communication core 0 is busy and communication core 1 is idle. TDU saves the request and no longer accepts the request of the main die. It dispatches tasks when both cores are idle.

[0073] ④ is the fourth arbitration: four core requests from all dies. At this time, the communication core 1 from the die is idle and not all cores are busy. TDU saves the four-core request and no longer accepts any request. After the previous two core requests are completed and all cores are idle, the four-core task is dispatched to all cores.

[0074] This solution supports specifying a specific computing core group or not specifying a computing core group. When not specified, TDU will allocate it according to the idle state of the computing core group, and the scheduling is flexible. Fairness between multi-granularity and single-granularity request arbitration. When computing core group 0 or core 0 are both idle, multi-granularity and single-granularity requests compete fairly. The arbitration result is obtained by the arbitrator, and there will be no starvation of one party or unfair arbitration. Use multiple groups of arbitrators to arbitrate requests from different core groups or cores to protect the internal state of the arbitration. When a single communication core group or computing core is idle, after arbitrating multiple granularity requests, the previous result will not be arbitrated again. Cross-die management, treat the core groups or cores of multiple dies as one device and schedule them uniformly. There are multiple distribution modules in the TDU in the main die, which can manage the core groups or cores inside and outside the die and record the information of related tasks.

[0075] Each computing core group or communication core is configured with a distribution module to better manage the internal state and record the execution time and some information. The task descriptor does not specify the specific core group or core to be executed, and can be dispatched according to the idle state, which improves the utilization of the core group. All computing core groups or communication cores in multiple dies are uniformly scheduled to improve utilization and expand the application scenarios compared with single-granularity scheduling.

[0076] The number of dies, number of computing core groups, core groups or core types used in the embodiments of the present invention are not fixed and may be adjusted according to the solution. The number of corresponding arbitrators and distribution modules will also change when the number of core groups changes, and will not be listed one by one. The scheduling or arbitration method can be implemented in the management of the Internet of Things and multiple devices, such as multi-brain collaboration.

[0077] This solution is suitable for multi-die chips. Multi-core groups or core scheduling can achieve the concept of exposing only one device to upper-level users. All computing core groups or communication cores of multiple dies can be uniformly scheduled to better realize single-granularity and multi-granularity functions. In some cases, the single computing core group task of each die plus the collective communication core task will have lower accuracy than the multi-core group computing core group under certain algorithms.

[0078] The technical solution of the embodiment of the present invention obtains the target task descriptor based on the doorbell triggering behavior of the main core, and then generates a task issuing request based on the target task descriptor when it is determined that the target task descriptor meets the descriptor sending condition, and obtains the scheduled unit status data, and then sends a task issuing request to the target arbitrator when it is determined that there is at least one target scheduled unit idle based on the scheduled unit status data, and further arbitrates the task issuing request based on the target arbitrator to obtain the request arbitration result, and dispatches tasks according to the request arbitration result. In this solution, task scheduling is implemented by hardware, the chip core is liberated, and when the chip is integrated with multiple sub-chips, the consistency problem between the main core and the slave core is simplified to between the main core and the TDU. By using TDU for scheduling, the delay between tasks can be significantly reduced. The core does not need to be directly responsible for dispatching tasks. It only needs to adjust tasks and handle exceptions based on the feedback of task status after configuring TDU, which can reduce the complexity of software operations and solve the problems of large delays between tasks and high operational complexity in software-implemented task scheduling in AI chips. It can dispatch tasks directly without using the core, which not only reduces the delay between tasks but also reduces the operational complexity of task scheduling.

[0079] Embodiment three: Figure 6 This is a schematic diagram of the structure of a task scheduling device provided in Embodiment 3 of the present invention. Figure 6 As shown, the device comprises: A descriptor acquisition module 310, configured to acquire a target task descriptor based on the doorbell triggering behavior of the main core; The task sending request generating module 320 is used to generate a task sending request according to the target task descriptor when it is determined that the target task descriptor meets the descriptor sending condition; The task issuing module 330 is used to issue a request based on the target arbitrator's arbitration task, obtain a request arbitration result, and perform task dispatch according to the request arbitration result.

[0080] The technical solution of the embodiment of the present invention obtains the target task descriptor based on the doorbell triggering behavior of the main core, so that when it is determined that the target task descriptor meets the descriptor sending condition, a task issuing request is generated according to the target task descriptor, and then the arbitration task issuing request is based on the target arbitrator to obtain the request arbitration result, and the task is dispatched according to the request arbitration result. In this scheme, task scheduling is implemented by hardware to liberate the chip core, and when the chip is integrated with multiple sub-chips, the consistency problem between the main core and the slave core is simplified to between the main core and the TDU. When the TDU is used for scheduling, the delay between tasks can be significantly reduced. The core does not need to be directly responsible for dispatching tasks. It only needs to adjust tasks and handle exceptions according to the feedback task status after configuring the TDU, which can reduce the complexity of software operation, solve the problem of large delay between tasks and high operation complexity in the software implementation of task scheduling in AI chips, and can dispatch tasks directly without using the core, reducing the delay between tasks while also reducing the operational complexity of task scheduling.

[0081] Optionally, the task scheduling device may further include a request sending module for obtaining status data of the scheduled unit; when it is determined based on the status data of the scheduled unit that at least one target scheduled unit is idle, the task sending request is sent to the target arbitrator.

[0082] Optionally, the task issuing module 330 is specifically used to, when the state of the target scheduled unit is idle, obtain the request arbitration result that the target scheduled unit supports task dispatching; when the issuing granularity of the task issuing request is not a single granularity and the state of the target scheduled unit is not all idle, obtain the request arbitration result that the target scheduled unit does not support task dispatching.

[0083] Optionally, the task dispatching module 330 is specifically used to dispatch tasks to the target scheduled unit based on the target chip number and / or the target core number when the arbitration result of the request is to support task dispatching and, based on the task dispatching request, it is determined that there is a target chip number and / or a target core number; when the arbitration result of the request is not to support task dispatching, determine and save the tasks that have not been dispatched by arbitration; shield subsequent scheduling requests of the target scheduled unit, and shield the target arbitrator to wait until the status of the target scheduled units are all changed to idle before dispatching tasks.

[0084] Optionally, the task issuing module 330 is specifically used to determine the dispatching order of the arbitration-unissued tasks in the order of the issuing granularity from small granularity to large granularity; when the states of the target scheduled units corresponding to the current arbitration-unissued target tasks are all changed to idle, the tasks are dispatched to the target scheduled units corresponding to the current arbitration-unissued target tasks.

[0085] Optionally, the task issuing module 330 is specifically used to identify the current idle scheduled unit based on the scheduled unit status data when it is determined that the target chip number and the target core number are not specified according to the task issuing request; select the target scheduled unit from the current idle scheduled unit to dispatch the task to the target scheduled unit; wherein the target scheduled unit includes: a communication core, and / or a computing core group.

[0086] Optionally, a task dispatching request generating module 320 is specifically used to send the target task descriptor to the slave chip task scheduling unit when the target task descriptor is a cross-chip type descriptor, so as to dispatch the task in the slave chip task scheduling unit; obtain the task completion write-back data of the slave chip task scheduling unit, and write the task completion write-back data into the main memory.

[0087] The task scheduling device provided in the embodiment of the present invention can execute the task scheduling method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0088] Embodiment 4: Figure 7 A schematic diagram of an electronic device that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0089] like Figure 7 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0090] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0091] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a task scheduling method.

[0092] In some embodiments, the task scheduling method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the task scheduling method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the task scheduling method in any other appropriate manner (e.g., by means of firmware).

[0093] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0094] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0095] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0096] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0097] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0098] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of traditional physical hosts and VPS servers, which are difficult to manage and have weak business scalability.

[0099] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0100] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A task scheduling method, characterized in that: Performed by TDU, including: Based on the doorbell triggering behavior of the main core, obtain the target task descriptor; When it is determined that the target task descriptor satisfies the descriptor sending condition, generating a task sending request according to the target task descriptor; Arbitrating the task issuance request based on the target arbitrator, obtaining the request arbitration result, and dispatching the task according to the request arbitration result; According to the arbitration result of the request, tasks are assigned, including: When the arbitration result of the request is to support task dispatching, and when it is determined that there is a target chip number and / or a target core number according to the task dispatching request, dispatching the task to the target scheduled unit based on the target chip number and / or the target core number; When the arbitration result of the request is that task dispatching is not supported, determine and save the tasks that have not been dispatched by arbitration; shield the subsequent scheduling requests of the target scheduled unit, and shield the target arbitrator to wait until the states of the target scheduled units are all changed to idle before dispatching tasks.

2. The method according to claim 1, characterized in that Before issuing a request based on the target arbitrator to arbitrate the task and obtaining the request arbitration result, the method further includes: Obtain the status data of the scheduled unit; When it is determined based on the scheduled unit status data that at least one of the target scheduled units is idle, the task issuing request is sent to the target arbitrator.

3. The method according to claim 2, characterized in that The task issuing request is arbitrated based on the target arbitrator, and the request arbitration result is obtained, including: When the state of the target scheduled unit is idle, the arbitration result of the request is obtained that the target scheduled unit supports task dispatching; When the sending granularity of the task sending request is not a single granularity and the target scheduled units are not all idle, the request arbitration result is that the target scheduled unit does not support task dispatching.

4. The method according to claim 1, characterized in that: Waiting for the target scheduled units to change their states to idle before dispatching tasks, including: Determine the dispatching order of the tasks not dispatched by the arbitration according to the order of dispatching granularity from small granularity to large granularity; When the states of the target scheduled units corresponding to the target tasks not issued by the current arbitration are all changed to idle, tasks are dispatched to the target scheduled units corresponding to the target tasks not issued by the current arbitration.

5. The method according to claim 2, characterized in that: Dispatching tasks according to the arbitration result of the request, further comprising: When it is determined that the target chip number and the target core number are not specified according to the task issuing request, identifying the currently idle scheduled unit based on the scheduled unit state data; Selecting the target scheduled unit from the currently idle scheduled units to dispatch tasks to the target scheduled unit; The target scheduled unit includes: a communication core, and / or a computing core group.

6. The method according to claim 1, characterized in that When it is determined that the target task descriptor satisfies the descriptor sending condition, generating a task sending request according to the target task descriptor, including: When the target task descriptor is a cross-chip type descriptor, sending the target task descriptor to a slave chip task scheduling unit so as to perform task dispatching in the slave chip task scheduling unit; The task completion write-back data of the slave chip task scheduling unit is obtained, and the task completion write-back data is written into the main memory.

7. A task scheduling device, characterized in that: Configured in TDU, including: A descriptor acquisition module is used to obtain the target task descriptor based on the doorbell triggering behavior of the main core; A task issuing request generating module, configured to generate a task issuing request according to the target task descriptor when it is determined that the target task descriptor satisfies the descriptor sending condition; A task issuing module, used to arbitrate the task issuing request based on the target arbitrator, obtain the request arbitration result, and perform task dispatch according to the request arbitration result; The task issuing module is specifically used to issue tasks to the target scheduled unit based on the target chip number and / or the target core number when the arbitration result of the request is to support task dispatching and, according to the task issuing request, it is determined that there is a target chip number and / or a target core number; when the arbitration result of the request is not to support task dispatching, determine and save the tasks that have not been issued by arbitration; shield the subsequent scheduling requests of the target scheduled unit, and shield the target arbitrator to wait until the status of the target scheduled units are all changed to idle before dispatching tasks.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory in communication with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the task scheduling method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the task scheduling method according to any one of claims 1 to 6 when executed.

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