Method and device for keeping cache consistency of storage and calculation integrated framework

Abstract

The invention discloses a cache consistency keeping method and device for a storage and calculation integrated framework, and the method comprises the steps: firstly initializing the storage and calculation integrated framework, and building a check point in an application program in response to the starting of the application program; then obtaining a plurality of consistency operation requests at the central processing unit, combining the consistency operation requests into a first compression signature, obtaining a plurality of consistency operation requests at the storage and calculation integrated architecture, and combining the consistency operation requests into a second compression signature; when the first compressed signatures or the second compressed signatures reach the maximum number of signatures, conflict comparison is carried out on the first compressed signatures and the second compressed signatures; and finally, if a conflict exists, rolling back to a first instruction address executed by the storage and calculation integrated architecture through a check point, and if the conflict does not exist, updating a cache line in the dynamic random access memory based on the first compression signature and the second compression signature, so that the speed of keeping cache consistency in the storage and calculation integrated architecture can be effectively improved, and the cache consistency of the storage and calculation integrated architecture is ensured. And the overhead of hardware resources is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and specifically relates to a method and device for maintaining cache consistency in a storage-computing integrated architecture. Background Art

[0002] This year, with the rapid development of the Internet, computer architecture has shifted from compute-intensive to memory-intensive. In order to reduce the latency and power consumption caused by the frequent interaction of data between computing and memory, a memory-centric computing architecture, also known as the integrated computing architecture, has begun to emerge. The integrated computing architecture deploys computing units in memory units to reduce data access latency. However, when this architecture processes tasks, since each core of the central processing unit (CPU) contains its own private cache, when one core of the CPU writes data to the memory, the cache consistency mechanism must be used to update or invalidate the data copies in the caches of other cores. The application of traditional consistency protocols in the integrated computing architecture will force a large number of coherence messages to traverse the narrow processor-memory bus, which may offset the advantages of high bandwidth and low latency brought by the integrated computing architecture.

[0003] Therefore, how to improve the speed of maintaining cache consistency in a storage-computing integrated architecture and reduce resource overhead is a technical problem to be solved by technical personnel in this field. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problems of slow speed in maintaining cache consistency and large resource overhead in a storage-computing integrated architecture.

[0005] To achieve the above technical objectives, on the one hand, the present invention provides a method for maintaining cache consistency for a storage-computing integrated architecture, the method comprising:

[0006] Initialize the storage-computing architecture and establish a checkpoint in the application in response to the startup of the application;

[0007] Obtain multiple consistency operation requests at the central processing unit and combine them into a first compressed signature, obtain multiple consistency operation requests at the storage-computing integrated architecture and combine them into a second compressed signature;

[0008] When the first compressed signature or the second compressed signature reaches the maximum number of signatures, the first compressed signature and the second compressed signature are compared for conflicts;

[0009] If there is a conflict, the checkpoint is used to roll back to the address of the first instruction executed by the storage-computing integrated architecture. If there is no conflict, the cache line in the dynamic random access memory is updated based on the first compression signature and the second compression signature.

[0010] Furthermore, the initialization of the storage-computing integrated architecture specifically includes determining a logical core in the storage-computing integrated architecture for processing an application, and configuring a filtering condition for the logical core, wherein the filtering condition is used to filter out consistency operation requests that meet the condition.

[0011] Furthermore, the multiple consistency operation requests at the storage-computing integrated architecture specifically include all cache line addresses read and written by the logical core.

[0012] Furthermore, the conflict comparison specifically includes:

[0013] Decoding the first compressed signature to obtain a first address set;

[0014] The cache row addresses read by the storage-computing integrated architecture are traversed, and if at least one address in the first address set exists in the cache row addresses read by the storage-computing integrated architecture, it is determined that a conflict exists.

[0015] Further, updating the cache line in the dynamic random access memory based on the first compression signature and the second compression signature specifically includes:

[0016] Determining a first address set corresponding to the first compressed signature;

[0017] Determine a cache line to be updated based on the cache line address written by the storage-computing integrated architecture in the first address set and the second compression signature;

[0018] The cache line to be updated is written into the dynamic random access memory.

[0019] Furthermore, the method further includes merging overlapping portions of the cache lines to be updated, and then clearing an uncommitted flag in the first-level cache in the logic core.

[0020] Furthermore, the method further comprises:

[0021] When there are multiple logical cores processing the application program, when any one of the logical cores is rolled back during the processing, the remaining logical cores all perform the same rollback operation.

[0022] Furthermore, the method further comprises:

[0023] If conflicts occur three times in a row, the conflicting address and all consistent directory entries of the storage-computing architecture are locked, and all signatures in the CPU and storage-computing architecture are cleared.

[0024] On the other hand, the present invention also provides a device for maintaining cache consistency in a storage-computing integrated architecture, the device comprising:

[0025] An initialization module, used to initialize the storage-computing integrated architecture and establish a checkpoint in the application in response to the startup of the application;

[0026] An acquisition module, used to acquire multiple consistency operation requests from the central processing unit and combine them into a first compressed signature, acquire multiple consistency operation requests from the storage-computing integrated architecture and combine them into a second compressed signature;

[0027] A comparison module, configured to perform a conflict comparison between the first compressed signature and the second compressed signature when the first compressed signature or the second compressed signature reaches a maximum number of signatures;

[0028] The update module is used to roll back through the checkpoint if there is a conflict, and update the cache line in the dynamic random access memory based on the first compression signature and the second compression signature if there is no conflict.

[0029] The present invention provides a method and device for maintaining cache consistency in a storage-computing integrated architecture. Compared with the prior art, the method first initializes the storage-computing integrated architecture, and establishes a checkpoint in the application in response to the startup of the application; then obtains multiple consistency operation requests from the central processing unit, and combines them into a first compression signature, obtains multiple consistency operation requests at the storage-computing integrated architecture, and combines them into a second compression signature; then when the first compression signature or the second compression signature reaches the maximum number of signatures, the first compression signature and the second compression signature are compared for conflicts; finally, if there is a conflict, roll back to the first instruction address executed by the storage-computing integrated architecture through a checkpoint; if there is no conflict, the cache line in the dynamic random access memory is updated based on the first compression signature and the second compression signature, which can effectively improve the speed of maintaining cache consistency in the storage-computing integrated architecture and reduce the overhead of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 The figure is a flow chart of a method for maintaining cache consistency in a storage-computing integrated architecture provided by an embodiment of the present specification;

[0032] Figure 2 Shown is a schematic diagram of the structure of a device for maintaining cache consistency in a storage-computing integrated architecture provided in an embodiment of this specification. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0034] like Figure 1 The flowchart of the method for maintaining cache consistency for a storage-computing integrated architecture provided by the embodiment of this specification is shown. Although this specification provides the method operation steps or device structures shown in the following embodiments or drawings, the method or device may include more or fewer operation steps or module units after partial merger based on routine or no creative labor. In the steps or structures where there is no necessary causal relationship logically, the execution order of these steps or the module structure of the device is not limited to the execution order or module structure shown in the embodiments or drawings of this specification. When the method or module structure is applied in actual devices, servers or terminal products, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or drawings (for example, in an environment of parallel processors or multi-threaded processing, or even in an implementation environment of distributed processing and server clusters).

[0035] The method for maintaining cache consistency for the storage-computing integrated architecture provided in the present description is as follows: Figure 1 As shown, the method specifically comprises the following steps:

[0036] Step S101, initialize the storage and computing integrated architecture, and establish a checkpoint in the application in response to the startup of the application.

[0037] In an embodiment of the present application, the initialization of the storage-computing integrated architecture specifically includes determining a logical core in the storage-computing integrated architecture for processing an application, and configuring filtering conditions for the logical core, wherein the filtering conditions are used to filter out consistency operation requests that meet the conditions.

[0038] Specifically, the storage-computing integrated architecture needs to be initialized first. The initialization operation is to determine the logical core used to process the application in the storage-computing integrated architecture, that is, to determine the core in the memory that needs to execute the application and use it as the logical core. Then, filter conditions are configured for the logical core to filter out some consistency request instructions that need to be ignored. The filtering conditions include data movement between the on-chip cache and the main memory exceeding the data movement threshold, incomplete consistency request instructions or the existence of interleaved partitions (for example: read-modify-write operations), consistency request instructions with poor cache locality, and repeatedly executed instructions.

[0039] During the execution of the solution of the present application, when an application arrives in the storage-computing integrated architecture, the central processor or the preprocessing module in the memory can assign the application to an idle logical core, which is processed by the idle logical core. When the logical core receives the application, it will check it and create a checkpoint for rollback. In order to reduce the overhead required for rolling back and restarting the PIM logical core, the PIM logical core executes part of the PIM kernel (each PIM kernel is divided into smaller execution blocks). Each cache line in the PIM LI cache has a speculative write bit to mark all data updates as speculative data updates. When the logical core starts processing the application, the data in the PIM LI cache line is updated to an uncommitted state.

[0040] Step S102: obtain multiple consistency operation requests at the central processing unit and combine them into a first compressed signature, obtain multiple consistency operation requests at the storage and computing integrated architecture, and combine them into a second compressed signature.

[0041] In an embodiment of the present application, the multiple consistency operation requests at the storage-computing integrated architecture specifically include all cache line addresses read and written by the logical core.

[0042] Specifically, when the central processing unit and the storage-computing integrated architecture execute the application, multiple consistency operation requests from the central processing unit and multiple execution operation requests from the storage-computing integrated architecture are obtained respectively, and they are combined into a first compression signature and a second compression signature respectively. The logical core does not check the consistency operation request directory of the central processing unit during the execution of the application, and determines that the data update will not be submitted to the memory during the execution. That is to say, the execution of the logical core and the execution of the central processing unit are executed concurrently. At the same time, during the execution process, three groups of cache line addresses are tracked. The first group of cache line addresses are all cache line addresses read by the logical core, and the second group of cache line addresses are all cache line addresses written by the logical core. The first group of cache line addresses and the second group of cache line addresses are combined and compressed to form the second compression signature. The third group of cache line addresses are all cache line addresses of the logical core area recorded by the central processing unit. The third group of cache line addresses are combined and compressed to form the first compression signature.

[0043] Step S103: When the first compressed signature or the second compressed signature reaches the maximum number of signatures, the first compressed signature and the second compressed signature are compared for conflicts.

[0044] Specifically, a counter is configured for the first compressed signature and the second compressed signature to count the number of signatures in the first compressed signature and the second compressed signature. When the first compressed signature or the second compressed signature reaches the maximum number of signatures, or the logical core is executed, the first compressed signature and the second compressed signature are compared for conflicts.

[0045] In the embodiment of the present application, the conflict comparison specifically includes:

[0046] Decoding the first compressed signature to obtain a first address set;

[0047] The cache row addresses read by the storage-computing integrated architecture are traversed, and if at least one address in the first address set exists in the cache row addresses read by the storage-computing integrated architecture, it is determined that a conflict exists.

[0048] Specifically, the first compressed signature and the second compressed signature can be compared for conflicts through a central processing unit or a preset comparison module to identify the consistency operation request that needs to be executed. First, the first compressed signature is decoded through a signature extension method to obtain a first address set. The first compressed signature is also the third group of cache row addresses mentioned above. It is determined whether the first address set is in the first group of cache row addresses. If so, there is a conflict.

[0049] Step S104: If there is a conflict, roll back to the first instruction address executed by the storage-computing integrated architecture through a checkpoint; if there is no conflict, update the cache line in the dynamic random access memory based on the first compression signature and the second compression signature.

[0050] Specifically, if there is a conflict, the conflicting cache line address is first determined, and then the conflicting cache line address is refreshed to the dynamic random access memory, and a copy of the conflicting cache line address is placed in the PIM L1 cache. At the same time, the speculated cache line is updated to invalid through the logical core, and the checkpoint is used to roll back to the beginning of the kernel, that is, the address of the first instruction executed by the storage-computing integrated architecture or the logical core, and all signatures of the kernel are deleted, wherein the central processing unit CPU schedules some applications to be executed on the computing unit (PIM logical core, PIM core) in the storage-computing integrated architecture, and the scheduled application is called the PIM kernel, that is, the logical core (PIM kernel). In order to reduce the possibility of program rollback, each PIM kernel is divided into smaller execution blocks (called PIM partial kernels, and the rollback can be rolled back to the first instruction address of the PIM partial kernel, and this kernel refers to the PIM partial kernel).

[0051] More specifically, during the execution of the PIM partial kernel, when a write operation is performed, the written data value cannot be committed to the memory, and the updated data value can be buffered in the PIM L1 cache, which is the first-level cache in the logical core, and marked as uncommitted. When no conflict is detected, the CPU will send a message to the PIM core, and the PIM core will commit the updated value in the L1 cache to the memory and clear the uncommitted flag of all updated data in the PIM L1 cache; when a conflict is detected, the updated uncommitted data in the L1 cache will be invalidated, and the rollback will continue to the PC checkpoint of the currently executed PIM partial kernel. If there is still a conflict after rolling back 3 times, the updated data in the PIM L1 cache fails to be submitted to the memory. After three consecutive submission failures, the logical core acquires a lock for each cache line in the first group of cache line addresses to ensure the continued execution of the logical core.

[0052] In an embodiment of the present application, updating a cache line in a dynamic random access memory based on a first compression signature and a second compression signature specifically includes:

[0053] Determining a first address set corresponding to the first compressed signature;

[0054] Determine a cache line to be updated based on the cache line address written by the storage-computing integrated architecture in the first address set and the second compression signature;

[0055] The cache line to be updated is written into the dynamic random access memory.

[0056] In addition, the method further includes merging the overlapping parts of the cache lines to be updated, and then clearing the uncommitted flag in the first-level cache of the logical core. When there are multiple logical cores processing the application, when any one of the logical cores generates a rollback during the processing, the remaining logical cores all perform the same rollback operation.

[0057] Specifically, when there is no conflict, the intersection of the second set of cache line addresses and the third set of cache line addresses is determined, and the intersection of the overlapping parts in the intersection is merged as the cache line to be updated, and the overlapping cache lines in the third set of cache line addresses are treated as invalid, and then the cache line to be updated is written into the dynamic random access memory.

[0058] In addition, when there are multiple logical cores processing applications, these logical cores maintain consistency through local directories. That is, when there are multiple PIM logical cores (PIM cores) processing applications, each PIM logical core contains a small private L1 instruction / data cache (L1 I / D Cache), which is also the first-level cache. The data caches in these PIM cores use the directory-based MESI cache consistency protocol to maintain consistency.

[0059] When any logical core is rolled back during processing, the remaining logical cores perform the same rollback operation.

[0060] Based on the above-mentioned method for maintaining cache consistency for a storage-computing integrated architecture, one or more embodiments of this specification also provide a platform and terminal for maintaining cache consistency for a storage-computing integrated architecture. The platform or terminal may include devices, software, modules, plug-ins, servers, clients, etc. that use the methods described in the embodiments of this specification and are combined with necessary implementation hardware devices. Based on the same innovative concept, the system in one or more embodiments provided in the embodiments of this specification is as described in the following embodiments. Since the implementation scheme and method for solving the problem of the system are similar, the implementation of the specific system in the embodiments of this specification can refer to the implementation of the aforementioned method, and the repetitions will not be repeated. The terms "unit" or "module" used below can be a combination of software and / or hardware that implements predetermined functions. Although the system described in the following embodiments is preferably implemented in software, hardware and a combination of software and hardware are also possible and conceived.

[0061] Specifically, Figure 2 Schematic diagram of the module structure of an embodiment of a device for maintaining cache consistency in a storage-computing integrated architecture provided in this specification, such as Figure 2 As shown, the device for maintaining cache consistency for a storage-computing integrated architecture provided in this specification includes:

[0062] Initialization module 201, used to initialize the storage-computing integrated architecture and establish a checkpoint in the application in response to the startup of the application;

[0063] An acquisition module 202 is used to acquire multiple consistency operation requests from the central processing unit and combine them into a first compressed signature, acquire multiple consistency operation requests from the storage-computing integrated architecture and combine them into a second compressed signature;

[0064] A comparison module 203, configured to perform a conflict comparison between the first compressed signature and the second compressed signature when the first compressed signature or the second compressed signature reaches a maximum number of signatures;

[0065] The update module 204 is used to roll back to the first instruction address executed by the storage-computing integrated architecture through a checkpoint if there is a conflict, and to update the cache line in the dynamic random access memory based on the first compression signature and the second compression signature if there is no conflict.

[0066] It should be noted that the above-mentioned system may also include other implementation modes according to the description of the corresponding method embodiment. The specific implementation modes may refer to the description of the above-mentioned corresponding method embodiment, which will not be described one by one here.

[0067] The present application also provides an electronic device, including:

[0068] processor;

[0069] a memory for storing instructions executable by the processor;

[0070] The processor is configured to execute the method provided in the above embodiment.

[0071] The electronic device provided by the embodiment of the present application stores the executable instructions of the processor in the memory. When the processor executes the executable instructions, it can first initialize the storage-computing integrated architecture and establish a checkpoint in the application in response to the startup of the application; then obtain multiple consistency operation requests from the central processing unit and combine them into a first compression signature, obtain multiple consistency operation requests at the storage-computing integrated architecture and combine them into a second compression signature; then when the first compression signature or the second compression signature reaches the maximum number of signatures, the first compression signature and the second compression signature are compared for conflicts; finally, if there is a conflict, it is rolled back to the first instruction address executed by the storage-computing integrated architecture through a checkpoint. If there is no conflict, the cache lines in the dynamic random access memory are updated based on the first compression signature and the second compression signature, which can effectively improve the speed of maintaining cache consistency in the storage-computing integrated architecture and reduce the overhead of hardware resources.

[0072] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0073] The methods or devices described in the above embodiments provided in this specification can implement business logic through computer programs and record them on storage media, and the storage media can be read and executed by computers to achieve the effects of the solutions described in the embodiments of this specification, such as:

[0074] Initialize the storage-computing architecture and establish a checkpoint in the application in response to the startup of the application;

[0075] Obtain multiple consistency operation requests at the central processing unit and combine them into a first compressed signature, obtain multiple consistency operation requests at the storage-computing integrated architecture and combine them into a second compressed signature;

[0076] When the first compressed signature or the second compressed signature reaches the maximum number of signatures, the first compressed signature and the second compressed signature are compared for conflicts;

[0077] If there is a conflict, the checkpoint is used to roll back to the address of the first instruction executed by the storage-computing integrated architecture. If there is no conflict, the cache line in the dynamic random access memory is updated based on the first compression signature and the second compression signature.

[0078] The storage medium may include a physical device for storing information, which is usually a medium that digitizes information and then stores it in an electrical, magnetic or optical manner. The storage medium may include: a device that stores information in an electrical energy manner, such as various memories, such as RAM, ROM, etc.; a device that stores information in a magnetic energy manner, such as a hard disk, a floppy disk, a magnetic tape, a magnetic core memory, a magnetic bubble memory, a USB flash drive; a device that stores information in an optical manner, such as a CD or a DVD. Of course, there are other readable storage media, such as quantum memory, graphene memory, etc.

[0079] The embodiments of this specification are not limited to complying with industry communication standards, standard computer resource data update and data storage rules, or the situations described in one or more embodiments of this specification. Certain industry standards or slightly modified implementation plans based on the implementation described in the custom method or embodiment can also achieve the same, equivalent or similar, or predictable implementation effects after deformation of the above-mentioned embodiments. The embodiments obtained by using these modified or deformed data acquisition, storage, judgment, processing methods, etc. can still fall within the scope of the optional implementation plans of the embodiments of this specification.

[0080] The device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. There may be other divisions in actual implementation, such as multiple units or plug-ins may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of the device or unit, which may be electrical, mechanical or other forms.

[0081] These computer program instructions may also be loaded onto a computer or other programmable resource data updating device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions executed on the computer or other programmable device for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. In the description of this specification, the description of the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0083] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the present invention.

Claims

1. A method for maintaining cache consistency in a storage-computing integrated architecture, characterized in that: The method comprises: Initialize the storage-computing architecture and establish a checkpoint in the application in response to the startup of the application; Obtain multiple consistency operation requests at the central processing unit and combine them into a first compressed signature, obtain multiple consistency operation requests at the storage-computing integrated architecture and combine them into a second compressed signature; When the first compressed signature or the second compressed signature reaches the maximum number of signatures, the first compressed signature and the second compressed signature are compared for conflicts; If there is a conflict, the checkpoint is used to roll back to the address of the first instruction executed by the storage-computing integrated architecture. If there is no conflict, the cache line in the dynamic random access memory is updated based on the first compression signature and the second compression signature.

2. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 1, characterized in that: The initialization of the storage-computing integrated architecture specifically includes determining a logical core in the storage-computing integrated architecture for processing an application, and configuring a filtering condition for the logical core, wherein the filtering condition is used to filter out consistency operation requests that meet the condition.

3. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 2, characterized in that: The multiple consistency operation requests at the storage-computing integrated architecture specifically include all cache line addresses read and written by the logical core.

4. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 1, characterized in that: The conflict comparison specifically includes: Decoding the first compressed signature to obtain a first address set; The cache row addresses read by the storage-computing integrated architecture are traversed, and if at least one address in the first address set exists in the cache row addresses read by the storage-computing integrated architecture, it is determined that a conflict exists.

5. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 2, characterized in that: The updating of the cache line in the dynamic random access memory based on the first compression signature and the second compression signature specifically includes: Determining a first address set corresponding to the first compressed signature; Determine a cache line to be updated based on the cache line address written by the storage-computing integrated architecture in the first address set and the second compression signature; The cache line to be updated is written into the dynamic random access memory.

6. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 5, characterized in that: The method further includes merging overlapping portions of the cache lines to be updated, and then clearing an uncommitted flag in the first level cache in the logic core.

7. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 2, characterized in that: The method further comprises: When there are multiple logical cores processing the application program, when any one of the logical cores is rolled back during the processing, the remaining logical cores all perform the same rollback operation.

8. The method for maintaining cache consistency for a storage-computing integrated architecture according to claim 2, characterized in that: The method further comprises: If conflicts occur three times in a row, the conflicting address and all consistency directory entries of the storage-computing integrated architecture will be locked, and all signatures in the central processing unit and the storage-computing integrated architecture will be cleared.

9. A device for maintaining cache consistency in a storage-computing integrated architecture, characterized in that: The device comprises: An initialization module, used to initialize the storage-computing integrated architecture and establish a checkpoint in the application in response to the startup of the application; An acquisition module, used to acquire multiple consistency operation requests from the central processing unit and combine them into a first compressed signature, acquire multiple consistency operation requests from the storage-computing integrated architecture and combine them into a second compressed signature; A comparison module, configured to perform a conflict comparison between the first compressed signature and the second compressed signature when the first compressed signature or the second compressed signature reaches a maximum number of signatures; An update module is used to roll back to the first instruction address executed by the storage-computing integrated architecture through a checkpoint if there is a conflict, and to update the cache line in the dynamic random access memory based on the first compression signature and the second compression signature if there is no conflict.

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