Data reading method, selector-only memory and memory system

Abstract

The embodiment of the invention discloses a data reading method, a selector-only memory and a memory system. The data reading method comprises the following steps: increasing the voltage of a selected word line to a first word line voltage, and detecting the first bit line voltage of the selected word line; in response to the fact that the first bit line voltage of the selected bit line is smaller than the reference voltage, the voltage of the selected word line is boosted to a second word line voltage, and the second bit line voltage of the selected bit line is detected; and reading the target data based on the second bit line voltage of the selected bit line. Wherein the second word line voltage is greater than the first word line voltage.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a data reading method, a selector-only memory, and a memory system. Background Art

[0002] In a 3D XPoint memory (3D magnetic memory), a memory cell is composed of a selector (a switch used as a cell selection element) and a storage element (a phase change memory PCM); that is, the 3D XPoint memory has a 1S1R configuration.

[0003] In SOM (Selector Only Memory), the storage unit only includes the selector. Compared with 3D XPoint memory, SOM can adapt to smaller processing size. Even if the processing size is 15nm, the high threshold voltage and low threshold voltage states in SOM can be maintained; in addition, the write time of SOM devices is shorter, and the write time can be basically consistent between the reset and set states; and the write cycle life of SOM is also longer than that of 1S1R configuration memory.

[0004] However, there is still a problem of read disturbance (Read disturb) in the reading process of the SOM device, and the problem of reduced Ea (activation energy) will occur, which will cause the threshold voltage of the device to change and have an adverse effect on the performance of the device. Summary of the invention

[0005] In view of this, embodiments of the present application provide a data reading method, a selector-only memory, and a memory system, which can reduce the read disturbance problem and ensure the accuracy of the stored data.

[0006] The technical solution of the embodiment of the present application is implemented as follows:

[0007] An embodiment of the present application provides a data reading method, which is applied to a selector-only memory, including: raising the voltage of a selected word line to a first word line voltage, and detecting a first bit line voltage of the selected word line; in response to the first bit line voltage of the selected bit line being less than a reference voltage, raising the voltage of the selected word line to a second word line voltage, and detecting a second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage; and reading target data based on the second bit line voltage of the selected bit line.

[0008] In some embodiments of the present application, the data reading method further includes: in response to the voltage of the selected word line being increased to the second word line voltage, increasing the voltage of the unselected bit line to a compensation voltage.

[0009] In some embodiments of the present application, the compensation voltage is less than the first word line voltage and greater than a voltage of a ground terminal.

[0010] In some embodiments of the present application, the target data is read based on the second bit line voltage of the selected bit line, including: in response to the second bit line voltage of the selected bit line being greater than the reference voltage, the target data is read as 1; or, in response to the second bit line voltage of the selected bit line being less than the reference voltage, the target data is read as 0.

[0011] In some embodiments of the present application, after detecting the first bit line voltage of the selected bit line, the data reading method further includes: in response to the first bit line voltage of the selected bit line being greater than the reference voltage, reading the target data as 1.

[0012] In some embodiments of the present application, before raising the voltage of the selected word line to the first word line voltage, the data reading method further includes: discharging the selected bit line to a starting bit line voltage; the starting bit line voltage is less than the reference voltage.

[0013] In some embodiments of the present application, after reading the target data, the data reading method further includes: grounding the selected word line and the selected bit line.

[0014] An embodiment of the present application also provides a selector-only memory, comprising: a memory cell array and a peripheral circuit; wherein the memory cell array comprises: multiple rows of word lines and multiple columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit couples the multiple rows of word lines and the multiple columns of bit lines; the peripheral circuit is configured to increase the voltage of a selected word line to a first word line voltage, and detect a first bit line voltage of the selected bit line; and, in response to the first bit line voltage of the selected bit line being less than a reference voltage, increase the voltage of the selected word line to a second word line voltage, and detect the second bit line voltage of the selected bit line; and, based on the second bit line voltage of the selected bit line, read target data; wherein the second word line voltage is greater than the first word line voltage.

[0015] In some embodiments of the present application, the peripheral circuit is further configured to increase the voltage of the unselected word line to a compensation voltage in response to the voltage of the selected word line increasing to a second word line voltage; wherein the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

[0016] An embodiment of the present application also provides a memory system, comprising: one or more selector-only memories as described in the above scheme, and a memory controller; the memory controller is coupled to the selector-only memories; the memory controller controls the selector-only memories.

[0017] It can be understood that, during the reading process, the voltage of the selected word line is first increased to a smaller first word line voltage, and then, based on the first bit line voltage of the selected word line, it is determined whether to increase the voltage of the selected word line to a larger second word line voltage. In this way, a step-type word line voltage is adopted during the reading process to avoid directly increasing the voltage of the selected word line to the larger second word line voltage, thereby reducing the voltage of the selected word line during the reading process, reducing the current on the SOM device during the reading process, and then reducing the read interference problem, ensuring the accuracy of the stored data. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A This is a schematic diagram of the read disturbance problem in the SOM device;

[0019] Figure 1B This is an illustration of the read disturbance problem in a SOM device. Figure 2 ;

[0020] Figure 1C It is the third schematic diagram of the read disturbance problem in the SOM device;

[0021] Figure 2 1 is a structural diagram of only the selector memory provided in an embodiment of the present application;

[0022] Figure 3A 1 is a schematic diagram of electrical parameter waveforms of a write process of only a selector memory provided in an embodiment of the present application;

[0023] Figure 3B This is a schematic diagram of the electrical parameter waveform of the write process of the selector memory provided by the embodiment of the present application. Figure 2 ;

[0024] Figure 4 is a schematic diagram of a read process of only a selector memory provided in an embodiment of the present application;

[0025] Figure 5 1 is a schematic diagram of the implementation flow of the data reading method provided in the embodiment of the present application;

[0026] Figure 6 This is a schematic diagram of the implementation process of the data reading method provided in the embodiment of the present application. Figure 2 ;

[0027] Figure 7 1 is a schematic diagram of an electrical parameter waveform of a data reading method provided in an embodiment of the present application;

[0028] Figure 8 The electrical parameter waveform diagram of the data reading method provided in the embodiment of the present application is Figure 2 ;

[0029] Fig. 9 Schematic diagram 3 of the implementation flow of the data reading method provided in the embodiment of the present application;

[0030] Fig.10 Schematic diagram 3 of electrical parameter waveforms of the data reading method provided in an embodiment of the present application;

[0031] Fig.11 This is a schematic diagram of the implementation process of the data reading method provided in the embodiment of the present application. Figure 4 ;

[0032] Fig.12 This is a schematic diagram of the implementation process of the data reading method provided in the embodiment of the present application. Figure 5 ;

[0033] Fig.13 This is a schematic diagram of the structure of only the selector memory provided in the embodiment of the present application. Figure 2 ;

[0034] Fig.14 It is a schematic diagram of the structure of the memory system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0036] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0037] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0039] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items. The units "root", "bar" or "individual" for transmission lines all represent the same meaning.

[0041] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0042] In the related art, the increase in the number of read pulse cycles in the SOM will bring about the problem of read interference. Among them, read interference refers to the fact that due to the increase in the number of read cycles, a large voltage difference is applied to both ends of the device for many times, thereby causing the performance of the device to deteriorate (for example, Ea decreases, the threshold voltage changes), and in severe cases, the data stored in the device will change. For SOM devices, read interference is manifested as abnormal current during the reading process.

[0043] refer to Figure 1A , when the data "1" is stored in the SOM device, as the number of read cycles increases, the current of the SOM device during the reading process remains stable, that is, there is basically no read disturbance problem. Figure 1B When the data "0" is stored in the SOM device, as the number of read cycles increases, the current of the SOM device during the reading process becomes obviously abnormal, that is, a read disturbance problem occurs.

[0044] refer to Figure 1C For condition 1, that is, when data "1" is stored in the SOM device, as the number of read cycles increases, the Ea of the SOM device remains stable. For condition 2, that is, when data "0" is stored in the SOM device, as the number of read cycles increases, the Ea of the SOM device decreases significantly, which will cause a significant change in the threshold voltage of the SOM device and have an adverse effect on the performance of the device.

[0045] In summary, for the SOM device, when data "1" is stored in the SOM device, the read disturbance problem basically does not occur; however, when data "0" is stored in the SOM device, the read disturbance problem is prone to occur.

[0046] Figure 2 1 is an optional structural diagram of only the selector memory provided in the embodiment of the present application. Figure 2 ,In SOM, each OTS (bidirectional threshold switch selector) constitutes a storage unit, and the two ends of each OTS are respectively connected to the corresponding word line and bit line.

[0047] Combination Figure 2 and Figure 3AWhen the set process is performed, the voltage of the selected word line WL is increased from the ground terminal voltage VSS to the positive voltage Vp, and the voltage of the selected bit line BL is reduced from the ground terminal voltage VSS to the negative voltage Vn. In this way, the phase change material in the target OTS can be transformed from an amorphous state to a crystalline state, thereby writing data "1" to the target OTS.

[0048] Combination Figure 2 and Figure 3B When the reset process is performed, the voltage of the selected word line WL is reduced from the ground terminal voltage VSS to the negative voltage Vn, and the voltage of the selected bit line BL is increased from the ground terminal voltage VSS to the positive voltage Vp. In this way, the phase change material in the target OTS can be transformed from a crystalline state to an amorphous state, thereby writing data "0" to the target OTS.

[0049] Figure 4 The reading process of the SOM device is shown in FIG. Figure 4 As shown, during the reading process, the voltage of the selected word line WL will rise to a positive voltage, and at the same time, the voltage of the selected bit line BL will be detected, and the SOM device (ie, Figure 2 The target data stored in the target OTS in the SOM device is determined by the voltage drop between the selected bit line BL and the selected word line WL. In other words, the target data stored in the SOM device is determined according to the resistance of the SOM device, wherein the resistance of the SOM device is determined by the state of the phase change material. The current direction (i.e., the read direction) during the reading process is from the selected word line WL to the selected bit line BL.

[0050] It should be noted that the reference Figure 4 Since the reading direction is from the selected word line WL to the selected bit line BL, the larger the voltage of the selected word line WL is during the reading process, the larger the current on the SOM device is. Furthermore, the larger the current on the SOM device is during the reading process, the more likely it is that read disturbance will occur.

[0051] Figure 5 is an optional flow chart of a data reading method provided in an embodiment of the present application, and the data reading method is applied to a selector memory only. Figure 5 As shown, the data reading method includes steps S101 to S103, which will be described in combination with each step.

[0052] S101 , raising the voltage of a selected word line to a first word line voltage, and detecting a first bit line voltage of the selected word line.

[0053] In the present application examples, reference Figure 7During the reading process of the SOM device, the voltage of the selected word line WL can be first increased to the first word line voltage VBN1, that is, the "WL ramping P1" stage is executed; and the voltage of the selected bit line BL in the "WL ramping P1" stage is detected (the first bit line voltage of the selected bit line BL).

[0054] S102, in response to a first bit line voltage of a selected bit line being less than a reference voltage, raising the voltage of the selected word line to a second bit line voltage, and detecting the second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage.

[0055] S103 , reading target data based on a second bit line voltage of the selected bit line.

[0056] In the present application embodiment, Figure 7 In the example shown, the voltage of the selected bit line BL in the "WL ramping P1" stage (the first bit line voltage) is maintained as the starting bit line voltage VNR1, which is less than the reference voltage Vref. Then, the voltage of the selected word line WL can be increased from the first word line voltage VBN1 to the second word line voltage VBN2, that is, the "WL ramping P2" stage is performed; and the voltage of the selected bit line BL in the "WL ramping P2" stage (the second bit line voltage of the selected bit line BL) is detected. Furthermore, the target data to be read can be determined based on the second bit line voltage of the bit line BL.

[0057] In the embodiment of the present application, the second word line voltage VBN2 is greater than the first word line voltage VBN1; for example, the first word line voltage VBN1 may be 2 to 3 V, and the second word line voltage VBN2 may be 4 to 5 V. The second word line voltage VBN2 and the first word line voltage VBN1 may be provided by different power supplies preset in the SOM.

[0058] In some embodiments of the present application, the first word line voltage VBN1 and the second word line voltage VBN2 can be selected from a plurality of different voltage values ​​according to requirements. For example, one power source with three different voltage values ​​can be selected to provide the second word line voltage VBN2.

[0059] It can be understood that, during the reading process, the voltage of the selected word line WL is first increased to a smaller first word line voltage, and then, based on the first bit line voltage of the selected bit line BL, it is determined whether to increase the voltage of the selected word line WL to a larger second word line voltage. In this way, a step-type word line voltage is adopted during the reading process to avoid directly increasing the voltage of the selected word line WL to the larger second word line voltage, thereby reducing the voltage of the selected word line WL during the reading process, reducing the current on the SOM device during the reading process, and then reducing the read disturbance problem, ensuring the accuracy of the stored data.

[0060] In some embodiments of the present application, Figure 6 Steps S201 to S202 are shown to achieve Figure 5 Step S103 shown will be described in conjunction with each step.

[0061] S201 , in response to a second bit line voltage of a selected bit line being greater than a reference voltage, the read target data is 1.

[0062] In the present application examples, reference Figure 7 , when the voltage of the selected word line WL rises to the second word line voltage VBN2 (ie, in the "WL rise P2" phase), if the second bit line voltage of the selected bit line BL rises to the voltage VNR2 (greater than the reference voltage Vref); then, it can be determined Figure 2 The target OTS in the state of having a small resistance value, that is, it can be determined that the target data to be read is 1. Then, the "data latch" stage can be executed to latch the determined target data.

[0063] S202 , in response to a second bit line voltage of the selected bit line being less than a reference voltage, reading target data as 0.

[0064] In the present application examples, reference Figure 7 , when the voltage of the selected word line WL rises to the second word line voltage VBN2 (i.e., in the "WL rise P2" phase), if the second bit line voltage of the selected bit line BL maintains the starting bit line voltage VNR1 (less than the reference voltage Vref); then, it can be determined Figure 2 The target OTS in the state of having a large resistance value, that is, it can be determined that the target data to be read is 0. Then, the "data latch" stage can be executed to latch the determined target data.

[0065] In some embodiments of the present application, Figure 5 After step S101, the data reading method further includes Figure 6 Step S203 shown will be described in conjunction with each step.

[0066] S203 , in response to the first bit line voltage of the selected bit line being greater than the reference voltage, the read target data is 1.

[0067] In the present application examples, reference Figure 8, when the voltage of the selected word line WL is increased to the first word line voltage VBN1 (i.e., in the "WL increase P1" stage), if the first bit line voltage of the selected bit line BL is increased to the voltage VNR3 (greater than the reference voltage Vref); then, it is not necessary to further increase the voltage of the selected word line WL, and it can be determined Figure 2 The target OTS in the state is in a state with a small resistance value, that is, it can be determined that the target data to be read is 1. Then, the "data latch" stage can be executed to latch the determined target data.

[0068] It can be understood that, when the voltage of the selected word line WL is increased to the first word line voltage VBN1, if the first bit line voltage of the selected bit line BL is greater than the reference voltage Vref, the target data is directly determined to be 1; and if the first bit line voltage of the selected bit line BL is less than the reference voltage Vref, the voltage of the selected word line WL needs to be further increased to determine whether the target data is 0. In this way, in the case where the data "0" is stored in the SOM device, a step-type word line voltage is used during the reading process to avoid directly increasing the voltage of the selected word line WL to a larger second word line voltage, thereby being able to specifically reduce the read disturbance problem, that is, solving the problem that the SOM device in the "0" state is prone to read disturbance.

[0069] In some embodiments of the present application, Figure 5 After step S102, the data reading method further includes Fig. 9 The step S104 shown will be explained in conjunction with each step.

[0070] S104 , in response to the voltage of the selected word line being increased to the second word line voltage, the voltage of the unselected bit lines is increased to the compensation voltage.

[0071] In the present application examples, reference Figure 2 Since multiple storage cells (i.e., OTSs) are connected to the selected word line WL, during the reading process, the voltage increase of the selected word line WL not only affects the target OTS connected to the selected bit line BL, but also affects other OTSs connected to the unselected bit line Usel BL. In other words, the voltage increase of the selected word line WL will cause read interference to other OTSs.

[0072] It should be noted that during the writing process, a certain voltage difference needs to be applied across the OTS to change the state of the phase change material in the OTS, thereby writing the corresponding data. Figure 3A , in the process of writing data "1", the word line WL is applied with a positive voltage Vp, and the bit line BL is applied with a negative voltage Vn; Figure 3BIn the process of writing data "0", the word line WL applies a negative voltage Vn and the bit line BL applies a positive voltage Vp. In other words, when the voltage difference across OTS reaches a certain level, the stored data will be changed.

[0073] Combination Figure 2 and Fig.10 , when the voltage of the selected word line WL is increased to the second word line voltage VBN2, the voltage of the unselected bit line Usel BL is increased to the compensation voltage VC. In this way, the voltage difference between the unselected bit line Usel BL and the selected word line WL can be reduced, that is, the voltage difference between the two ends of other OTS connected to the unselected bit line Usel BL is reduced, thereby offsetting the influence of the second word line voltage VBN2 on other OTS, and ensuring the accuracy of the data stored in other OTS.

[0074] In some embodiments of the present application, the compensation voltage VC is less than the first word line voltage VBN1 and greater than the voltage VSS of the ground terminal. For example, the compensation voltage VC may be 1.2V.

[0075] It should be noted that the voltage of the unselected bit line Usel BL in an idle state is maintained at the voltage VSS of the ground terminal, and therefore, the compensation voltage VC needs to be greater than the voltage VSS of the ground terminal to be effective.

[0076] In addition, the compensation voltage VC should not be set too large. If the compensation voltage VC is too large, the voltage difference between the unselected bit line Usel BL and the selected bit line BL will be too large, which may cause leakage between the unselected bit line Usel BL and the selected bit line BL. At the same time, too large a compensation voltage VC will also lead to greater power consumption.

[0077] In some embodiments of the present application, the data reading method further includes: Fig.11 Steps S301 and S302 are shown. Each step will be described in combination.

[0078] S301, discharge the selected bit line to a starting bit line voltage; the starting bit line voltage is less than a reference voltage.

[0079] In the present application examples, reference Figure 7 and Figure 8 At the beginning of the reading process, the selected bit line BL needs to be discharged, that is, the "BL discharge" stage is performed. In this way, the residual voltage on the selected bit line BL can be prevented from affecting the reading result.

[0080] In the present application, continue to refer to Figure 7 and Figure 8, the selected bit line BL can be discharged to the starting bit line voltage VNR1; wherein the starting bit line voltage VNR1 is less than the reference voltage Vref, and the starting bit line voltage VNR1 is also less than the ground terminal voltage VSS.

[0081] S302 , grounding the selected word line and the selected bit line.

[0082] In the present application examples, reference Figure 7 and Figure 8 After the target data is read, the voltages of the selected word line WL and the selected bit line BL need to be reset, that is, the "weak reset" stage is performed. In this way, the residual voltage on the selected word line WL and the selected bit line BL can be prevented from affecting other working processes of the memory.

[0083] In the present application, continue to refer to Figure 7 and Figure 8 , the selected word line WL and the selected bit line BL may be grounded, so that the voltages of the selected word line WL and the selected bit line BL are both reset to the voltage VSS of the ground terminal.

[0084] Fig.12 is an optional flow chart of a data reading method provided in an embodiment of the present application, and the data reading method is applied to a selector memory only. Fig.12 As shown, the data reading method includes steps S401 to S407, which will be described in combination with each step.

[0085] S401 , the selected bit line BL is discharged to the starting bit line voltage VNR1 .

[0086] In the present application examples, reference Figure 7 and Figure 8 At the beginning of the reading process, the selected bit line BL needs to be discharged, that is, the "BL discharge" phase is performed. The selected bit line BL can be discharged to the starting bit line voltage VNR1.

[0087] S402 , the selected word line WL is increased to a first word line voltage VBN1 .

[0088] In the present application examples, reference Figure 7 and Figure 8 , the voltage of the selected word line WL may be first increased to the first word line voltage VBN1, that is, the “WL increase P1” phase is performed.

[0089] S403 , the selected word line WL is increased to a higher second word line voltage VBN2 .

[0090] In the present application examples, reference Figure 7After the voltage of the selected word line WL is increased to the first word line voltage VBN1, if the voltage of the selected bit line BL (the first bit line voltage) is less than the reference voltage Vref, then the voltage of the selected word line WL can be increased to a higher second word line voltage VBN2, that is, the "WL increase P2" stage is executed.

[0091] S404 , the selected word line WL is maintained at the first word line voltage VBN1 .

[0092] In the present application examples, reference Figure 8 After the voltage of the selected word line WL rises to the first word line voltage VBN1, if the voltage of the selected bit line BL (the first bit line voltage) is greater than the reference voltage Vref, the selected word line WL can be maintained at the first word line voltage VBN1. At this time, the target data can be read as 1.

[0093] S405 , the unselected bit line Unsel BL is increased to the compensation voltage VC.

[0094] In the present application examples, reference Fig.10 When the voltage of the selected word line is increased to the second word line voltage VBN2, the voltage of the unselected bit line Usel BL is increased to the compensation voltage VC to reduce the voltage difference between the unselected bit line Usel BL and the selected word line WL.

[0095] S406 , sensing and restoring the selected word line WL to the ground voltage VSS.

[0096] In the present application examples, reference Figure 7 and Figure 8 After the voltage of the selected word line is increased to the second word line voltage VBN2, the voltage of the selected bit line BL can be sensed, that is, the "data latch" stage is performed. At the same time, the selected word line WL can be restored to the ground terminal voltage VSS.

[0097] S407 , the voltage of the selected bit line BL is restored to the ground voltage VSS.

[0098] In the present application examples, reference Figure 7 and Figure 8 After the target data is read, the voltage of the selected bit line BL can be restored to the ground voltage VSS, that is, a “weak reset” phase is performed.

[0099] It can be understood that, when the voltage of the selected word line WL is increased to the first word line voltage VBN1, if the first bit line voltage of the selected bit line BL is greater than the reference voltage Vref, the target data is directly determined to be 1; and if the first bit line voltage of the selected bit line BL is less than the reference voltage Vref, the voltage of the selected word line WL needs to be further increased to determine whether the target data is 0. In this way, in the case where the data "0" is stored in the SOM device, a step-type word line voltage is used during the reading process to avoid directly increasing the voltage of the selected word line WL to a larger second word line voltage, thereby being able to specifically reduce the read disturbance problem, that is, solving the problem that the SOM device in the "0" state is prone to read disturbance.

[0100] At the same time, when the voltage of the selected word line is increased to the second word line voltage VBN2, the voltage of the unselected bit line UselBL is increased to the compensation voltage VC. In this way, the voltage difference between the two ends of other OTSs connected to the unselected bit line Usel BL is reduced, thereby offsetting the influence of the second word line voltage VBN2 on other OTSs, and ensuring the accuracy of the data stored in other OTSs.

[0101] Fig.13 FIG. 1 is a schematic diagram of an optional structure of only a selector memory in an embodiment of the present application. Fig.13 As shown, only the selector memory 10 includes: a peripheral circuit 110 and a memory cell array 120 .

[0102] In the embodiment of the present application, the memory cell array 120 includes: a plurality of rows of word lines WL and a plurality of columns of bit lines BL, and memory cells coupled between the word lines WL and the bit lines BL. The peripheral circuit 110 couples the plurality of rows of word lines WL and the plurality of columns of bit lines BL. Figure 2 , the word line WL and the bit line BL extend in different directions, and the memory cell (ie, OTS) is coupled between the word line WL and the bit line BL.

[0103] In the embodiment of the present application, the peripheral circuit 110 may perform operations to process data in the memory cell array 120. The peripheral circuit 110 may write data to the memory cell array 120 or read data from the memory cell array 120 based on the command CMD and the address ADDR.

[0104] In an embodiment of the present application, the peripheral circuit 110 is configured to increase the voltage of the selected word line to a first word line voltage and detect a first bit line voltage of the selected word line; and, in response to the first bit line voltage of the selected word line being less than a reference voltage, increase the voltage of the selected word line to a second word line voltage and detect a second bit line voltage of the selected bit line; and, based on the second bit line voltage of the selected bit line, read the target data; wherein the second word line voltage is greater than the first word line voltage.

[0105] In some embodiments of the present application, the peripheral circuit 110 is further configured to increase the voltage of the unselected word line to a compensation voltage in response to the voltage of the selected word line increasing to a second word line voltage; wherein the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

[0106] In some embodiments of the present application, the peripheral circuit 110 is further configured to read the target data as 1 in response to the second bit line voltage of the selected bit line being greater than the reference voltage; or to read the target data as 0 in response to the second bit line voltage of the selected bit line being less than the reference voltage.

[0107] In some embodiments of the present application, the peripheral circuit 110 is further configured to read the target data as 1 in response to a first bit line voltage of the selected bit line being greater than a reference voltage.

[0108] In some embodiments of the present application, the peripheral circuit 110 is further configured to discharge the selected bit line to a starting bit line voltage; wherein the starting bit line voltage is less than a reference voltage.

[0109] In some embodiments of the present application, the peripheral circuit 110 is further configured to ground the selected word line and the selected bit line.

[0110] Fig.14 FIG. 1 is a schematic diagram of an optional structure of a memory system in an embodiment of the present application. Fig.14 As shown, the memory system 30 includes: one or more selector-only memories 10 , and a memory controller 20 .

[0111] In the present application examples, reference Fig.14 The memory controller 20 is coupled to the selector-only memory 10 and the host HOST, and is configured to control the selector-only memory 10. The host HOST may be a processor (CPU) or a graphics processor (GPU). The host HOST may be configured to send data to the selector-only memory 10, or to receive data from the selector-only memory 10.

[0112] Continue to refer Fig.14 The memory controller 20 may manage data in the selector-only memory 10 and communicate with the host HOST. The memory controller 20 may be configured to control operations of the selector-only memory 10, such as read and write operations.

[0113] In the present application examples, reference Fig.14 The memory controller 20 may send data to the host HOST and receive data from the host HOST; and the memory controller 20 may send a command CMD and an address ADDR to the selector-only memory 10 .

[0114] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0115] The serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0116] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A data reading method, applied to a selector-only memory, characterized in that: include: Raising the voltage of the selected word line to a first word line voltage, and detecting a first word line voltage of the selected word line; In response to the first bit line voltage of the selected bit line being less than a reference voltage, raising the voltage of the selected word line to a second word line voltage, and detecting the second bit line voltage of the selected bit line; wherein the second word line voltage is greater than the first word line voltage; Target data is read based on the second bit line voltage of the selected bit line.

2. The data reading method according to claim 1, characterized in that: The data reading method further includes: In response to the voltage of the selected word line being raised to the second word line voltage, the voltage of the unselected bit lines is raised to a compensation voltage.

3. The data reading method according to claim 2, characterized in that: The compensation voltage is smaller than the first word line voltage and larger than a voltage of a ground terminal.

4. The data reading method according to claim 1, characterized in that: The step of reading target data based on the second bit line voltage of the selected bit line comprises: In response to the second bit line voltage of the selected bit line being greater than the reference voltage, the target data is read as 1; or, In response to the second bit line voltage of the selected bit line being less than the reference voltage, the target data is read as 0.

5. The data reading method according to claim 1, characterized in that: After detecting the first bit line voltage of the selected bit line, the data reading method further includes: In response to the first bit line voltage of the selected bit line being greater than the reference voltage, the target data is read as 1.

6. The data reading method according to claim 1, characterized in that: Before the voltage of the selected word line is raised to the first word line voltage, the data reading method further comprises: The selected bit line is discharged to a starting bit line voltage; the starting bit line voltage is less than the reference voltage.

7. The data reading method according to any one of claims 1 to 6, characterized in that: After reading the target data, the data reading method further includes: The selected word line and the selected bit line are grounded.

8. A selector-only memory, characterized in that include: Memory cell array and peripheral circuits; wherein, The memory cell array comprises: a plurality of rows of word lines and a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines; The peripheral circuit is coupled to the multiple rows of word lines and the multiple columns of bit lines; The peripheral circuit is configured to increase the voltage of the selected word line to a first word line voltage and detect a first bit line voltage of the selected bit line; and, in response to the first bit line voltage of the selected bit line being less than a reference voltage, increase the voltage of the selected word line to a second word line voltage and detect the second bit line voltage of the selected bit line; and, based on the second bit line voltage of the selected bit line, read target data; wherein the second word line voltage is greater than the first word line voltage.

9. The selector-only memory according to claim 8, characterized in that The peripheral circuit is further configured to increase the voltage of the unselected bit line to a compensation voltage in response to the voltage of the selected word line increasing to a second word line voltage; wherein the compensation voltage is less than the first word line voltage and greater than the voltage of the ground terminal.

10. A memory system, characterized in that: include: One or more selector-only memories as claimed in claim 8 or 9, and a memory controller; The memory controller is coupled to the selector-only memory; the memory controller controls the selector-only memory.

Images