Memory device and method of operating a memory device

Abstract

The present disclosure relates to a memory device and a method for operating the memory device. The memory device includes a memory block, a voltage generator, a pass switch group that connects or blocks a global line and a local line to each other in response to a block selection voltage, a decoder, and a logic circuit, the logic circuit being configured to control the decoder and the voltage generator so that the local line is floated after initializing a channel of a string, and the voltage of the global line is lower than the voltage of the global line when the channel of the string is initialized, and when a programming operation of a selected memory cell included in a selected page of the memory block is completed, the channel of the string is initialized and the local line is floated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0076692 filed on June 23, 2020 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a memory device and a method of operating the memory device, and more particularly, the present disclosure relates to a memory device capable of performing a program operation and a method of operating the program operation. Background Art

[0004] A memory device may store data or output stored data. For example, a memory device may be a volatile memory device in which stored data is lost when power is turned off, or a memory device may be a nonvolatile memory device in which stored data is retained even if power is turned off. A memory device may include: a memory cell array in which data is stored; a peripheral circuit capable of performing programming, reading, or erasing operations; and a logic circuit capable of controlling the peripheral circuit.

[0005] The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The memory cells may be connected in series to each other between the bit line and the source line, and a string may be configured. The memory cells included in different strings and connected to the same word line may configure a page. The programming operation and the read operation may be performed in units of pages. The programming operation may include a sub-programming operation to increase the threshold voltage of the selected memory cell, and a verification operation to determine whether the threshold voltage of the selected memory cell is increased to a target voltage. The sub-programming operation and the verification operation may configure a loop, and a plurality of loops may be performed in the programming operation. When a plurality of loops are performed, the programming voltage may be gradually increased. This programming method is referred to as an incremental step pulse programming (ISPP) method. Summary of the invention

[0006] A memory device according to an embodiment of the present disclosure may include: a memory block including a plurality of strings including a plurality of memory cells connected to a local line; a voltage generator configured to generate an operating voltage and output the operating voltage to a global line; a pass switch group that connects or blocks the global line and the local line to each other in response to a block selection voltage; a decoder configured to output the block selection voltage in response to a row address; and a logic circuit configured to control the decoder and the voltage generator so that the local line is floated after a channel of the string is initialized, and a voltage of the global line is lower than a voltage of the global line when the channel of the string is initialized, and when a programming operation of a selected memory cell included in a selected page of the memory block is completed, the channel of the string is initialized and the local line is floated.

[0007] A method for operating a memory device according to an embodiment of the present disclosure may include: providing a voltage generator that outputs an operating voltage through a global line, a pass switch that transmits the operating voltage applied to the global line to a local line, and a memory block including a plurality of memory cells connected to the local line; connecting the global line and the local line to each other; performing a programming operation on a selected memory cell connected to a selected word line among the local lines; initializing a channel of a string including the memory cell when the programming operation is completed; floating the channel when the channel is initialized; blocking the global line and the local line from each other when the channel is floated; and lowering the voltage of a global word line included in the global line when the local line is floated. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram for describing a memory device according to one embodiment of the present disclosure.

[0009] Figure 2 Is used to describe Figure 1 Diagram of a memory cell array.

[0010] Figure 3 is a diagram for specifically describing an i-th memory block according to one embodiment of the present disclosure.

[0011] Figure 4 is a diagram for specifically describing the structure of a memory cell.

[0012] Figure 5 is a diagram for specifically describing a row decoder according to an embodiment of the present disclosure.

[0013] Figure 6 Is used to describe Figure 5 The through switch group diagram is shown.

[0014] Figure 7 and Figure 8 is a diagram for describing an operating method according to the first embodiment of the present disclosure.

[0015] Fig. 9 and Fig.10 is a diagram for describing an operating method according to a second embodiment of the present disclosure.

[0016] Fig.11 and Fig.12 is a diagram for describing an operating method according to a third embodiment of the present disclosure.

[0017] Fig.13 is a diagram for specifically describing a row decoder according to another embodiment of the present disclosure.

[0018] Fig.14 Is used to describe Fig.13 The through switch group diagram is shown.

[0019] Fig.15 is a diagram for describing a memory system including a memory device of the present disclosure.

[0020] Fig.16 is a diagram for describing another memory system including the memory device of the present disclosure. DETAILED DESCRIPTION

[0021] One embodiment of the present disclosure may provide a memory device and an operating method thereof capable of suppressing the occurrence of errors during a program operation.

[0022] The present technology can improve the reliability of a read operation of a programmed memory block by suppressing the occurrence of errors during a programming operation.

[0023] Figure 1 is a diagram for describing a memory device according to one embodiment of the present disclosure.

[0024] refer to Figure 1 , the memory device 1100 may include: a memory cell array 110 in which data is stored; peripheral circuits 120 to 160 that perform programming, reading, and erasing operations; and a logic circuit 170 that controls the peripheral circuits. The peripheral circuits 120 to 160 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0025] The memory cell array 110 may include a plurality of memory blocks, and each of the memory blocks may include a plurality of memory cells. The memory blocks may be connected to the row decoder 130 through the first local line LL1 to the i-th local line LLi, and may be connected to the page buffer group 140 through the bit line BL. In one embodiment, i may be an integer greater than 1.

[0026] The voltage generator 120 may generate an operation voltage required for a programming, reading or erasing operation in response to an operation code Cop. For example, the voltage generator 120 may generate an operation voltage including a programming voltage, a reading voltage, an erasing voltage, a pass voltage, a shutoff voltage, etc., and may adjust the output time of the operation voltage according to a setting time. The voltage generator 120 may transmit the operation voltage to the row decoder 130 through a global line GL.

[0027] The row decoder 130 may select a memory block in response to a row address ADDR#, and may transmit an operating voltage received through a global line GL to a local line (any one of LL1 to LLi) connected to the selected memory block. Each of the first to i-th local lines LL1 to LLi may include a plurality of word lines, a drain selection line, and a source selection line.

[0028] During a program operation, the page buffer group 140 may temporarily store data received from the outside, and may temporarily store data sensed from a memory cell during a verification or read operation. The page buffer group 140 may temporarily store data or precharge a bit line in response to a page buffer signal PBSIG, and may sense a voltage or current of a bit line.

[0029] The column decoder 150 may transfer data between the input / output circuit 160 and the page buffer group 140 in response to the column address ADDC.

[0030] The input / output circuit 160 may receive a command CMD and an address ADD from an external device (e.g., a controller) through an input / output line IO, and input or output data. During a program operation, the input / output circuit 160 may transmit the command CMD and the address ADD input through the input / output line IO to the logic circuit 170, and transmit the data to the page buffer group 140. During a read operation, the input / output circuit 160 may output data read from the page buffer group 140 to an external device.

[0031] The logic circuit 170 may be configured by software and hardware capable of controlling peripheral circuits in response to the command CMD and the address ADD. The logic circuit 170 may output an operation code Cop, a page buffer signal PBSIG, a row address ADDR#, and a column address ADDC in response to the command CMD and the address ADD.

[0032] Figure 2 Is used to describe Figure 1 Diagram of a memory cell array.

[0033] refer to Figure 2, the memory cell array 110 may include a first memory block BLK1 to an i-th memory block BLKi. In a single-plane structure, the first memory block BLK1 to the i-th memory block BLKi may configure the memory cell array 110. In a multi-plane structure, the first memory block BLK1 to the i-th memory block BLKi may configure one plane, and the memory cell array 110 may include a plurality of planes. The first memory block BLK1 to the i-th memory block BLKi may be configured to be identical to each other, and among the first memory block BLK1 to the i-th memory block BLKi, the i-th memory block BLKi is specifically described as follows as an embodiment.

[0034] Figure 3 is a diagram for specifically describing an i-th memory block according to one embodiment of the present disclosure.

[0035] refer to Figure 3 , the i-th memory block BLKi may include a plurality of memory strings ST11 to ST1m and ST21 to ST2m connected between the bit lines BL1 to BLm and the source line SL. Each of the memory strings ST11 to ST1m and ST21 to ST2m may extend along the Z direction. Here, the Z direction may be a direction in which the memory cells MC are stacked, and may be a direction perpendicular to the substrate. m is an integer equal to or greater than 2.

[0036] Each of the memory strings ST11 to ST1 m and ST21 to ST2 m may include a source select transistor SST, a memory cell MC, and a drain select transistor DST connected in series.

[0037] The source selection transistor SST included in one of the memory strings (any one of ST11 to ST1m and ST21 to ST2m) may be connected in series between the memory cell MC and the source line SL. The gate electrode of the source selection transistor SST may be connected to the source selection line SSL. In addition, the source selection transistors SST located on the same layer may be connected to the same source selection line SSL.

[0038] The memory cells MC included in one of the memory strings (any one of ST11 to ST1m and ST21 to ST2m) may be connected in series between at least one source selection transistor SST and at least one drain selection transistor DST. The gate electrode of the memory cell MC may be connected to the word line WL. An operating voltage (programming voltage, pass voltage, read voltage, etc.) required for driving may be applied to each of the word lines WL. A group of memory cells connected to the same word line WL becomes a page PG. The memory cell MC may be programmed or read in units of page PG.

[0039] The drain selection transistor DST included in one of the memory strings (any one of ST11 to ST1m and ST21 to ST2m) can be connected in series between the bit lines BL1 to BLm and the memory cell MC. The gate electrode of the drain selection transistor DST is connected to the drain selection line DSL. Among the drain selection transistors DST included in the memory strings ST11 to ST1m or ST21 to ST2m arranged in the same row (X direction), the drain selection transistors DST formed on the same layer can be connected to the same drain selection line DSL. In addition, the drain selection transistors DST arranged in different rows (X direction) can be connected to different drain selection lines DSL.

[0040] A source select line SSL, a word line WL, and a drain select line DSL connected to an i-th memory block BLKi may be included in an i-th local line LLi.

[0041] The structures of some memory cells 31 included in the eleventh string ST11 are specifically described as follows.

[0042] Figure 4 is a diagram for specifically describing the structure of a memory cell.

[0043] refer to Figure 4 , the memory block may be formed in a stacked structure including a plurality of word lines WL and interlayer insulating layers IT stacked in a direction Z perpendicular to the substrate, and plugs PLG vertically passing through the word lines WL and the interlayer insulating layers IT. The word lines WL and the interlayer insulating layers IT may be alternately stacked. The word lines WL may be formed of a conductive material, and the interlayer insulating layers IT may be formed of an insulating material.

[0044] The plug PLG may be formed in a vertical hole VH vertically passing through the word line WL and the interlayer insulating layer IT. The plug PLG may include a gap filling layer GF, a channel layer CL, and a memory layer MR. The gap filling layer GF may be formed in a columnar shape extending from the center of the vertical hole VH in the vertical direction Z. The channel layer CL may be formed in a columnar shape surrounding the sidewall of the gap filling layer GF, and the memory layer MR may be formed in a columnar shape surrounding the sidewall of the channel layer CL. The gap filling layer GF may be formed of an insulating material, and the channel layer CL may be formed of polysilicon. Alternatively, the channel layer CL may be formed in a columnar shape to replace the gap filling layer GF in the center of the vertical hole VH. In the present embodiment described below, the plug PLG in which the gap filling layer GF is formed in the center of the vertical hole VH is described as an example.

[0045] The memory layer MR may include a columnar tunneling insulating layer TO surrounding the sidewall of the channel layer CL, a columnar charge trapping layer TR surrounding the sidewall of the tunneling insulating layer TO, and a columnar blocking layer BK surrounding the sidewall of the charge trapping layer TR. The tunneling insulating layer TO may be formed of an oxide layer, which is an insulating material, the charge trapping layer TR may be formed of a nitride layer, and the blocking layer BK may be formed of an oxide layer, which is an insulating material. The tunneling insulating layer TO is a layer in which electrons tunnel between the channel layer CL and the charge trapping layer TR, the charge trapping layer TR is a layer that traps electrons, and the blocking layer BK is a layer that blocks the electrons trapped in the charge trapping layer TR from moving to the word line WL.

[0046] A memory cell may be formed in the plug PLG adjacent to the word line WL, and the width of the memory cell may be the same as the width of the plug PLG. For example, since the plug PLG is formed inside a vertical hole VH vertically passing through the word line WL and the interlayer insulating layer IT, the width of the plug PLG is determined according to the width of the vertical hole VH.

[0047] When a positive voltage is applied to the word line WL, a channel may be formed in the channel layer CL included in the memory cell. For example, when a positive voltage higher than the threshold voltage of the memory cell is applied to the word line WL, a channel may be formed in the channel layer CL included in the memory cell, and thereby the memory cell may be turned on. The voltage of the channel layer CL becomes a channel voltage, and the channel voltage may change according to the threshold voltage of the memory cell or the voltage applied to the word line WL.

[0048] Figure 5 is a diagram for specifically describing a row decoder according to an embodiment of the present disclosure.

[0049] refer to Figure 5, the row decoder 130 may include first through switch groups PSG1 to i-th through switch groups PSGi connected to the first memory block BLK1 to the i-th memory block BLKi, and first decoders DEC1 to i-th decoders DECi that selectively start the first through switch groups PSG1 to the i-th through switch groups PSGi. For example, the i-th decoder DECi and the i-th through switch group PSGi may form a pair, and select or not select the i-th memory block BLKi according to the i-th row address ADDRi. The first through switch groups PSG1 to the i-th through switch groups PSGi may be connected between the global line GL and the first local line LL1 to the i-th local line LLi, respectively. That is, the operating voltage output from the voltage generator 120 may be transmitted to the first through switch groups PSG1 to the i-th through switch groups PSGi in common through the global line GL. The first through switch groups PSG1 to the i-th through switch groups PSGi may be connected to the first decoders DEC1 to the i-th decoders DECi through the block selection lines BLKSEL1 to BLKSELi.

[0050] During a programming operation, when the voltage generator 120 outputs an operating voltage Vop for a programming operation to the global line GL, the operating voltage Vop may be transmitted to the first through switch groups PSG1 to the i-th through switch groups PSGi in common. When the first memory block BLK1 is selected, the first decoder DEC1 may output a block selection voltage of a positive voltage to the first block selection line BLKSEL1 in response to the first row address ADDR1. When the block selection voltage is applied through the first block selection line BLKSEL1, the first through switch group PSG1 may connect the global line GL and the first local line LL1 to each other. At this time, since the second through decoders DEC2 to the i-th decoders DECi are deactivated according to the second address ADDR2 to the i-th address ADDRi, the second through switch groups PSG2 to the i-th through switch groups PSGi block the global line GL and the second local line LL2 to the i-th local line LLi from each other. Therefore, the second local line LL2 to the i-th local line LLi may be floated. Since the operating voltage Vop is applied to the first local line LL1 , a program operation on the first memory block BLK1 may be performed.

[0051] When a turn-off voltage is applied through the first block selection line BLKSEL1 , the first pass switch group PSG1 may block the global line GL and the first local line LL1 from each other.

[0052] Figure 6 Is used to describe Figure 5 The through switch group diagram is shown.

[0053] refer to Figure 6, the i-th pass switch group PSGi may include the first pass switch PS1 to the n+2-th pass switch PSn+2. The first pass switch PS1 to the n+2-th pass switch PSn+2 may be connected between the global line GL and the i-th local line LLi, and the gates of the first pass switch PS1 to the n+2-th pass switch PSn+2 may be commonly connected to the i-th block selection line BLKSELi. For example, the first pass switch PS1 may be connected between the global source selection line GSSL and the source selection line SSL, the second pass switch PS2 to the n+1-th pass switch PSn+1 may be connected between the first global word line GWL1 to the n-th global word line GWLn and the first word line WL1 to the n-th word line WLn, and the n+2-th pass switch PSn+2 may be connected between the global drain selection line GDSL and the drain selection line DSL.

[0054] When a block selection voltage of a positive voltage is applied to the i-th block selection line BLKSELi, the first to n+2-th pass switches PSn+2 may be turned on at the same time. When the first to n+2-th pass switches PSn+2 are all turned on, the global line GL is connected to the i-th local line LLi. At this time, the operation voltage Vop applied to the global source selection line GSSL, the first to n-th global word lines GWL1 to GWLn, and the global drain selection line GDSL may be transmitted to the source selection line SSL, the first to n-th word lines WL1 to WLn, and the drain selection line DSL.

[0055] When the turn-off voltage is applied to the i-th block selection line BLKSELi, the first pass switch PS1 to the n+2th pass switch PSn+2 may be turned off at the same time. When the first pass switch PS1 to the n+2th pass switch PSn+2 are all turned off, the i-th pass switch group PSG1 may block the global line GL and the i-th local line LLi from each other. Therefore, the operation voltage Vop is applied to the global source selection line GSSL, the first global word line GWL1 to the n-th global word line GWLn, and the global drain selection line GDSL, but the source selection line SSL, the first word line WL1 to the n-th word line WLn, and the drain selection line DSL may be floated. In one embodiment, when the pass switch is turned off, the operation voltage Vop applied to the global source selection line GSSL, the first global word line GWL1 to the n-th global word line GWLn, and the global drain selection line GDSL is prevented from being transmitted to the source selection line SSL, the first word line WL1 to the n-th word line WLn, and the drain selection line DSL.

[0056] Figure 7 and Figure 8 is a diagram for describing an operating method according to the first embodiment of the present disclosure.

[0057] Figure 7is a diagram for briefly describing a program operation method of an i-th memory block according to a first embodiment, and Figure 8 is a diagram for specifically describing a program operation method of an i-th memory block according to the first embodiment.

[0058] refer to Figure 7 , a programming operation on the selected memory cell may be performed until the threshold voltage of the selected memory cell increases to a target voltage. For example, a programming operation may be performed by applying a programming voltage to a selected word line connected to the selected memory cell. The programming operation may be performed by an incremental step pulse programming (ISPP) method that gradually increases the programming voltage applied to the selected word line. In the programming operation of the ISPP method, a first loop LP1 to an nth loop LPn (n is a positive integer) may be performed. Each of the first loop LP1 to the nth loop LPn may include a sub-programming operation of increasing the threshold voltage of the memory cell using the programming voltage, and a verification operation of determining whether the threshold voltage of the memory cell increases to the target voltage. For example, in the first loop LP1, a first sub-programming operation SPGM1 using a first programming voltage may be performed, and after performing the first sub-programming operation SPGM1, a first verification operation V1 may be performed. When the threshold voltage of the selected memory cell reaches the target voltage, the first verification operation V1 passes, and the programming operation on the selected memory cell may be ended. When it is detected that the threshold voltage of at least one of the selected memory cells does not reach the target voltage, the first verification operation V1 may be determined to be a failure, and the second loop LP2 may be performed. In the second loop LP2, a second sub-programming operation SPGM2 may be performed, the second sub-programming operation SPGM2 uses a programming voltage higher than the programming voltage used in the first sub-programming operation SPGM1, and a second verification operation V2 may be performed, the second verification operation V2 being used to determine whether the threshold voltage of the memory cell on which the second sub-programming operation SPGM2 is performed increases to the target voltage. In such a method, the first loop LP1 to the nth loop LPn may be performed until the threshold voltage of the selected memory cell increases to the target voltage. That is, the nth loop LPn may include the nth sub-programming operation SPGMn and the nth verification operation Vn, and when the nth verification operation Vn passes, the programming operation on the selected memory cell may be ended.

[0059] When the program operation of the selected memory cells included in the selected page is completed, a post-operation POP may be continuously performed for a next operation of the selected page.

[0060] For example, in the post-operation POP of the first embodiment, a channel initialization operation CI and a channel maintenance operation CM may be performed. The channel initialization operation CI and the channel maintenance operation CM may be performed to prevent the following phenomenon: the voltage of the channel is lower than the reference level due to coupling according to the voltage drop of the word line when the word line to which a positive voltage is applied is discharged in a programming operation. Here, the reference level may be 0V. The post-operation POP according to the first embodiment is specifically described as follows.

[0061] refer to Figure 8 , in the period T1 to T2, the nth verification operation Vn of the nth loop LPn may be performed. When the nth verification operation Vn passes, the post-operation POP may be performed starting from the time point T2.

[0062] While performing a programming operation, a block selection voltage Vblks having a positive voltage may be applied to the i-th block selection line BLKSELi. Thus, the voltage applied to the global line GL may be transmitted to the i-th local line LLi. For example, at time point T1, when a verification voltage Vvf is applied to the global selected word line Sel_GWL, the verification voltage Vvf may be transmitted to the selected word line Sel_WL, and when a pass voltage Vpass is applied to the global unselected word line Unsel_GWL, the pass voltage Vpass may be transmitted to the unselected word line Unsel_WL. When a turn-on voltage Von is applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL.

[0063] The off voltage Voff may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and thus, the off voltage Voff may also be applied to the unselected drain selection line Unsel_DSL and the unselected source selection line Unsel_SSL. The ground voltage GND may be applied to the source line SL.

[0064] At the time point T2, when the nth verification operation Vn passes, since the program operation of the selected page is completed, the post-operation POP may be performed from the time point T2. Figure 8In the first embodiment shown, the post operation POP may include a channel initialization operation CI and a channel maintenance operation CM. The channel initialization operation CI may be performed in periods T2 to T4. The channel initialization operation CI may include applying an on voltage Von to global selection lines Sel_GDSL, Sel_GSSL, Unsel_GDSL, and Unsel_GSSL (T2 to T3), applying an off voltage Voff to selection lines Sel_GDSL, Sel_GSSL, Unsel_GDSL, and Unsel_GSSL (①), floating local lines (②), and discharging global word lines (③). Steps ①, ②, and ③ may be performed sequentially.

[0065] The channel initialization operation CI is specifically described as follows.

[0066] At time point T2, the turn-on voltage Von may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL. That is, in period T2 to T3, since the turn-on voltage Von is applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may also be transmitted to the unselected drain selection line Unsel_DSL and the unselected source selection line Unsel_SSL, and the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL. Thus, the channels of all strings included in the i-th memory block BLKi may be initialized.

[0067] At time point T3, a turn-off voltage Voff may be applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, and the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Sel_GSSL (①). In addition, at time point T3, a compensation voltage Vcom having a positive voltage level may be applied to the global word lines Sel_GWL and Unsel_GWL. The compensation voltage Vcom may have a level higher than the verification voltage Vvf and lower than the pass voltage Vpass. Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi in the period T3 to T4, the turn-off voltage Voff may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL included in the i-th local line LLi. When the turn-off voltage Voff is applied to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL, the channel of the string including the selected memory cell may be floated. In addition, the compensation voltage Vcom may be transmitted to the selected word line Sel_WL and the unselected word line Unsel_WL included in the i-th local line LLi.

[0068] The channel maintenance operation CM is specifically described as follows. At time point T4, the off voltage Voff may be applied to the i-th block selection line BLKSELi to float the i-th local line LLi (②). The off voltage Voff may be the ground voltage GND. When the off voltage Voff is applied to the i-th block selection line BLKSELi, the global line GL connected to the i-th local line LLi is Figure 6 All of the pass switches PS1 to PSn+2 are turned off, so the connection between the global line GL and the i-th local line LLi can be blocked. Thus, the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL can be floated in a state where the off voltage Voff is applied, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated in a state where the compensation voltage Vcom is applied.

[0069] At the time point T5, the voltage of the global word lines Sel_GWL and Unsel_GWL may be adjusted to be low. For example, at the time point T5, the voltage applied to the global word lines Sel_GWL and Unsel_GWL may be reduced to a level lower than the voltage applied to the global word lines Sel_GWL and Unsel_GWL when the channel initialization operation CI is performed. For example, at the time point T5, the voltage of the global word lines Sel_GWL and Unsel_GWL may be reduced to the ground voltage GND, or reduced to a positive voltage Vpos that is higher than the ground voltage GND and lower than the verification voltage Vvf. At this time, due to Figure 6 All of the pass switches PS1 to PSn+2 are turned off, so the word lines Sel_WL and Unsel_WL included in the i-th local line LLi can be maintained in a floating FLT state. Therefore, in the memory block to which the word lines Sel_WL and Unsel_WL included in the i-th local line LLi are connected, the phenomenon that the voltage of the channel of the string is lower than the reference level can be prevented. That is, when the voltage of the channel of the string is lower than the reference level, the reliability of the data of the memory cell may be reduced when the next read operation to be performed is performed. Therefore, in one embodiment, the voltage of the channel may not be reduced to below the reference level to improve the reliability of the memory device. Therefore, it is preferred that the voltage applied to the global word lines Sel_GWL and Unsel_GWL is reduced to a positive voltage Vpos higher than the ground voltage GND at time point T5. Since at Figure 6 Leakage may occur in the through switches PS1 to PSn+2, so in order to effectively prevent the voltage of the word lines Sel_WL and Unsel_WL included in the i-th local line LLi from decreasing, Figure 1 The logic circuit 170 can control Figure 1 The voltage generator 120 enables the positive voltage Vpos to be applied to the global word lines Sel_GWL and Unsel_GWL.

[0070] Fig. 9 and Fig.10 is a diagram for describing an operating method according to a second embodiment of the present disclosure.

[0071] Fig. 9 is a diagram for briefly describing an operation method according to a second embodiment, and Fig.10 is a diagram for specifically describing the operation method according to the second embodiment.

[0072] refer to Fig. 9 , the programming operation of the selected memory cell can be compared with the reference Figure 7 The described method is performed exactly the same, and in the post-operation POP, the n+1th sub-programming operation SPGMn+1 may be additionally performed. For example, when the nth verification operation Vn performed in the nth loop LPn passes, after performing the n+1th sub-programming operation SPGMn+1, the channel initialization operation CI and the channel maintenance operation CM may be performed. The n+1th sub-programming operation SPGMn+1 may be performed to narrow the distribution width of the threshold voltage of the memory cell by additionally applying a programming voltage to the selected word line Sel_WL after the programming operation of the selected page is completed.

[0073] refer to Fig.10, in the period T1 to T2, the nth verification operation Vn of the nth loop LPn may be performed. When the nth verification operation Vn passes, the post-operation POP may be performed starting from the time point T2.

[0074] While performing a programming operation, a block selection voltage Vblks having a positive voltage may be applied to the i-th block selection line BLKSELi. Thus, the voltage applied to the global line GL may be transmitted to the i-th local line LLi. For example, at time point T1, when a verification voltage Vvf is applied to the global selected word line Sel_GWL, the verification voltage Vvf may be transmitted to the selected word line Sel_WL, and when a pass voltage Vpass is applied to the global unselected word line Unsel_GWL, the pass voltage Vpass may be transmitted to the unselected word line Unsel_WL. When a turn-on voltage Von is applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL.

[0075] The off voltage Voff may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and thus, the off voltage Voff may also be applied to the unselected drain selection line Unsel_DSL and the unselected source selection line Unsel_SSL. The ground voltage GND may be applied to the source line SL.

[0076] At the time point T2, when the nth verification operation Vn passes, since the program operation of the selected page is completed, the post-operation POP may be performed from the time point T2. Fig.10 In the second embodiment shown, the post operation POP may include an n+1th sub-programming operation SPGMn+1 and a channel initialization operation CI.

[0077] At time point T2, both the global line GL and the i-th local line LLi may be discharged, and then a programming voltage Vpgm may be applied to the selected global word line Sel_GWL. The programming voltage Vpgm may have the same level as the programming voltage used in the n-th sub-programming operation SPGMn, or may have a level lower than the programming voltage used in the n-th sub-programming operation SPGMn. When the programming voltage Vpgm is applied to the selected global word line Sel_GWL, a pass voltage Vpass may be applied to the unselected global word line Unsel_GWL, and a turn-on voltage Von may be applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL. At this time, a turn-off voltage Voff may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL.

[0078] Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi, the voltage applied to the global line GL may be transferred to the i-th local line LLi. After applying the program voltage Vpgm to the selected word line Sel_WL during a predetermined time, a channel initialization operation CI may be performed.

[0079] The channel initialization operation CI may include applying an on voltage Von to global selection lines Sel_GDSL, Sel_GSSL, Unsel_GDSL, and Unsel_GSSL (T2 to T3), applying an off voltage Voff to the selection lines Sel_GDSL, Sel_GSSL, Unsel_GDSL, and Unsel_GSSL (①), floating local lines (②), and discharging global word lines (③). Steps ①, ②, and ③ may be performed sequentially.

[0080] The channel initialization operation CI is specifically described as follows.

[0081] At time point T3, a compensation voltage Vcom lower than the program voltage Vpgm may be applied to the selected global word line Sel_GWL. The compensation voltage Vcom may have a level lower than the pass voltage Vpass and higher than the ground voltage GND. Thus, voltages having the same level as each other may be applied to the selected word line Sel_WL and the unselected word line Unsel_WL.

[0082] After applying the compensation voltage Vcom to the selected word line Sel_WL during a predetermined time, the turn-on voltage Von may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL. That is, since the turn-on voltage Von is applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may also be transmitted to the unselected drain selection line Unsel_DSL and the unselected source selection line Unsel_SSL, and the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL. Thus, the channels of all strings included in the i-th memory block BLKi may be initialized.

[0083] At time point T4, the off voltage Voff may continue to be applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, and the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL (①). In addition, at time point T4, a compensation voltage Vcom having a positive voltage level may be applied to the global word lines Sel_GWL and Unsel_GWL. The compensation voltage Vcom may have a level higher than the verification voltage Vvf and lower than the pass voltage Vpass. Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi in the period T4 to T5, the off voltage Voff may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL included in the i-th local line LLi. When the off voltage Voff is applied to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL, the channel of the string including the selected memory cell may be floated. In addition, the compensation voltage Vcom may be transmitted to the selected word line Sel_WL and the unselected word line Unsel_WL included in the i-th local line LLi.

[0084] The channel maintenance operation CM is described specifically as follows.

[0085] At time point T5, the off voltage Voff may be applied to the i-th block selection line BLKSELi to float the i-th local line LLi (②). The off voltage Voff may be the ground voltage GND. When the off voltage Voff is applied to the i-th block selection line BLKSELi, the global line GL connected to the i-th local line LLi is Figure 6All of the pass switches PS1 to PSn+2 are turned off, so the connection between the global line GL and the i-th local line LLi can be blocked. Thus, the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL can be floated in a state where the off voltage Voff is applied, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated in a state where the compensation voltage Vcom is applied.

[0086] At the time point T6, the voltages of the global word lines Sel_GWL and Unsel_GWL may be adjusted to be low. For example, at the time point T6, the voltages applied to the global word lines Sel_GWL and Unsel_GWL may be reduced to have a level lower than the voltages applied to the global word lines Sel_GWL and Unsel_GWL when the channel initialization operation CI is performed. For example, at the time point T6, the voltages of the global word lines Sel_GWL and Unsel_GWL may be reduced to the ground voltage GND, or to a positive voltage Vpos that is higher than the ground voltage GND and lower than the verification voltage Vvf. At this time, due to Figure 6 All of the pass switches PS1 to PSn+2 are turned off, so the word lines Sel_WL and Unsel_WL included in the i-th local line LLi can be maintained in a floating FLT state. Therefore, in the memory block to which the word lines Sel_WL and Unsel_WL included in the i-th local line LLi are connected, the phenomenon that the voltage of the channel of the string is lower than the reference level can be prevented. That is, when the voltage of the channel of the string is lower than the reference level, the reliability of the data of the memory cell may be reduced when the next read operation to be performed is performed. Therefore, in the present embodiment, the voltage of the channel may not be reduced to below the reference level to improve the reliability of the memory device. Therefore, it is preferred that the voltage applied to the global word lines Sel_GWL and Unsel_GWL is reduced to a positive voltage Vpos higher than the ground voltage GND at time point T6. Since at Figure 6 Leakage may occur in the through switches PS1 to PSn+2, so in order to effectively prevent the voltage of the word lines Sel_WL and Unsel_WL included in the i-th local line LLi from decreasing, Figure 1 The logic circuit 170 can control Figure 1 The voltage generator 120 enables the positive voltage Vpos to be applied to the global word lines Sel_GWL and Unsel_GWL.

[0087] Fig.11 and Fig.12 is a diagram for describing an operating method according to a third embodiment of the present disclosure.

[0088] Fig.11is a diagram for briefly describing an operation method according to a third embodiment, and Fig.12 is a diagram for specifically describing the operation method according to the third embodiment.

[0089] refer to Fig.11 , the programming operation of the selected memory cell can be compared with the reference Figure 7 The described method is performed exactly the same, and in the post-operation POP, the n+1th sub-programming operation SPGMn+1 and the channel compensation operation CP may be additionally performed. For example, when the nth verification operation Vn performed in the nth loop LPn passes, the n+1th sub-programming operation SPGMn+1, the channel initialization operation CI, and the channel retention operation CM may be performed sequentially. The n+1th sub-programming operation SPGMn+1 may be performed to narrow the distribution width of the threshold voltage of the memory cell by additionally applying a programming voltage to the selected word line Sel_WL after the programming operation of the selected page is completed. The channel initialization operation CI and the channel retention operation CM may be performed to prevent the following phenomenon: the voltage of the channel is lower than the reference level due to coupling according to the voltage drop of the word line when the word line to which a positive voltage is applied is discharged in the programming operation. In Fig.11 In the third embodiment shown, Fig. 9 The channel initialization operation CI shown is different and may include operations of discharging the lines and sequentially reducing the voltage applied to the word lines.

[0090] refer to Fig.12 , in the period T1 to T2, the nth verification operation Vn of the nth loop LPn may be performed. When the nth verification operation Vn passes, the post-operation POP may be performed starting from the time point T2.

[0091] While performing a programming operation, a block selection voltage Vblks having a positive voltage may be applied to the i-th block selection line BLKSELi. Thus, the voltage applied to the global line GL may be transmitted to the i-th local line LLi. For example, at time point T1, when a verification voltage Vvf is applied to the global selected word line Sel_GWL, the verification voltage Vvf may be transmitted to the selected word line Sel_WL, and when a pass voltage Vpass is applied to the global unselected word line Unsel_GWL, the pass voltage Vpass may be transmitted to the unselected word line Unsel_WL. When a turn-on voltage Von is applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL.

[0092] The off voltage Voff may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and thus, the off voltage Voff may also be applied to the unselected drain selection line Unsel_DSL and the unselected source selection line Unsel_SSL. The ground voltage GND may be applied to the source line SL.

[0093] At the time point T2, when the nth verification operation Vn passes, since the program operation of the selected page is completed, the post-operation POP may be performed from the time point T2. Fig.12 In the third embodiment shown, the post operation POP may include an n+1th sub-programming operation SPGMn+1, a channel initializing operation CI, and a channel maintaining operation CM.

[0094] At time point T2, both the global line GL and the i-th local line LLi may be discharged, and then a programming voltage Vpgm may be applied to the selected global word line Sel_GWL. The programming voltage Vpgm may have the same level as the programming voltage used in the n-th sub-programming operation SPGMn, or may have a level lower than the programming voltage used in the n-th sub-programming operation SPGMn. When the programming voltage Vpgm is applied to the selected global word line Sel_GWL, a pass voltage Vpass may be applied to the unselected global word line Unsel_GWL, and a turn-on voltage Von may be applied to the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL. At this time, a turn-off voltage Voff may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL.

[0095] Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi, the voltage applied to the global line GL may be transferred to the i-th local line LLi. After applying the program voltage Vpgm to the selected word line Sel_WL during a predetermined time, a channel compensation operation CP may be performed in periods T3 to T5.

[0096] At time point T3, after both the global line GL and the i-th local line LLi are discharged, at time point T4, the compensation voltage Vcom may be applied to the global word lines Sel_GWL and Unsel_GWL, and the global drain selection line Sel_GDSL and the global source selection line Sel_GSSL. The compensation voltage Vcom may be set to a voltage lower than the pass voltage Vpass and higher than the verification voltage Vvf. Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi, the compensation voltage Vcom may be transmitted to the selected word line Sel_WL, the unselected word line Unsel_WL, and the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL. Before the start of time point T5, the turn-on voltage Von may be applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL. That is, since the turn-on voltage Von is applied to the unselected global drain selection line Unsel_GDSL and the unselected global source selection line Unsel_GSSL, and the selected global drain selection line Sel_GDSL and the selected global source selection line Sel_GSSL, the turn-on voltage Von may also be transmitted to the unselected drain selection line Unsel_DSL and the unselected source selection line Sel_SSL, and the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL. Thus, the channels of all strings included in the i-th memory block BLKi may be initialized.

[0097] At time point T5, the off voltage Voff may be applied to the global drain selection line Sel_GDSL and the global source selection line Sel_GSSL (①). Since the block selection voltage Vblks is applied to the i-th block selection line BLKSELi, the off voltage Voff may be transmitted to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL included in the i-th local line LLi. When the off voltage Voff is applied to the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL, the channel of the string including the selected memory cell may be floated.

[0098] In the period T5 to T6, the voltage of the global word lines Sel_GWL and Unsel_GWL may be gradually reduced. For example, when the compensation voltage Vcom is applied to the global word lines Sel_GWL and Unsel_GWL until the time point T5, a voltage lower than the compensation voltage Vcom may be gradually applied to the global word lines Sel_GWL and Unsel_GWL in the period T5 to T6. When the voltage applied to the global word lines Sel_GWL and Unsel_GWL is gradually reduced, the gradually reduced voltage may be sequentially applied to the selected word line Sel_WL and the unselected word line Unsel_WL included in the i-th local line LLi. In the period T5 to T6, the voltage of the global word lines Sel_GWL and Unsel_GWL may be reduced to a first positive voltage Vpos1 having a level higher than the ground voltage GND.

[0099] The channel maintenance operation CM is described specifically as follows.

[0100] At time point T6, the off voltage Voff may be applied to the i-th block selection line BLKSELi to float the i-th local line LLi (②). The off voltage Voff may be the ground voltage GND. When the off voltage Voff is applied to the i-th block selection line BLKSELi, the global line GL connected to the i-th local line LLi is Figure 6 All of the pass switches PS1 to PSn+2 are turned off, so the connection between the global line GL and the i-th local line LLi can be blocked. Thus, the selected drain selection line Sel_DSL and the selected source selection line Sel_SSL can be floated in a state where the off voltage Voff is applied, and the selected word line Sel_WL and the unselected word line Unsel_WL can be floated in a state where the first positive voltage Vpos1 is applied.

[0101] At time point T7, the global word lines Sel_GWL and Unsel_GWL may be reduced from the first positive voltage Vpos1 to the second positive voltage Vpos2 (③). The second positive voltage Vpos2 may be set to a level between the first positive voltage Vpos1 and the ground voltage GND. For example, at time point T7, the voltages of the global word lines Sel_GWL and Unsel_GWL may be reduced to the ground voltage GND, or to the second positive voltage Vpos2, which is higher than the ground voltage GND and lower than the first positive voltage Vpos1. At this time, due to Figure 6All of the pass switches PS1 to PSn+2 are turned off, so the word lines Sel_WL and Unsel_WL included in the i-th local line LLi can be maintained in a floating FLT state. Therefore, in the memory block to which the word lines Sel_WL and Unsel_WL included in the i-th local line LLi are connected, the phenomenon that the voltage of the channel of the string is lower than the reference level can be prevented. That is, when the voltage of the channel of the string is lower than the reference level, the reliability of the data of the memory cell may be reduced when the next read operation to be performed is performed. Therefore, in the present embodiment, the voltage of the channel may not be reduced to below the reference level to improve the reliability of the memory device. Therefore, it is preferred that the voltage applied to the global word lines Sel_GWL and Unsel_GWL is reduced to a second positive voltage Vpos2 higher than the ground voltage GND at time point T7. Since at Figure 6 Leakage may occur in the through switches PS1 to PSn+2, so in order to effectively prevent the voltage of the word lines Sel_WL and Unsel_WL included in the i-th local line LLi from decreasing, Figure 1 The logic circuit 170 can control Figure 1 The voltage generator 120 is configured to apply the second positive voltage Vpos2 to the global word lines Sel_GWL and Unsel_GWL. Therefore, in the memory block to which the word lines Sel_WL and Unsel_WL included in the i-th local line LLi are connected, the phenomenon that the voltage of the channel of the string is lower than the reference level can be prevented. That is, when the voltage of the channel of the string is lower than the reference level, when the read operation to be performed next is performed, the reliability of the data of the memory cell may be reduced. Therefore, in the present embodiment, the voltage of the channel may not be reduced to below the reference level to improve the reliability of the memory device.

[0102] Fig.13 is a diagram for specifically describing a row decoder according to another embodiment of the present disclosure.

[0103] refer to Fig.13, the row decoder 130a may include a plurality of decoders DEC1 to DEC(i / 2) and a plurality of pass switch groups PSG1 to PSGi, and one decoder may be configured to turn on or off two or more pass switch groups at the same time. To this end, a plurality of voltage generators may also be included. The number of voltage generators included may be the same as the number of pass switch groups operated by one decoder. For example, when the first pass switch group PSG1 and the second pass switch group PSG2 are commonly connected to the first decoder DEC1, since one decoder controls the two pass switch groups, the voltage generator may include a first voltage generator 120a and a second voltage generator 120b configured to output voltages to the corresponding first pass switch group PSG1 and the second pass switch group PSG2. That is, the first pass switch group PSG1 and the second pass switch group PSG2 may be commonly connected to the first block selection line BLKSEL1, and the first decoder DEC1 may output a block selection voltage to the first block selection line BLKSEL1 in response to the first row address ADDR1. As used herein with respect to occurrences, the words "simultaneously" and "concurrently" refer to occurrences that occur at overlapping time intervals. For example, if a first occurrence occurs within a first time interval, and a second occurrence occurs simultaneously within a second time interval, the first interval and the second interval at least partially overlap each other, such that there is a time when both the first occurrence and the second occurrence occur.

[0104] The first voltage generator 120a may be connected to the first pass switch group PSG1 through a first global line 1GL, and the second voltage generator 120b may be connected to the second pass switch group PSG2 through a second global line 2GL When one of the first and second voltage generators 120a and 120b is activated, the other may be deactivated.

[0105] As an example, a case in which the first memory block BLK1 is selected is described.

[0106] The first voltage generator 120a can output the operation voltage Vop through the first global line 1GL, and the second voltage generator 120b can output the ground voltage GND through the second global line 2GL. The operation voltage Vop is applied to the odd-numbered pass switch groups PSG1, PSG3, ... and PSGi-1 connected to the first global line 1GL. When the first decoder DEC1 outputs the block selection voltage to the first block selection line BLKSEL1 in response to the first row address ADDR1, the pass switches included in the first pass switch group PSG1 and the second pass switch group PSG2 can be turned on. In response to the second row address ADDR2 to the i / 2 row address ADDR(i / 2), all the remaining even-numbered pass switch groups PSG2, PSG4, ... and PSGi are disabled, and all the pass switches included in the even-numbered pass switch groups PSG2, PSG4, ... and PSGi can be turned off. Therefore, the operating voltage Vop may be transferred only to the first local line LL1 , the ground voltage GND may be applied to the second local line LL2 , and the remaining third to i-th local lines LL3 to LLi may be floated FLT.

[0107] Fig.14 Is used to describe Fig.13 The through switch group diagram is shown.

[0108] refer to Fig.14 , all gates of the pass switches PS1 to PSn+2 included in each of the first pass switch group PSG1 and the second pass switch group PSG2 may be commonly connected to the first block selection line BLKSEL1 .

[0109] The first pass switch PS1 to the n+2th pass switch PSn+2 included in the first pass switch group PSG1 may be connected between the first global line 1GL and the first local line LL1. For example, the first pass switch PS1 included in the first pass switch group PSG1 may be connected between the global source selection line GSSL included in the first global line 1GL and the source selection line SSL included in the first local line LL1. In this method, the second pass switch PS2 to the n+1th pass switch PSn+1 may be connected between the first global word line GWL1 to the nth global word line GWLn and the first word line WL1 to the nth word line WLn, and the n+2th pass switch PSn+2 may be connected between the global drain selection line GDSL and the drain selection line DSL. The first pass switch PS1 included in the second pass switch group PSG2 may be connected between the global source selection line GSSL included in the second global line 2GL and the source selection line SSL included in the second local line LL2. In this method, the second pass switch PS2 to the n+1th pass switch PSn+1 can be connected between the first global word line GWL1 to the nth global word line GWLn and the first word line WL1 to the nth word line WLn, and the n+2th pass switch PSn+2 can be connected between the global drain selection line GDSL and the drain selection line DSL.

[0110] When a positive block selection voltage is applied to the first block selection line BLKSEL1, since the first to n+2th pass switches PS1 to PSn+2 included in the first and second pass switch groups PSG1 and PSG2 are turned on at the same time, the second local line LL2 may be connected to the second global line 2GL, and the first local line LL1 may be connected to the first global line 1GL. Since the ground voltage GND is applied to the second global line 2GL, the ground voltage GND may be transmitted to the second local line LL2. Since the operation voltage Vop is applied to the first global line 1GL, the operation voltage Vop may be transmitted to the first local line LL1.

[0111] exist Fig.13 and Fig.14 In the device shown, programming operations and post-operations can be performed according to the above Figures 7 to 12 The embodiment shown is implemented.

[0112] Fig.15 is a diagram for describing a memory system including a memory device of the present disclosure.

[0113] refer to Fig.15 The memory system 1000 may include a memory device 1100 in which data is stored and a controller 1200 for communicating between the memory device 1100 and a host 2000 .

[0114] The memory system 1000 may include a plurality of memory devices 1100, and each memory device 1100 may perform a programming operation according to the above-described embodiment. The memory device 1100 may be connected to the controller 1200 through at least one channel. For example, a plurality of memory devices 1100 may be connected to one channel, and even when a plurality of channels are connected to the controller 1200, a plurality of memory devices 1100 may be connected to each channel.

[0115] The controller 1200 may communicate between the host 2000 and the memory device 1100. The controller 1200 may control the memory device 1100 according to a request of the host 2000, or may perform background operations to improve the performance of the memory system 1000 even without a request from the host 2000. The host 2000 may generate requests for various operations and output the generated requests to the memory system 1000. For example, the request may include a program request that may control a program operation, a read request that may control a read operation, an erase request that may control an erase operation, and the like.

[0116] The host 2000 can communicate with the memory system 1000 through various interfaces, such as Peripheral Component Interconnect Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0117] Fig.16 is a diagram for describing another memory system including the memory device of the present disclosure.

[0118] refer to Fig.16 , the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a controller 1200 , and a card interface 7100 .

[0119] The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

[0120] The memory device 1100 may perform a program operation according to the above-described embodiments, and during a read operation, data programmed in the memory device 1100 may be output through the card interface 7100 under the control of the controller 1200 .

[0121] The card interface 7100 may interface data exchange between the host 60000 and the controller 1200 according to a protocol of the host 60000. According to one embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface 7100 may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0122] When the memory system 70000 is connected to the host interface 6200 of the host 60000, the host interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor (μP) 6100. The host 60000 is, for example, a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box.

Claims

1. A memory device, comprising: a memory block including a plurality of strings including a plurality of memory cells connected to a local line; a voltage generator configured to generate an operating voltage and output the operating voltage to a global line; connecting the global line and the local line to each other or blocking each other in response to a block selection voltage through a switch group; a decoder configured to output the block selection voltage in response to a row address; as well as A logic circuit is configured to control the decoder and the voltage generator so that the local line is floated after the channel of the string is initialized and the voltage of the global line when the local line is floated is lower than the voltage of the global line when the channel of the string is initialized, and when the programming operation of the selected memory cell included in the selected page of the memory block is completed, the channel of the string is initialized and the local line is floated.

2. The memory device of claim 1, wherein the voltage generator is configured to output at least one of a program voltage, a verification voltage, a pass voltage, a compensation voltage, a turn-on voltage, a turn-off voltage, and a ground voltage through the global line.

3. The memory device according to claim 2, wherein the program voltage, the verification voltage, and the pass voltage are set to be higher than the ground voltage, The pass voltage is set higher than the verification voltage, The programming voltage is set higher than the pass voltage, and The compensation voltage is set to be higher than the verification voltage and lower than the pass voltage. 4 . The memory device according to claim 1 , wherein the pass switch group includes a plurality of switches connected between the global line and the local line and are simultaneously turned on or off according to the block selection voltage.

5. The memory device according to claim 2, wherein when the programming operation of the selected memory cell included in the selected page is completed, the logic circuit controls the voltage generator to float the channel by applying the turn-off voltage to the global word line included in the global line after initializing the channel by applying the turn-on voltage to the global drain selection line and the global source selection line included in the global line, the logic circuit controls the decoder to float the local line by blocking the global line and the local line from each other, and the logic circuit controls the voltage generator so that in a state in which the local line is floated, a low voltage is applied to the global word line included in the global line. 6 . The memory device of claim 5 , wherein the logic circuit controls the voltage generator so that the compensation voltage is applied to the global word line after the channel is floated. 7 . The memory device of claim 5 , wherein the low voltage applied to the global word line is a positive voltage higher than the ground voltage.

8. A method of operating a memory device, the method comprising: providing a voltage generator outputting an operating voltage through a global line, a pass switch transmitting the operating voltage applied to the global line to a local line, and a memory block including a plurality of memory cells connected to the local line; connecting the global line and the local line to each other; performing a program operation on a selected memory cell connected to a selected word line among the local lines; When the programming operation is completed, initializing a channel of a string including the plurality of memory cells; After the channel is initialized, floating the channel; When the channel is floated, blocking the global line and the local line from each other; as well as When the local lines are floated, a voltage of a global word line included in the global lines is lowered.

9. The method of claim 8, wherein initializing the channel comprises applying a turn-on voltage to a selection line connected to the string and supplying a ground voltage to a source line coupled to the string, wherein the selection line is disposed at an end of each of the strings and a word line is disposed between the selection lines.

10. The method of claim 9, wherein floating the channel comprises: applying an off voltage to a global selection line included in the global lines in a state in which the global lines and the local lines are connected to each other; transferring the off voltage applied to the global selection line to the selection line included in the local lines; and According to the turn-off voltage transmitted to the local line, a selection transistor connected to the selection line is turned off.

11. The method of claim 8, wherein blocking the global line and the local line from each other comprises turning off the pass switch.

12. The method of claim 8, further comprising: after the programming operation is completed and before floating the channel: discharging the local line; applying a programming voltage to the selected word line when the local line is discharged; applying a pass voltage to unselected word lines among the local lines; and A turn-on voltage is applied to a selection line among the local lines. 13 . The method of claim 12 , wherein discharging the local line is performed by discharging the global line in a state in which the global line and the local line are connected to each other. 14 . The method of claim 12 , wherein applying a program voltage to the selected word line comprises applying the program voltage to a selected global word line included in the global word lines. 15 . The method of claim 12 , wherein applying the pass voltage to the unselected word lines is performed by applying the pass voltage to unselected global word lines included in the global word lines. 16 . The method of claim 12 , wherein applying the turn-on voltage to the selection line is performed by applying the turn-on voltage to a global selection line included in the global lines.

17. The method according to claim 12, further comprising, after applying the turn-on voltage to the select line: discharging the local line; and A compensation voltage is applied to the local line. 18 . The method of claim 17 , wherein discharging the local line is performed by discharging the global line in a state in which the global line and the local line are connected to each other.

19. The method of claim 17, wherein applying the compensation voltage to the local line is performed by applying the compensation voltage to the global line in a state in which the global line and the local line are connected to each other.

20. The method of claim 17, wherein the compensation voltage is set to be lower than the pass voltage and higher than a ground voltage.

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