Refresh control circuit and memory

Abstract

The invention provides a refresh control circuit and a memory. The refresh control circuit comprises a refresh window control circuit and a refresh window generation circuit. The output end of the refresh window control circuit is connected to the input end of the refresh window generation circuit, and the refresh window control circuit is used for receiving a same-memory-bank refresh command and a full-memory-bank refresh command, so that in the same-memory-bank refresh process corresponding to the same-memory-bank refresh command, when the full-memory-bank refresh command is received, the same-memory-bank refresh command is executed; and controlling the refresh window generation circuit to output a first refresh window signal with a first level to the memory banks which have completed the same-memory-bank refresh, and when the first refresh window signal is at the first level, stopping data refresh of the memory banks which have completed the same-memory-bank refresh. Therefore, repeated refresh of the same memory bank refresh and the full memory bank refresh can be avoided as much as possible, and the power consumption of the memory can be reduced.

Description

Technical Field

[0001] The present application relates to but is not limited to a refresh control circuit and a memory. Background Art

[0002] The memory is used to store data. Some memories can temporarily store data. In order to avoid data loss in these memories, the memory needs to be constantly refreshed. Data refresh here can be understood as the process of reading data from the memory to rewrite the same data.

[0003] In the prior art, a refresh control circuit is provided in the memory to control the memory to perform data refresh. Specifically, when the refresh control circuit receives a Same Bank Refresh (REFSB) command, data is refreshed for a specified memory bank in each memory group. When the refresh control circuit receives an All Bank Refresh (REFAB) command, data is refreshed for all memory banks in each memory group. During the Same Bank Refresh process, if an All Bank Refresh command is received, data is refreshed for all memory banks in each memory group.

[0004] However, the above solution may result in higher power consumption of the memory. Summary of the invention

[0005] An embodiment of the present application provides a refresh control circuit and a memory to reduce power consumption of the memory.

[0006] In a first aspect, an embodiment of the present application provides a refresh control circuit, including:

[0007] A refresh window control circuit and a refresh window generation circuit;

[0008] The output end of the refresh window control circuit is connected to the input end of the refresh window generation circuit, and the refresh window control circuit is used to receive a same-bank refresh command and a full-bank refresh command, so that when the full-bank refresh command is received during the same-bank refresh process corresponding to the same-bank refresh command, the refresh window generation circuit is controlled to output a first refresh window signal with a first level to the bank that has completed the same-bank refresh, and when the first refresh window signal is at the first level, the bank that has completed the same-bank refresh stops refreshing data.

[0009] In one embodiment, the refresh window generation circuit includes: a refresh window generation subcircuit and a refresh window output circuit;

[0010] The refresh window generation subcircuit is used to receive a refresh command to generate a second refresh window signal according to the refresh command, wherein the refresh command is the same-bank refresh command or the full-bank refresh command;

[0011] The two input ends of the refresh window output circuit are respectively connected to the output end of the refresh window control circuit and the output end of the refresh window generation subcircuit, and are used to receive the refresh window control signal output by the refresh window control circuit and the second refresh window signal output by the refresh window generation subcircuit, so as to output the first refresh window signal with the first level to the storage body that has completed the same storage body refresh under the control of the refresh window control signal, and output the first refresh window signal with the second level to the storage body that has not completed the same storage body refresh; when the first refresh window signal is at the second level, the storage body that has not completed the same storage body refresh performs data refresh.

[0012] In one embodiment, when the refresh window control signal is high level and effective, the refresh window output circuit includes a first inverter circuit and a first AND logic circuit;

[0013] The input end of the first inverting circuit is connected to the output end of the refresh window control circuit, and is used to receive the refresh window control signal output by the refresh window control circuit to generate an inverted signal of the refresh window control signal;

[0014] The two input terminals of the first AND logic circuit are respectively connected to the output terminal of the first inverting circuit and the output terminal of the refresh window generating sub-circuit, and are used to receive the inverted signal of the refresh window control signal output by the first inverting circuit, and the second refresh window signal output by the refresh window generating sub-circuit, so as to generate the first refresh window signal through an AND logic operation.

[0015] In one embodiment, the refresh window control circuit includes: a same-bank refresh window generation circuit and a window control signal output circuit;

[0016] The same-bank refresh window generation circuit is used to receive the same-bank refresh command to generate a same-bank refresh window signal according to the same-bank refresh command, and when the same-bank refresh window signal is at a second level, the memory bank corresponding to the same-bank refresh window signal performs a same-bank refresh;

[0017] The window control signal output circuit is used to receive the same-bank refresh window signal and the full-bank refresh command output by the same-bank refresh window generation circuit, so as to output the refresh window control signal having the second level when the full-bank refresh command is received while the same-bank refresh window signal is at the second level.

[0018] In one embodiment, the window control signal output circuit includes: a repeated refresh determination circuit and a window control signal output sub-circuit;

[0019] The repeat refresh judgment circuit is used to receive the same-bank refresh window signal and the full-bank refresh command, so as to output a repeat refresh indication signal having the second level when both the same-bank refresh window signal and the full-bank refresh command are at the second level;

[0020] The input end of the window control signal output subcircuit is connected to the output end of the repeated refresh judgment circuit, and is used to receive the repeated refresh indication signal output by the repeated refresh judgment circuit, so as to output a refresh window control signal with the second level when the repeated refresh indication signal is at the second level.

[0021] In one embodiment, the window control signal output subcircuit includes: a first latch; the window control signal output circuit also includes a window control reset signal generating circuit;

[0022] The window control reset signal generating circuit is used to receive the second refresh window signal and the row activation pulse signal output by the refresh window generating sub-circuit, and output the window control reset signal when the number of pulses in the row activation pulse signal is greater than or equal to the number of rows of the memory bank that have completed the same memory bank refresh;

[0023] The set end and the reset end of the first latch are respectively connected to the output end of the repeated refresh judgment circuit and the output end of the window control reset signal generating circuit, and are used to output a refresh window control signal with the second level when the repeated refresh indication signal is at the second level, or to output a refresh window control signal with the first level when the window control reset signal is at the second level.

[0024] In one embodiment, the window control reset signal generating circuit includes: a first pulse signal generating circuit and a counting circuit;

[0025] The first pulse signal generating circuit is used to receive the second refresh window signal output by the refresh window generating subcircuit, the row activation pulse signal and the refresh window control signal output by the window control signal output circuit, so as to output a first pulse signal corresponding to the row activation pulse signal when the refresh window control signal is at the second level;

[0026] The input end of the counting circuit is connected to the output end of the first pulse signal generating circuit, and is used to receive the first pulse signal to count the number of pulses in the first pulse signal, and when the count reaches a target value, output the window control reset signal with the second level, and the target value is the number of rows of the storage body that have completed the same storage body refresh.

[0027] In one embodiment, the first pulse signal generating circuit comprises: a second pulse signal generating circuit and a first pulse signal generating sub-circuit;

[0028] The second pulse signal generating circuit is used for receiving the second refresh window signal and the row activation pulse signal to generate a second pulse signal;

[0029] The multiple input terminals of the first pulse signal generating subcircuit are respectively connected to the output terminal of the second pulse signal generating circuit and the output terminal of the window control signal output circuit, and are used to receive the second pulse signal and the refresh window control signal to generate the first pulse signal.

[0030] In one embodiment, the second pulse signal generating circuit comprises: a plurality of second AND logic circuits and OR logic circuits respectively corresponding to the memory banks;

[0031] One input end of each of the second AND logic circuits is connected to the output end of the refresh window generation subcircuit corresponding to the memory bank, and is used to receive the second refresh window signal output by the corresponding refresh window generation subcircuit, and the other input end receives the row activation pulse signal, so as to generate a row refresh signal corresponding to the memory bank through an AND logic operation;

[0032] Multiple input terminals of the OR logic circuit are connected to the output terminals of the second AND logic circuits of the storage bodies in the storage group, and are used to receive the row refresh signals of the storage bodies to generate the second pulse signal through an OR logic operation.

[0033] In one embodiment, the refresh window control circuit further includes: a same-bank refresh reset signal generating circuit, the same-bank refresh window generating circuit is a second latch, a set end of the second latch is used to receive the same-bank refresh command, and a reset end of the second latch is connected to an output end of the same-bank refresh reset signal generating circuit;

[0034] The multiple input ends of the same-storage body refresh reset signal generating circuit are respectively connected to the output end of the second latch of each storage body in the same storage group and the output end of the window control reset signal generating circuit, and are used to receive the window control reset signal output by the window control reset signal generating circuit and the same-storage body refresh window signal of each storage body in the same storage group, so as to generate a second-level same-storage body refresh reset signal when each of the same-storage body refresh window signals is at the second level and the window control reset signal is at the first level.

[0035] In one embodiment, the same bank refresh reset signal generating circuit comprises: a third AND logic circuit, a second inverting circuit and a fourth AND logic circuit;

[0036] The plurality of input terminals of the third AND logic circuit are respectively connected to the output terminals of the second latches of the respective memory banks in the same memory group, and are used to receive the same-memory bank refresh window signals of the respective memory banks, so as to generate the same-memory bank cycle end signal through AND logic operation;

[0037] The input end of the second inverting circuit is connected to the output end of the window control reset signal generating circuit, and is used to receive the window control reset signal to generate an inverted signal of the window control reset signal;

[0038] The fourth AND logic circuit is connected to the third AND logic circuit and the second inversion circuit, and is used to receive the same-bank cycle end signal and the inversion signal to generate the same-bank refresh reset signal through an AND logic operation.

[0039] In one embodiment, the refresh control circuit further includes: a refresh command generation circuit and a delay circuit;

[0040] The multiple output ends of the refresh command generation circuit are respectively connected to the input end of the refresh window control circuit and the input end of the delay circuit, and the refresh command generation circuit is used to receive an external command address signal to generate the same-bank refresh command and the full-bank refresh command, and output them to the refresh window control circuit and the delay circuit;

[0041] The output end of the delay circuit is connected to the input end of the refresh window generating circuit, and the delay circuit is used to match the time delay introduced by the refresh window control circuit.

[0042] In one embodiment, the refresh control circuit further includes: a row address generation circuit;

[0043] The input end of the row address generation circuit is connected to the output end of the refresh window control circuit, and is used to receive a refresh window control signal output by the refresh window control circuit, so as to output a row address to be refreshed when the refresh window control signal is at a first level.

[0044] In one embodiment, the refresh control circuit further includes: an activation circuit;

[0045] The input end of the activation circuit is connected to the output end of the refresh window generation circuit, and is used to receive the first refresh window signal output by the refresh window generation circuit to generate a row activation pulse signal according to the first refresh window signal, and the row activation pulse signal is used to activate the row in the storage body to refresh the data.

[0046] In a second aspect, an embodiment of the present application provides a memory, comprising the refresh control circuit described in the first aspect.

[0047] The embodiment of the present application provides a refresh control circuit and a memory, including: a refresh window control circuit and a refresh window generation circuit. The output end of the refresh window control circuit is connected to the input end of the refresh window generation circuit, and the refresh window control circuit is used to receive a same-storage-bank refresh command and a full-storage-bank refresh command, so that when a full-storage-bank refresh command is received during a same-storage-bank refresh process corresponding to the same-storage-bank refresh command, the refresh window generation circuit is controlled to output a first refresh window signal having a first level to a storage bank that has completed the same-storage-bank refresh, and when the first refresh window signal is at the first level, the storage bank that has completed the same-storage-bank refresh stops data refresh. In this way, repeated refreshes of the same-storage-bank refresh and the full-storage-bank refresh can be avoided as much as possible, and the power consumption of the memory can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0049] Figure 1 This is a refresh timing diagram of a REFSB command provided in an embodiment of the present application;

[0050] Figure 2 It is a refresh timing diagram of a REFAB command provided in an embodiment of the present application;

[0051] Figure 3 is a structural schematic diagram of a refresh control circuit provided in an embodiment of the present application;

[0052] Figure 4 It is a structural schematic diagram of a refresh window generation circuit provided in an embodiment of the present application;

[0053] Figure 5 is a structural schematic diagram of another refresh control circuit provided in an embodiment of the present application;

[0054] Figure 6 is a structural schematic diagram of a window control signal output circuit provided in an embodiment of the present application;

[0055] Figure 7 It is a structural schematic diagram of a memory bank refresh reset signal generating circuit provided by an embodiment of the present application;

[0056] Figure 8 This is a timing diagram of stopping data refresh provided in an embodiment of the present application.

[0057] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0058] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0059] The embodiments of the present application are applicable to a memory, where the memory is any semiconductor device that can store data, for example, DRAM (Dynamic Random Access Memory), including but not limited to SDRAM (Synchronous DRAM), SDRAM including but not limited to DDR (Double Rate SDRAM) 5.

[0060] The refresh commands of the above memory may include two types: a REFSB command and a REFAB command.

[0061] Figure 1 This is a refresh timing diagram of a REFSB command provided in an embodiment of the present application. Figure 2 1 is a refresh timing diagram of a REFAB command provided in an embodiment of the present application. The memory includes multiple BGs, Figure 1 and Figure 2 They are respectively the REFSB refresh timing of a BG (Bank Group) and the REFAB refresh timing of a BG. The REFSB refresh timings of different BGs are the same, and the REFSB refresh timings of different BGs are also the same.

[0062] Reference Figure 1 As shown, the same BG includes 4 BAs (Banks, storage bodies) from BA0 to BA3, wherein the refresh window signal of the storage body BA0 has a high level to refresh the storage body BA0 once, and the row activation pulse signal of the storage body BA0 has 2 pulses to activate the 2 rows to be refreshed in the storage body BA0.

[0063] The refresh window signals of the memory cells BA1, BA2 and BA3 are all at low level, and the row activation pulse signals of the memory cells BA1, BA2 and BA3 have no pulses. Therefore, the memory cells BA1, BA2 and BA3 do not refresh data.

[0064] In summary, Figure 1 The REFSB command corresponding to the refresh timing shown is used to refresh the two rows of BA0, that is, the designated BA corresponding to the REFSB command is BA0.

[0065] Reference Figure 2 As shown, the refresh window signals of BA0 to BA3 in the same BG all have a high level to refresh the storage bodies BA0 to BA3 once, and the row activation pulse signals of the storage bodies BA0 to BA3 all have 5 pulses to activate the 5 rows to be refreshed in the storage bodies BA0 to BA3.

[0066] In summary, Figure 2 The REFAB command corresponding to the refresh timing shown is used to refresh two rows of BA0 to BA3 at the same time.

[0067] It can be seen that when the REFAB command is received, whether or not the same memory bank is being refreshed, it will be refreshed according to Figure 2 The refresh timing shown in FIG. 1 refreshes all rows of each BA in each BG in the memory. Under this mechanism, when the memory receives the REFAB command, if it is refreshing the same memory bank for the REFSB command, the memory will still refresh all rows of all BAs (Banks) of all BGs (Bank Groups) of the memory according to REFAB. In this way, the rows refreshed by the REFSB command will be repeatedly refreshed by the REFAB command, resulting in higher power consumption of the memory.

[0068] In order to solve the above technical problems, the embodiment of the present application can be provided with a refresh control circuit to determine whether the above scenario of receiving a full memory bank refresh command during the same memory bank refresh process corresponding to the same memory refresh command occurs. When it is determined that this scenario occurs, the refresh window generation circuit is controlled to generate a first refresh window signal of a first level to control the memory bank to stop refreshing data. Therefore, the power consumption of the memory can be reduced.

[0069] Figure 3 is a schematic diagram of a refresh control circuit provided in an embodiment of the present application, referring to Figure 3 As shown, the refresh control circuit includes: a refresh window control circuit and a refresh window generation circuit.

[0070] Reference Figure 3 As shown, the output end of the refresh window control circuit is connected to the input end of the refresh window generation circuit. The refresh window control circuit is used to receive a same-bank refresh command and a full-bank refresh command, so that when a full-bank refresh command is received during a same-bank refresh process corresponding to the same-bank refresh command, the refresh window generation circuit is controlled to output a first refresh window signal having a first level to the bank that has completed the same-bank refresh. When the first refresh window signal is at the first level, the bank that has completed the same-bank refresh stops refreshing data.

[0071] Specifically, the refresh window control circuit can make a judgment based on the same-bank refresh command and the full-bank refresh command to determine whether a scenario of receiving a full-bank refresh command occurs during the same-bank refresh process corresponding to the same-bank refresh command. If it occurs, the refresh window control circuit can output a refresh window control signal of a second level, and the refresh window generation circuit outputs a first refresh window signal of a first level when receiving the refresh window control signal of the second level. If it does not occur, the refresh window control circuit can output a refresh window control signal of a first level, and the refresh window generation circuit outputs a first refresh window signal of a second level when receiving the refresh window control signal of the first level.

[0072] In the embodiment of the present application, the first level is an invalid level, and the second level is a valid level. The first level and the second level can be flexibly set. The embodiment of the present application is described by taking the first level as a low level and the second level as a high level as an example.

[0073] In some embodiments, reference Figure 4 As shown, the above refresh window generation circuit includes: a refresh window generation sub-circuit and a refresh window output circuit.

[0074] The refresh window generation subcircuit is used to receive a refresh command to generate a second refresh window signal according to the refresh command, wherein the refresh command is a same-bank refresh command or a full-bank refresh command. Specifically, the refresh window generation subcircuit outputs a second refresh window signal with a second level each time a refresh command is received.

[0075] The two input ends of the refresh window output circuit are respectively connected to the output end of the refresh window control circuit and the output end of the refresh window generation subcircuit, and are used to receive the refresh window control signal output by the refresh window control circuit and the second refresh window signal output by the refresh window generation subcircuit, so as to output a first refresh window signal with a first level to the storage body that has completed the same storage body refresh under the control of the refresh window control signal, and output a first refresh window signal with a second level to the storage body that has not completed the same storage body refresh. When the first refresh window signal is at the second level, the storage body that has not completed the same storage body refresh performs data refresh.

[0076] Specifically, when the refresh window control signal is at the second level, the refresh window output circuit uses the second refresh window signal at the second level as the first refresh window signal with the second level, and uses the second refresh window signal at the first level as the first refresh window signal with the first level. When the refresh window control signal is at the second level, the refresh window output circuit outputs the first refresh window signal at the first level.

[0077] In some embodiments, when the refresh window control signal is high level effective, that is, the second level of the refresh window control signal is high level. The refresh window output circuit includes a first inverter circuit and a first AND logic circuit. The first inverter circuit here can be Figure 4 Inverter INV1, the first AND logic circuit can be Figure 4 Of course, the first inverting circuit may also be obtained by connecting an odd number of inverters in series, and the first AND logic circuit may also be any circuit that implements an AND logic operation. The embodiment of the present application does not limit the specific forms of the first inverting circuit and the first AND logic circuit.

[0078] The input end of the first inverting circuit is connected to the output end of the refresh window control circuit, and is used to receive a refresh window control signal output by the refresh window control circuit to generate an inverted signal of the refresh window control signal.

[0079] The two input terminals of the first AND logic circuit are respectively connected to the output terminal of the first inverting circuit and the output terminal of the refresh window generating subcircuit, and are used to receive the inverted signal of the refresh window control signal output by the first inverting circuit, and the second refresh window signal output by the refresh window generating subcircuit, so as to generate the first refresh window signal through the AND logic operation.

[0080] It should be noted that when the refresh window control signal is at a low level and effective, the first level of the refresh window control signal is at a high level. Figure 4 The circuit shown can be flexibly adjusted, and the embodiments of the present application will not be described in detail here.

[0081] Reference Figure 4 As shown, the refresh window generation subcircuit can be a latch, which is recorded as the third latch SR3. The effective levels of the refresh command, the refresh end signal and the second refresh window signal, that is, the second level, are all high. Initially, the second refresh window signal output by the output terminal Q of the third latch SR3 is low, and the refresh command and the refresh end signal received by the set terminal S and the reset terminal R of the third latch SR3 are both low, so that the third latch SR3 always keeps outputting the second refresh window signal of low level before receiving the refresh command of high level.

[0082] When a refresh command arrives, the refresh command received by the set terminal S of the third latch SR3 has a high-level pulse to set the second refresh window signal output by the output terminal Q to a high level. When the refresh end signal is high, representing that this pulse of the refresh command refreshes to the target number of rows, the third latch SR3 outputs a low-level second refresh window signal, thereby completing this refresh. In other words, a pulse of the refresh command can be used to refresh the target number of rows, which is a preset number, and different types of refresh commands can correspond to different target numbers of rows. For example, for the REFSB command, the target number of rows can be 2, and for the REFAB command, the target number of rows can be 5.

[0083] In some embodiments, reference Figure 5 As shown, the refresh window control circuit includes: a storage body refresh window generation circuit and a window control signal output circuit.

[0084] The same-bank refresh window generation circuit is used to receive a same-bank refresh command to generate a same-bank refresh window signal according to the same-bank refresh command. When the same-bank refresh window signal is at a second level, the memory bank corresponding to the same-bank refresh window signal performs a same-bank refresh. Specifically, when the same-bank refresh command has a second level, the same-bank refresh window generation circuit generates a same-bank refresh window signal with a second level for the same-bank refresh command to perform a data refresh. For example, the second level is a high level. When a high-level pulse appears in the same-bank refresh command, a same-bank refresh window signal for the high-level pulse is generated to perform a data refresh. Each data refresh can perform a refresh of one or more rows, for example, a refresh of 2 rows.

[0085] The window control signal output circuit is used to receive the same-bank refresh window signal and the full-bank refresh command output by the same-bank refresh window generation circuit, so as to output a refresh window control signal with a second level when the full-bank refresh command is received during the process in which the same-bank refresh window signal is at a second level.

[0086] It is understandable that the second level of the same bank refresh window signal indicates that the same bank refresh is in progress, and the receipt of the full bank refresh command indicates that the full bank refresh command is at the second level. At this time, the second level refresh window control signal can be output to stop data refresh.

[0087] Specifically, refer to Figure 5 As shown, the above-mentioned window control signal output circuit includes: a repeated refresh judgment circuit and a window control signal output sub-circuit.

[0088] The repeat refresh judgment circuit is used to receive the same-bank refresh window signal and the full-bank refresh command, and output a repeat refresh indication signal with a second level when the same-bank refresh window signal and the full-bank refresh command are both at the second level. When the second level is a high level, the repeat refresh judgment circuit is an AND logic circuit, for example, Figure 6 AND gate AD2 is shown.

[0089] The input end of the window control signal output subcircuit is connected to the output end of the repeat refresh judgment circuit, and is used to receive the repeat refresh indication signal output by the repeat refresh judgment circuit, so as to output a refresh window control signal with a second level when the repeat refresh indication signal is at a second level, and output a refresh window control signal with a first level otherwise.

[0090] Reference Figure 5 As shown, the above-mentioned window control signal output subcircuit includes: a first latch, denoted as SR1. The window control signal output circuit also includes a window control reset signal generating circuit.

[0091] The window control reset signal generating circuit is used to receive the second refresh window signal and the row activation pulse signal output by the refresh window generating subcircuit, so as to output the window control reset signal when the number of pulses in the row activation pulse signal is greater than or equal to the number of rows of the storage body that have completed the refresh of the same storage body. Among them, a refresh is performed every time a pulse of the second refresh window signal appears. Every time a pulse of the row activation pulse signal appears, it is used to refresh a row. One refresh can correspond to one or more rows of refreshes, and the number of rows corresponding to one refresh is the number of pulses of the row activation pulse signal during the process of one pulse of the second refresh window signal. However, the present application needs to count the number of pulses in the above-mentioned row activation pulse signal during the process of the refresh window control signal being at the second level.

[0092] Reference Figure 6 As shown, the set terminal S and the reset terminal R of the first latch SR1 are respectively connected to the output terminal of the repeated refresh judgment circuit and the output terminal of the window control reset signal generating circuit, and are used to output a refresh window control signal with a second level when the repeated refresh indication signal is at a second level, or, when the window control reset signal is at the second level, output a refresh window control signal with a first level through the output terminal Q.

[0093] Among them, the second level is a high level, and the first level is a low level. Initially, the repeat refresh indication signal and the window control reset signal are both low levels, and the output end of the first latch SR1 is low level. When a full storage body refresh command is received during the same storage body refresh process, a high level pulse appears in the repeat refresh indication signal, and the refresh window control signal output from the output end Q of the first latch SR1 is set to a high level. When the window control reset signal is a high level, it means that the stop refresh has ended and it is necessary to continue refreshing. Therefore, when the repeat refresh indication signal is a low level and the window control reset signal is a high level, the first latch SR1 resets the output refresh window control signal to a low level to continue data refresh.

[0094] Reference Figure 6 As shown, the above-mentioned window control reset signal generating circuit includes: a first pulse signal generating circuit and a counting circuit.

[0095] The first pulse signal generating circuit is used to receive the second refresh window signal output by the refresh window generating subcircuit, the row activation pulse signal and the refresh window control signal output by the window control signal output circuit, so as to output a first pulse signal corresponding to the row activation pulse signal when the refresh window control signal is at a second level.

[0096] The input end of the counting circuit is connected to the output end of the first pulse signal generating circuit, and is used to receive the first pulse signal to count the number of pulses in the first pulse signal, and when the count reaches a target value, output a window control reset signal with a second level, and the target value is the number of rows of the storage body that have completed the same storage body refresh.

[0097] The target value is the preset number of refresh rows for each refresh, and the counting circuit can be Figure 6 The counter shown is counter.

[0098] Reference Figure 6 As shown, the first pulse signal generating circuit includes: a second pulse signal generating circuit and a first pulse signal generating sub-circuit.

[0099] The second pulse signal generating circuit is used to receive the second refresh window signal and the row activation pulse signal to generate a second pulse signal. Specifically, when the second refresh window signal is at the second level and the row activation pulse signal is at the second level, the second pulse signal at the second level is output. Otherwise, the second pulse signal at the first level is output.

[0100] The multiple input terminals of the first pulse signal generating subcircuit are respectively connected to the output terminal of the second pulse signal generating circuit and the output terminal of the window control signal output circuit, and are used to receive the second pulse signal and the refresh window control signal to generate the first pulse signal. Specifically, when the second pulse signal is at the second level and the refresh window control signal is at the second level, the first pulse signal at the second level is output; otherwise, the first pulse signal at the first level is output. Figure 6 As shown, the first pulse signal generating sub-circuit may be an AND gate AD7.

[0101] When the second level is high, the second pulse signal generating circuit can be an AND logic circuit to perform an AND logic operation on the second refresh window signal and the row activation pulse signal of the storage body to obtain the second pulse signal. In order to allow multiple storage bodies in the same storage group to reuse the second pulse signal generating circuit, the second pulse signal generating circuit includes: multiple second AND logic circuits corresponding to the storage bodies, and an OR logic circuit.

[0102] Each storage body in the storage group corresponds to a second AND logic circuit, one input end of each second AND logic circuit is connected to the output end of the refresh window generation subcircuit of the corresponding storage body, and is used to receive the second refresh window signal output by the corresponding refresh window generation subcircuit, and the other input end receives the row activation pulse signal to generate a row refresh signal of the corresponding storage body through an AND logic operation.

[0103] Reference Figure 6 As shown, the second AND logic circuits corresponding to each storage body BA0 to BA3 in the storage group are AND gates AD3, AD4, AD5 and AD6. The two input ends of the AND gate AD3 are used to receive the second refresh window signal of the storage body BA0 and the row activation pulse signal of BA0 respectively. The two input ends of the AND gate AD4 are used to receive the second refresh window signal of the storage body BA1 and the row activation pulse signal of BA1 respectively. The two input ends of the AND gate AD5 are used to receive the second refresh window signal of the storage body BA2 and the row activation pulse signal of BA2 respectively. The two input ends of the AND gate AD6 are used to receive the second refresh window signal of the storage body BA3 and the row activation pulse signal of BA3 respectively.

[0104] Multiple input terminals of the OR logic circuit are connected to the output terminals of the second AND logic circuit of each memory bank in the memory group, and are used to receive the row refresh signal of each memory bank to generate the second pulse signal through the OR logic operation.

[0105] OR logic circuits can include Figure 6 The two NOR gates ORN1 and ORN2 and the NAND gate NAN1 in the circuit are connected. The two input ends of the NOR gate ORN1 are connected to the output ends of the AND gates AD3 and AD4 respectively, and the two input ends of the NOR gate ORN2 are connected to the output ends of the AND gates AD5 and AD6 respectively. The two input ends of the NAND gate NAN1 are connected to the output ends of the two NOR gates ORN1 and ORN2 respectively. Therefore, the NOR gate NAN1 outputs the second pulse signal.

[0106] The embodiment of the present application can generate the second pulse signal through simple logical operations, which can reduce circuit complexity.

[0107] Reference Figure 5 As shown, the same bank refresh window generation circuit is a second latch. The refresh window control circuit also includes a same bank refresh reset signal generation circuit. The set end S of the second latch is used to receive the same bank refresh command, and the reset end R of the second latch is connected to the output end of the same bank refresh reset signal generation circuit.

[0108] Multiple input terminals of the same-bank refresh reset signal generating circuit are respectively connected to the output terminal of the second latch of each bank in the same bank group and the output terminal of the window control reset signal generating circuit, and are used to receive the window control reset signal output by the window control reset signal generating circuit and the same-bank refresh window signal of each bank in the same bank group, so as to generate a second-level same-bank refresh reset signal when each same-bank refresh window signal is at the second level and the window control reset signal is at the first level.

[0109] When the same bank refresh window signals of each BA in the same BG are all at the second level, it indicates that the refresh of the same bank completes one cycle.

[0110] Take the first level as a low level and the second level as a high level as an example. Initially, the same storage bank refresh window signal outputted from the output terminal Q of the second latch is all at a low level, and the same storage bank refresh command and the same storage bank refresh reset command are both at a low level. In this way, the second latch always keeps outputting the same storage bank refresh window signal at a low level. When a high level pulse appears in the same storage bank refresh command, the same storage bank refresh window signal is set to a high level. Thereafter, when a high level pulse appears in the same storage bank refresh reset signal, the same storage bank refresh window signal is set to a low level.

[0111] It can be understood that when all the same-bank refresh window signals are at a high level and the window control reset signal is at a low level, a high-level same-bank refresh reset signal is generated to set the same-bank refresh window signal to a low level. When at least one same-bank refresh window signal is at a low level and / or the window control reset signal is at a low level, a low-level same-bank refresh reset signal is generated to continue to refresh data according to the same-bank refresh command signal.

[0112] In some implementations, the same bank refresh reset signal generating circuit may include: a third AND logic circuit, a second inversion circuit, and a fourth AND logic circuit.

[0113] The multiple input terminals of the third AND logic circuit are respectively connected to the output terminals of the second latches of each memory bank in the same memory group, and are used to receive the same memory bank refresh window signals of each memory bank, so as to generate the same memory bank cycle end signal through the AND logic operation. The specific structure of the third AND logic circuit can be flexibly set according to the number of memory banks in the same memory group. For example, when the same memory group includes four memory banks BA0 to BA3, refer to Figure 7 As shown, the third AND logic circuit may include a NAND gate NAN2, a NAND gate NAN3, and a NOR gate ORN3. The two input ends of the NAND gate NAN2 are used to receive the same-bank refresh window signals of the memory banks BA0 and BA1, and the two input ends of the NAND gate NAN3 are used to receive the same-bank refresh window signals of the memory banks BA2 and BA3. The input end of the NOR gate ORN3 is connected to the output ends of the NAND gates NAN2 and NAN3. The NOR gate ORN3 is used to output the same-bank cycle end signal.

[0114] The input end of the second inverting circuit is connected to the output end of the window control reset signal generating circuit, and is used to receive the window control reset signal to generate an inverted signal of the window control reset signal. The second inverting circuit can be Figure 7 Inverter INV2 is shown.

[0115] The fourth AND logic circuit is connected to the third AND logic circuit and the second inversion circuit, and is used to receive the same storage body cycle end signal and the inversion signal to generate the same storage body refresh reset signal through an AND logic operation. The fourth AND logic circuit can be Figure 7 AND gate AD8 is shown.

[0116] Reference Figure 7 As shown, when the window control reset signal is low level and all the memory banks in the same memory group are performing the same memory bank refresh window signal, the same memory bank refresh reset signal is high level. Otherwise, the same memory bank refresh reset signal is high level or low level.

[0117] Reference Figure 5As shown, the refresh control circuit also includes: a refresh command generation circuit and a delay circuit. Multiple output ends of the refresh command generation circuit are respectively connected to the input end of the refresh window control circuit and the input end of the delay circuit. The refresh command generation circuit is used to receive an external command address signal to generate a same-storage bank refresh command and a full-storage bank refresh command, and output them to the refresh window control circuit and the delay circuit.

[0118] The output end of the delay circuit is connected to the input end of the refresh window generation circuit, and the delay circuit is used to match the time delay introduced by the refresh window control circuit.

[0119] It can be understood that since the refresh window control circuit processes the output signal of the refresh command generating circuit and needs a certain time delay to output the refresh window control signal, it is necessary to use a delay circuit to make the time when the delayed refresh command reaches the refresh window generating circuit and the time when the refresh window control signal reaches the refresh window generating circuit as close as possible to each other, which helps to improve the generation accuracy of the first refresh window signal.

[0120] In some embodiments, reference Figure 5 As shown, the refresh control circuit also includes: a row address generation circuit. The input end of the row address generation circuit is connected to the output end of the refresh window control circuit, and is used to receive a refresh window control signal output by the refresh window control circuit, so as to output the row address to be refreshed when the refresh window control signal is at a first level. When the refresh window control signal is at a second level, the output of the row address to be refreshed is stopped. In this way, the power consumption of the memory can be further reduced.

[0121] In some embodiments, reference Figure 5 As shown, the refresh control circuit also includes: an activation circuit. The input end of the activation circuit is connected to the output end of the refresh window generation circuit, and is used to receive the first refresh window signal output by the refresh window generation circuit to generate a row activation pulse signal according to the first refresh window signal. The row activation pulse signal is used to activate the row in the storage body to refresh the data. When the first refresh window signal is at the second level, the activation circuit outputs the row activation pulse signal; when the first refresh window signal is at the first level, the activation circuit does not output the row activation pulse signal. In other words, the embodiment of the present application controls the output of the first refresh window signal through the refresh window control signal, and the first refresh window signal is used to control the output of the row activation pulse signal. Therefore, when the refresh window control signal is at the first level, the row activation pulse signal is not output, and the data refresh is stopped.

[0122] It should be noted that the embodiments of the present application provide Figures 3 to 7 The circuits shown are all circuits corresponding to one memory bank. Figure 6 a second pulse signal generating circuit in Figure 7 The third AND logic circuit in the same storage group is a common circuit for each storage bank. In addition, Figures 3 to 7 The remaining circuits in are circuits used separately by each memory bank.

[0123] Figure 8 1 is a timing diagram of stopping data refresh provided by an embodiment of the present application. Figure 8 As shown, the memory body BA0 has completed a same-memory body refresh, and this same-memory body refresh has achieved two-row refresh. Therefore, when the memory body BA0 receives the full-memory body refresh command, it stops data refresh to avoid repeated refresh of the two rows that have been refreshed with the same memory body. And after stopping the data refresh, BA0 continues to refresh the three rows that have not been refreshed with the same memory body. The refresh window signals of the memory bodies BA1, BA2 and BA3 that have not completed the same-memory body refresh still need to perform 5-row data refresh. In other words, the memory bodies BA1, BA2 and BA3 will not stop data refresh.

[0124] An embodiment of the present application also provides a memory, comprising the aforementioned refresh control circuit.

[0125] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0126] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A refresh control circuit, characterized in that: include: A refresh window control circuit and a refresh window generation circuit; The output end of the refresh window control circuit is connected to the input end of the refresh window generation circuit, and the refresh window control circuit is used to receive a same-bank refresh command and a full-bank refresh command, so that when the full-bank refresh command is received during the same-bank refresh process corresponding to the same-bank refresh command, the refresh window generation circuit is controlled to output a first refresh window signal with a first level to the bank that has completed the same-bank refresh, and when the first refresh window signal is at the first level, the bank that has completed the same-bank refresh stops refreshing data.

2. The refresh control circuit according to claim 1, characterized in that: The refresh window generation circuit comprises: a refresh window generation sub-circuit and a refresh window output circuit; The refresh window generation subcircuit is used to receive a refresh command to generate a second refresh window signal according to the refresh command, wherein the refresh command is the same-bank refresh command or the full-bank refresh command; The two input ends of the refresh window output circuit are respectively connected to the output end of the refresh window control circuit and the output end of the refresh window generation subcircuit, and are used to receive the refresh window control signal output by the refresh window control circuit and the second refresh window signal output by the refresh window generation subcircuit, so as to output the first refresh window signal with the first level to the storage body that has completed the same storage body refresh under the control of the refresh window control signal, and output the first refresh window signal with the second level to the storage body that has not completed the same storage body refresh; when the first refresh window signal is at the second level, the storage body that has not completed the same storage body refresh performs data refresh.

3. The refresh control circuit according to claim 2, characterized in that: When the refresh window control signal is high level and effective, the refresh window output circuit includes a first inverting circuit and a first AND logic circuit; The input end of the first inverting circuit is connected to the output end of the refresh window control circuit, and is used to receive the refresh window control signal output by the refresh window control circuit to generate an inverted signal of the refresh window control signal; The two input terminals of the first AND logic circuit are respectively connected to the output terminal of the first inverting circuit and the output terminal of the refresh window generating sub-circuit, and are used to receive the inverted signal of the refresh window control signal output by the first inverting circuit, and the second refresh window signal output by the refresh window generating sub-circuit, so as to generate the first refresh window signal through an AND logic operation.

4. The refresh control circuit according to claim 3, characterized in that: The refresh window control circuit comprises: a same memory bank refresh window generation circuit and a window control signal output circuit; The same-bank refresh window generation circuit is used to receive the same-bank refresh command to generate a same-bank refresh window signal according to the same-bank refresh command, and when the same-bank refresh window signal is at a second level, the memory bank corresponding to the same-bank refresh window signal performs a same-bank refresh; The window control signal output circuit is used to receive the same-bank refresh window signal and the full-bank refresh command output by the same-bank refresh window generation circuit, so as to output the refresh window control signal having the second level when the full-bank refresh command is received while the same-bank refresh window signal is at the second level.

5. The refresh control circuit according to claim 4, characterized in that: The window control signal output circuit comprises: a repeated refresh judgment circuit and a window control signal output sub-circuit; The repeat refresh judgment circuit is used to receive the same-bank refresh window signal and the full-bank refresh command, so as to output a repeat refresh indication signal having the second level when both the same-bank refresh window signal and the full-bank refresh command are at the second level; The input end of the window control signal output subcircuit is connected to the output end of the repeated refresh judgment circuit, and is used to receive the repeated refresh indication signal output by the repeated refresh judgment circuit, so as to output a refresh window control signal with the second level when the repeated refresh indication signal is at the second level.

6. The refresh control circuit according to claim 5, characterized in that: The window control signal output subcircuit includes: a first latch; the window control signal output circuit also includes a window control reset signal generating circuit; The window control reset signal generating circuit is used to receive the second refresh window signal and the row activation pulse signal output by the refresh window generating sub-circuit, and output the window control reset signal when the number of pulses in the row activation pulse signal is greater than or equal to the number of rows of the memory bank that have completed the same memory bank refresh; The set end and the reset end of the first latch are respectively connected to the output end of the repeated refresh judgment circuit and the output end of the window control reset signal generating circuit, and are used to output a refresh window control signal with the second level when the repeated refresh indication signal is at the second level, or to output a refresh window control signal with the first level when the window control reset signal is at the second level.

7. The refresh control circuit according to claim 6, characterized in that: The window control reset signal generating circuit comprises: a first pulse signal generating circuit and a counting circuit; The first pulse signal generating circuit is used to receive the second refresh window signal output by the refresh window generating subcircuit, the row activation pulse signal and the refresh window control signal output by the window control signal output circuit, so as to output a first pulse signal corresponding to the row activation pulse signal when the refresh window control signal is at the second level; The input end of the counting circuit is connected to the output end of the first pulse signal generating circuit, and is used to receive the first pulse signal to count the number of pulses in the first pulse signal, and when the count reaches a target value, output the window control reset signal with the second level, and the target value is the number of rows of the storage body that have completed the same storage body refresh.

8. The refresh control circuit according to claim 7, characterized in that: The first pulse signal generating circuit comprises: a second pulse signal generating circuit and a first pulse signal generating sub-circuit; The second pulse signal generating circuit is used for receiving the second refresh window signal and the row activation pulse signal to generate a second pulse signal; The multiple input terminals of the first pulse signal generating subcircuit are respectively connected to the output terminal of the second pulse signal generating circuit and the output terminal of the window control signal output circuit, and are used to receive the second pulse signal and the refresh window control signal to generate the first pulse signal.

9. The refresh control circuit according to claim 8, characterized in that: The second pulse signal generating circuit comprises: a plurality of second AND logic circuits and an OR logic circuit respectively corresponding to the storage bodies; One input end of each of the second AND logic circuits is connected to the output end of the refresh window generation subcircuit corresponding to the memory bank, and is used to receive the second refresh window signal output by the corresponding refresh window generation subcircuit, and the other input end receives the row activation pulse signal, so as to generate a row refresh signal corresponding to the memory bank through an AND logic operation; Multiple input terminals of the OR logic circuit are connected to the output terminals of the second AND logic circuits of the storage bodies in the storage group, and are used to receive the row refresh signals of the storage bodies to generate the second pulse signal through an OR logic operation.

10. The refresh control circuit according to any one of claims 6 to 9, characterized in that: The refresh window control circuit further includes: a same-bank refresh reset signal generating circuit, the same-bank refresh window generating circuit is a second latch, a set end of the second latch is used to receive the same-bank refresh command, and a reset end of the second latch is connected to an output end of the same-bank refresh reset signal generating circuit; The multiple input ends of the same-storage body refresh reset signal generating circuit are respectively connected to the output end of the second latch of each storage body in the same storage group and the output end of the window control reset signal generating circuit, and are used to receive the window control reset signal output by the window control reset signal generating circuit and the same-storage body refresh window signal of each storage body in the same storage group, so as to generate a second-level same-storage body refresh reset signal when each of the same-storage body refresh window signals is at the second level and the window control reset signal is at the first level.

11. The refresh control circuit according to claim 10, characterized in that: The same memory bank refresh reset signal generating circuit comprises: a third AND logic circuit, a second inverting circuit and a fourth AND logic circuit; The plurality of input terminals of the third AND logic circuit are respectively connected to the output terminals of the second latches of the respective memory banks in the same memory group, and are used to receive the same-memory bank refresh window signals of the respective memory banks, so as to generate the same-memory bank cycle end signal through AND logic operation; The input end of the second inverting circuit is connected to the output end of the window control reset signal generating circuit, and is used to receive the window control reset signal to generate an inverted signal of the window control reset signal; The fourth AND logic circuit is connected to the third AND logic circuit and the second inversion circuit, and is used to receive the same-bank cycle end signal and the inversion signal to generate the same-bank refresh reset signal through an AND logic operation.

12. The refresh control circuit according to any one of claims 1 to 9, characterized in that: The refresh control circuit also includes: a refresh command generation circuit and a delay circuit; The multiple output ends of the refresh command generation circuit are respectively connected to the input end of the refresh window control circuit and the input end of the delay circuit, and the refresh command generation circuit is used to receive an external command address signal to generate the same-bank refresh command and the full-bank refresh command, and output them to the refresh window control circuit and the delay circuit; The output end of the delay circuit is connected to the input end of the refresh window generating circuit, and the delay circuit is used to match the time delay introduced by the refresh window control circuit.

13. The refresh control circuit according to any one of claims 2 to 9, characterized in that: The refresh control circuit further includes: a row address generation circuit; The input end of the row address generation circuit is connected to the output end of the refresh window control circuit, and is used to receive a refresh window control signal output by the refresh window control circuit, so as to output a row address to be refreshed when the refresh window control signal is at a first level.

14. The refresh control circuit according to any one of claims 1 to 9, characterized in that: The refresh control circuit further includes: an activation circuit; The input end of the activation circuit is connected to the output end of the refresh window generation circuit, and is used to receive a first refresh window signal output by the refresh window generation circuit to generate a row activation pulse signal according to the first refresh window signal, and the row activation pulse signal is used to activate the row in the storage body to refresh the data.

15. A memory, characterized in that: The refresh control circuit comprises the refresh control circuit as claimed in any one of claims 1 to 14.

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