NAND FLASH controller architecture based on STT-MRAM, caching method and medium

Abstract

The invention relates to the technical field of integrated circuit memory design, and discloses an STT-MRAM-based NAND FLASH controller architecture, a caching method and a medium, the controller architecture comprises an NAND FLASH controller which is connected with a host interface and an NAND FLASH interface, the NAND FLASH controller comprises a dual-port STT-MRAM caching module, the dual-port STT-MRAM caching module is used for realizing data internal buffering and a buffering process, and the dual-port STT-MRAM caching module is used for realizing data internal buffering. When a host writes data into the NAND FLASH and reads data from the NAND FLASH, the data buffer is used as a data buffer and stores a mapping table and a metadata log; according to the caching method, the STT-MRAM cache is divided into an FTL mapping table storage area, a log area and a data cache area according to memory addresses under the architecture of the controller. According to the invention, the service life of the NAND FLASH can be prolonged, and the data recovery capability under the condition of accidental power failure is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit memory design, and in particular to a NANDFLASH controller architecture, a cache method and a medium based on STT-MRAM. Background Art

[0002] NAND FLASH memory has the advantages of large capacity, fast rewrite speed, reliable data storage capacity, etc., and is therefore widely used. The development of nLC (amorphous silicon technology) and 3D structure technology has greatly reduced the unit storage cost of NAND FLASH. However, along with the cost advantage comes the problem of shortened P / E cycle (i.e., there is a limit on the program / erase cycle), which has a great impact on the reliability of NAND FLASH. In particular, the erase-before-write feature of NAND FLASH will reduce the service life of NAND FLASH and affect the data recovery capability in the event of power failure. However, there is no effective solution to these problems in the prior art. Summary of the invention

[0003] To this end, the technical problem to be solved by the present invention is to overcome the deficiencies in the prior art and provide a NAND FLASH controller architecture, a caching method and a medium based on STT-MRAM, which can extend the service life of NAND FLASH and improve the data recovery capability in the event of an unexpected power outage.

[0004] In order to solve the above technical problems, the present invention provides a NAND FLASH controller architecture based on STT-MRAM, including:

[0005] It includes a NAND FLASH controller, a host interface, and a NAND FLASH interface, wherein the NAND FLASH controller is connected to the host interface and the NAND FLASH interface respectively;

[0006] The NAND FLASH controller includes a dual-port STT-MRAM cache module, which is used to implement internal data buffering and buffering process, and is used as a data buffer when the host writes data to the NAND FLASH and reads data from the NAND FLASH, and stores a mapping table and a metadata log.

[0007] Furthermore, the NAND FLASH controller also includes a command parsing module and a timing control module, and the command parsing module and the timing control module each include a state machine; the state machine in the command parsing module interprets the command from the host and transmits the control signal to the timing control module; the state machine in the timing control module generates all necessary control signals based on the received control signal so that the NAND FLASH performs repetitive tasks with strict timing requirements.

[0008] Furthermore, the NAND FLASH controller further comprises an address counting module, which generates an address control signal required for data buffering according to a state machine in the command parsing module, and determines the completion status of data operations.

[0009] Furthermore, the NAND FLASH controller also includes an ECC check code generation module and an ECC check code detection module. The ECC check code generation module generates an ECC check code during a page programming operation and stores the ECC check code in the OOB area of ​​the NAND FLASH. The ECC check code detection module uses the ECC check code in the NAND FLASH to detect errors in the data during a read operation performed by the host.

[0010] Furthermore, the dual-port STT-MRAM cache module is a dual-port RAM.

[0011] Furthermore, the pin configuration of the host interface includes:

[0012] CLK pin is input, the valid state is N / A, indicating the clock signal;

[0013] RES pin is an input, the effective state is high, indicating a reset signal;

[0014] BF_sel pin, input high, effective state is high, indicating dual-port STT-MRAM enable signal;

[0015] BF_ad[10:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM address signal;

[0016] BF_din[7:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM data signal;

[0017] BF_we pin is an input, and its effective state is high, indicating the dual-port STT-MRAM write signal;

[0018] RWA[15:0] pin is input, the valid state is N / A, indicating that the NAND FLASH writes the physical address signal;

[0019] BF_dou[7:0] pin is output, and its valid state is N / A, indicating that the dual-port STT-MRAM transmits data to the host;

[0020] PErr pin is an output, the effective state is high, indicating a page programming operation error signal;

[0021] EErr pin is an output, the effective state is high, indicating a block erase operation error signal;

[0022] RErr pin is an output, the effective state is high, indicating a page read operation error signal;

[0023] nfc_cmd[2:0] pin is input, the valid state is N / A, indicating the command code signal;

[0024] The nfc_strt pin is an input, and its effective state is high. When set, it indicates that the host has started an operation.

[0025] The nfc_done pin is an output with a valid state of high. When set, it indicates that an operation is completed.

[0026] Furthermore, the pin configuration of the NAND FLASH interface includes:

[0027] I / O[7:0] pins are input / output, with the valid state being N / A. They are used to send commands, addresses, and data to NAND FLASH and receive data during read operations.

[0028] The CLE pin is an output, and its effective state is high, indicating that the command latch is enabled;

[0029] The ALE pin is an output, and its effective state is high, indicating that the address latch is enabled;

[0030] WE_n pin is an output, and its effective state is low, indicating write enable;

[0031] RE_n pin is an output, and its effective state is low, indicating read enable;

[0032] CE_n pin is an output, and its effective state is low, indicating that the chip is enabled;

[0033] The R_nB pin is an input, and its valid state is N / A. When this signal is high, NAND FLASH is ready for the next operation, and when this signal is low, the internal operation is in progress.

[0034] The present invention also provides a NAND FLASH cache method based on STT-MRAM. Under the NAND FLASH controller architecture based on STT-MRAM, the STT-MRAM cache is divided into an FTL mapping table storage area, a log area, and a data cache area according to the memory address;

[0035] The FTL mapping table storage area is used to store and update the FTL mapping table, write the updates of the FTL mapping table pages in situ, and change the mapping directory that tracks the location of the FTL mapping table pages;

[0036] The log area is used to record metadata logs, and the logs are updated in advance through the WAL technology;

[0037] The data buffer area and the NAND FLASH storage are divided with the same page granularity, and page alignment is used when moving the data of the entire page to the NAND FLASH.

[0038] Furthermore, a metadata log operation process is also included, and the metadata log operation process includes:

[0039] The NAND FLASH controller receives a write instruction from the host, allocates a data buffer area page and writes the data, and after completion confirms to the host that the data has been received;

[0040] The corresponding NAND FLASH physical address is allocated through the FTL layer, and the metadata log is generated. At this time, the judgment flag written in the NAND FLASH is set to 0; the metadata log is written to the log area, and the NAND FLASH controller is confirmed that the metadata log writing has been completed;

[0041] After the NAND FLASH controller confirms that the metadata log is generated, it starts writing into the NAND FLASH according to the allocated physical address, updates the FTL mapping table after completion, and updates the write log flag bit of the log area to 1;

[0042] The NAND FLASH controller starts a checkpoint operation to confirm whether there is enough space in the log area. If the log area is about to be full, the log area is recycled and the completed log entry space is marked.

[0043] The present invention also provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the NAND FLASH cache method based on STT-MRAM is implemented.

[0044] The above technical solution of the present invention has the following beneficial effects compared with the prior art:

[0045] The cache write strategy in the present invention combines log pre-write and metadata technology on the basis of utilizing the persistence of STT-MRAM cache data, effectively solves the storage loss problem caused by frequent write operations of mapping table updates and log file systems, and prolongs the service life of NAND FLASH. At the same time, it ensures the atomicity of cache data and improves the data recovery capability in the event of an unexpected power outage. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0047] Figure 1 1 is an overall architecture diagram of the controller architecture in a preferred embodiment of the present invention.

[0048] Figure 2 FIG. 4 is a cache structure diagram of STT-MRAM in a preferred embodiment of the present invention.

[0049] Figure 3 This is a flowchart of the working process under the controller architecture in the preferred embodiment of the present invention.

[0050] Figure 4 The figure is a flowchart of metadata log operation in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0052] Embodiment 1

[0053] The present invention combines the design of a novel non-volatile storage STT-MRAM with a NAND FLASH controller to carry out research, aiming to solve the problem of reduced lifespan caused by the erase-before-write feature of NAND FLASH. Figure 1As shown, the present invention discloses a NAND FLASH controller architecture based on STT-MRAM, including a NAND FLASH controller, a host interface, and a NAND FLASH interface, wherein the NAND FLASH controller is connected to the host interface and the NAND FLASH interface respectively. The NAND FLASH controller includes a dual-port STT-MRAM cache module, which is used to implement internal data buffering and buffering processes, and is used as a data buffer when the host writes data to the NAND FLASH and reads data from the NAND FLASH, and stores mapping tables and metadata logs. The NAND FLASH controller generates metadata including updated mapping entries, timestamp records, and a flag bit for judging whether writing is complete. Figure 3 It shows the log process and the correspondence between recorded information.

[0054] In this embodiment, the NAND FLASH controller further includes a command parsing module and a timing control module. The command parsing module and the timing control module are the main modules in the design. The two modules each include a state machine. The state machine in the command parsing module and the state machine in the timing control module cooperate with each other. The state machine in the command parsing module interprets the command from the host and transmits the control signal to the timing control module. The state machine in the timing control module generates all necessary control signals according to the received control signal so that the NAND FLASH performs repetitive tasks with strict timing requirements.

[0055] In this embodiment, the NAND FLASH controller further includes an address counting module, which generates an address control signal required for data buffering according to a state machine in the command parsing module to determine the completion status of data operations.

[0056] In this embodiment, the NAND FLASH controller also includes an ECC check code generation module and an ECC check code detection module. The ECC check code generation module generates an ECC check code during a page programming operation and stores the ECC check code in the OOB area of ​​the NAND FLASH. The ECC check code detection module uses the ECC check code in the NAND FLASH during a host read operation to detect errors in the data to ensure data integrity.

[0057] In this embodiment, the dual-port STT-MRAM cache module is a dual-port RAM.

[0058] In this embodiment, the pin configuration of the host interface is shown in Table 1, specifically including:

[0059] CLK pin is input, the valid state is N / A, indicating the clock signal;

[0060] RES pin is an input, the effective state is high, indicating a reset signal;

[0061] BF_sel pin, input high, effective state is high, indicating dual-port STT-MRAM enable signal;

[0062] BF_ad[10:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM address signal;

[0063] BF_din[7:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM data signal;

[0064] BF_we pin is an input, and its effective state is high, indicating the dual-port STT-MRAM write signal;

[0065] RWA[15:0] pin is input, the valid state is N / A, indicating that the NAND FLASH writes the physical address signal;

[0066] BF_dou[7:0] pin is output, and its valid state is N / A, indicating that the dual-port STT-MRAM transmits data to the host;

[0067] PErr pin is an output, the effective state is high, indicating a page programming operation error signal;

[0068] EErr pin is an output, the effective state is high, indicating a block erase operation error signal;

[0069] RErr pin is an output, the effective state is high, indicating a page read operation error signal;

[0070] nfc_cmd[2:0] pin is input, the valid state is N / A, indicating the command code signal;

[0071] The nfc_strt pin is an input, and its effective state is high. When set, it indicates that the host has started an operation.

[0072] The nfc_done pin is an output with a valid state of high. When set, it indicates that an operation is completed.

[0073] Table 1 Host interface pin list

[0074] Signal name IO Valid status definition CLK enter N / A Clock signal RES enter high Reset signal BF_sel enter high Dual-port STT-MRAM enable signal BF_ad[10:0] enter N / A Dual-port STT-MRAM address signal BF_din[7:0] enter N / A Dual-port STT-MRAM data signal BF_we enter high Dual-port STT-MRAM write signal RWA[15:0] enter N / A NAND FLASH device writes physical address signal BF_dou[7:0] Output N / A Dual-port STT-MRAM transmits data to the host PErr Output high Page Program Operation Error Signal EER Output high Block erase operation error signal R Output high Page read operation error signal nfc_cmd[2:0] enter N / A Command code signal nfc_strt enter high When set, indicates that the host has initiated an operation nfc_done Output high When set, indicates that an operation is completed

[0075] In this embodiment, the pin settings of the NAND FLASH interface are shown in Table 2, specifically including:

[0076] I / O[7:0] pins are input / output, with the valid state being N / A. They are used to send commands, addresses, and data to NAND FLASH and receive data during read operations.

[0077] The CLE pin is an output, and its effective state is high, indicating that the command latch is enabled;

[0078] The ALE pin is an output, and its effective state is high, indicating that the address latch is enabled;

[0079] WE_n pin is an output, and its effective state is low, indicating write enable;

[0080] RE_n pin is an output, and its effective state is low, indicating read enable;

[0081] CE_n pin is an output, and its effective state is low, indicating that the chip is enabled;

[0082] The R_nB pin is an input, and its valid state is N / A. When this signal is high, NAND FLASH is ready for the next operation, and when this signal is low, the internal operation is in progress.

[0083] Table 2 NAND FLASH interface pin list

[0084]

[0085] Embodiment 2

[0086] like Figure 2-Figure 4 As shown, the present invention also discloses a NAND FLASH cache method based on STT-MRAM. Under the NAND FLASH controller architecture based on STT-MRAM described in Example 1, based on the non-volatility and byte addressing of STT-MRAM, the STT-MRAM cache is divided into an FTL mapping table storage area, a log area, and a data cache area according to the memory address.

[0087] The FTL mapping table storage area is used to store and update the FTL mapping table, write the update of the FTL mapping table page in place, and change the mapping directory that tracks the location of the FTL mapping table page. The log area is used to record metadata logs, and the logs are updated in advance through the WAL (Write-Ahead Logging) technology so that checkpoint operations can be performed when the log area is full. The data cache area is consistent with the NAND FLASH storage and is divided into pages of the same size to reduce the complexity of metadata in the log and ensure efficient and consistent data transmission; page alignment is used when moving the data of the entire page to NAND FLASH. Through page alignment, the data of the entire page can be moved to NAND FLASH at one time and efficiently, thereby improving data transmission efficiency.

[0088] This embodiment also includes a metadata log operation process, which divides the write operation into four independent transactions and processes them in sequence, such as Figure 4 Specifically shown include:

[0089] S1: The NAND FLASH controller receives a write instruction from the host, allocates a data buffer page and writes the data, and after completion, confirms to the host that the data has been received;

[0090] S2: Assign the corresponding NAND FLASH physical address through the FTL layer (Flash Translation Layer) and start generating metadata logs. At this time, the judgment flag written in the NAND FLASH is set to 0; write the metadata log to the log area, and confirm to the NAND FLASH controller that the metadata log writing has been completed;

[0091] S3: After the NAND FLASH controller confirms that the metadata log is generated, it starts to write into the NAND FLASH according to the allocated physical address, and after completion, updates the FTL mapping table to ensure data consistency, and updates the write log flag bit of the log area to 1;

[0092] S4: The NAND FLASH controller starts a checkpoint operation to confirm whether there is enough space in the log area. If the log area is about to be full, the log area is recycled and the completed (ie, the mark bit is 1) log entry space is marked.

[0093] The entire metadata log operation process is designed to ensure that when data is written, the relevant metadata and mapping information are updated in real time, and can be quickly restored to a consistent state based on the log in the event of a power outage or other abnormality. Figure 4 It can be seen that except for the data update itself which needs to be written into NAND Flash, the rest of the update operations are completed in STT-MRAM.

[0094] Embodiment 3

[0095] The present invention also discloses a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the NAND FLASH cache method based on STT-MRAM in the second embodiment is implemented.

[0096] The present invention utilizes the byte addressing, low static power consumption and non-volatile characteristics of STT-MRAM to innovate the cache design of the NAND FLASH controller. The cache write strategy in the present invention combines log pre-write and metadata technology on the basis of utilizing the persistence of STT-MRAM cache data, effectively solves the storage loss problem caused by frequent write operations of the mapping table and log file system, and prolongs the service life of NAND FLASH, while ensuring the atomicity of cache data and improving data recovery capabilities in the event of unexpected power outages. Compared with traditional DRAM cache solutions, this design does not need to frequently transfer cache data to NAND FLASH to ensure data consistency, can effectively prolong the service life of NAND FLASH, and reduces dependence on power-off protection technology, simplifying system design.

[0097] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0098] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0099] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0100] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0101] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A NAND FLASH controller architecture based on STT-MRAM, characterized by: It includes a NAND FLASH controller, a host interface, and a NAND FLASH interface, wherein the NAND FLASH controller is connected to the host interface and the NAND FLASH interface respectively; The NAND FLASH controller includes a dual-port STT-MRAM cache module, which is used to implement internal data buffering and buffering process, and is used as a data buffer when the host writes data to the NAND FLASH and reads data from the NAND FLASH, and stores a mapping table and a metadata log.

2. The STT-MRAM-based NAND FLASH controller architecture according to claim 1, characterized in that: The NAND FLASH controller further includes a command parsing module and a timing control module, wherein the command parsing module and the timing control module each include a state machine; the state machine in the command parsing module interprets the command from the host and transmits the control signal to the timing control module; The state machine in the timing control module generates all necessary control signals according to the received control signal so that the NAND FLASH performs repetitive tasks with strict timing requirements.

3. The STT-MRAM-based NAND FLASH controller architecture according to claim 2, characterized in that: The NAND FLASH controller further includes an address counting module, which generates an address control signal required for data buffering according to a state machine in the command parsing module to determine the completion status of data operations.

4. The STT-MRAM-based NAND FLASH controller architecture according to claim 1, characterized in that: The NAND FLASH controller also includes an ECC check code generation module and an ECC check code detection module. The ECC check code generation module generates an ECC check code during a page programming operation and stores the ECC check code in the OOB area of ​​the NAND FLASH. The ECC check code detection module uses the ECC check code in the NAND FLASH to detect errors in data during a read operation performed by the host.

5. The STT-MRAM-based NAND FLASH controller architecture according to claim 1, characterized in that: The dual-port STT-MRAM cache module is a dual-port RAM.

6. The STT-MRAM-based NAND FLASH controller architecture according to claim 1, characterized in that: The pin configuration of the host interface includes: CLK pin is input, the valid state is N / A, indicating the clock signal; RES pin is an input, and its effective state is high, indicating a reset signal; BF_sel pin, input high, effective state is high, indicating dual-port STT-MRAM enable signal; BF_ad[10:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM address signal; BF_din[7:0] pin is input, the valid state is N / A, indicating the dual-port STT-MRAM data signal; BF_we pin is an input, and its effective state is high, indicating the dual-port STT-MRAM write signal; RWA[15:0] pin is input, the valid state is N / A, indicating that the NAND FLASH writes the physical address signal; BF_dou[7:0] pin is output, and its valid state is N / A, indicating that the dual-port STT-MRAM transmits data to the host; PErr pin is an output, the effective state is high, indicating a page programming operation error signal; EErr pin is an output, the effective state is high, indicating a block erase operation error signal; RErr pin is an output, the effective state is high, indicating a page read operation error signal; nfc_cmd[2:0] pin is input, the valid state is N / A, indicating the command code signal; The nfc_strt pin is an input, and its effective state is high. When set, it indicates that the host has started an operation. The nfc_done pin is an output with a valid state of high. When set, it indicates that an operation is completed.

7. The STT-MRAM-based NAND FLASH controller architecture according to claim 1, characterized in that: The pin settings of the NAND FLASH interface include: I / O[7:0] pins are input / output, with the valid state being N / A. They are used to send commands, addresses, and data to NAND FLASH and receive data during read operations. The CLE pin is an output, and its effective state is high, indicating that the command latch is enabled; The ALE pin is an output, and its effective state is high, indicating that the address latch is enabled; WE_n pin is an output, and its effective state is low, indicating write enable; RE_n pin is an output, and its effective state is low, indicating read enable; CE_n pin is an output, and its effective state is low, indicating that the chip is enabled; The R_nB pin is an input, and its valid state is N / A. When this signal is high, NAND FLASH is ready for the next operation, and when this signal is low, the internal operation is in progress.

8. A NAND FLASH cache method based on STT-MRAM, characterized in that: In the STT-MRAM-based NAND FLASH controller architecture described in any one of claims 1 to 7, the STT-MRAM cache is divided into an FTL mapping table storage area, a log area, and a data cache area according to the memory address; The FTL mapping table storage area is used to store and update the FTL mapping table, write the updates of the FTL mapping table pages in situ, and change the mapping directory that tracks the location of the FTL mapping table pages; The log area is used to record metadata logs, and the logs are updated in advance through the WAL technology; The data buffer area and the NAND FLASH storage are divided with the same page granularity, and page alignment is used when moving the data of the entire page to the NAND FLASH.

9. The STT-MRAM-based NAND FLASH caching method according to claim 8, characterized in that: It also includes a metadata log operation process, which includes: The NAND FLASH controller receives a write instruction from the host, allocates a data buffer area page and writes the data, and after completion confirms to the host that the data has been received; The corresponding NAND FLASH physical address is allocated through the FTL layer, and the metadata log is generated. At this time, the judgment flag written in the NAND FLASH is set to 0; the metadata log is written to the log area, and the NAND FLASH controller is confirmed that the metadata log writing has been completed; After the NAND FLASH controller confirms that the metadata log is generated, it starts writing into the NAND FLASH according to the allocated physical address, updates the FTL mapping table after completion, and updates the write log flag bit of the log area to 1; The NAND FLASH controller starts a checkpoint operation to confirm whether there is enough space in the log area. If the log area is about to be full, the log area is recycled and the completed log entry space is marked.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the STT-MRAM-based NAND FLASH cache method according to claim 8 or 9 is implemented.

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