Semiconductor device and semiconductor system

Abstract

The invention provides a semiconductor device and a semiconductor system. The semiconductor device includes at least one memory layer and a peripheral circuit coupled to the memory layer; wherein each storage layer comprises a plurality of storage units, a plurality of first conductive wires and a plurality of second conductive wires; the memory unit is located between the first conductive line and the second conductive line in the first direction; the plurality of memory cells arranged along the second direction are coupled with one first conductive wire, and the plurality of memory cells arranged along the third direction are coupled with one second conductive wire; the plurality of storage units are configured to store a matrix; the peripheral circuit is configured to: apply an input voltage on a plurality of first conductive lines in the memory layer based on input data; and obtaining an operation result of the input data and the matrix stored in the plurality of storage units in the storage layer based on the output current or the output voltage of the second conductor wire in the storage layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a semiconductor system. Background Art

[0002] In the classic von Neumann computing architecture, the memory and processor are separated, and data is transmitted between the two through a data bus. When executing a command, the processor first reads data from the memory, and after processing, writes the updated data back to the memory. The frequent movement of data brings huge power consumption and time overhead. In addition, due to the limited memory bandwidth, the processing speed of the processor is limited by the access speed of the memory, which will limit the improvement of computing performance. With the rise of application fields such as big data and artificial intelligence, the demand for processing massive data has made the bottleneck of the von Neumann computing architecture more and more prominent. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor device and a semiconductor system.

[0004] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, comprising at least one storage layer and a peripheral circuit coupled to the storage layer; wherein:

[0005] Each of the storage layers comprises a plurality of storage units, a plurality of first conductive lines and a plurality of second conductive lines; the storage units are located between the first conductive lines and the second conductive lines in a first direction; a plurality of storage units arranged along a second direction are coupled to a first conductive line, and a plurality of storage units arranged along a third direction are coupled to a second conductive line; the second direction intersects the third direction and is perpendicular to the first direction; the plurality of storage units are configured as a storage matrix;

[0006] The peripheral circuit is configured to: apply an input voltage to the first conductive lines in the storage layer based on input data; and obtain an operation result of the input data and the matrix stored in the plurality of storage cells in the storage layer based on an output current or an output voltage of a second conductive line in the storage layer.

[0007] In an optional embodiment, the memory cell has a first state and a second state; the threshold voltage of the memory cell in the first state is less than the threshold voltage of the memory cell in the second state and greater than the subthreshold voltage of the memory cell; the input voltage applied to one of the first conductive lines includes a first voltage and a second voltage; the first voltage is greater than the subthreshold voltage of the memory cell and less than the threshold voltage of the memory cell in the second state; the second voltage is less than the subthreshold voltage of the memory cell;

[0008] The memory cell coupled to the first conductive line to which the first voltage is applied and in the first state is configured to: output a first current or a first output voltage;

[0009] The storage unit coupled to the first conductive line to which the first voltage is applied and in the second state is configured to: output a second current or a second output voltage greater than the first current; the second current is smaller than the first current, and the second output voltage is smaller than the first output voltage.

[0010] In an optional implementation, the peripheral circuit includes an input circuit and a counting circuit; wherein,

[0011] The input circuit is connected to the first conductive line and is configured to: apply the input voltage to the plurality of first conductive lines respectively in multiple times based on the input data, and apply the input voltage to one first conductive line each time;

[0012] The counting circuit is connected to the second conductive line and is configured to: count the number of times the output current of each second conductive line is greater than a preset current to obtain a calculation result of the input data and the matrix, wherein the preset current is greater than the second current and less than the first current; or count the number of times the output voltage of each second conductive line is greater than a preset voltage to obtain a calculation result of the input data and the matrix, wherein the preset voltage is greater than the second output voltage and less than the first output voltage.

[0013] In an optional implementation, the peripheral circuit includes an input circuit and a calculation circuit; wherein,

[0014] The input circuit is connected to the first conductive line and is configured to: simultaneously apply the input voltage to a plurality of the first conductive lines in the storage layer based on the input data;

[0015] The calculation circuit is connected to the second conductive wires and is configured to: round the output current of each second conductive wire relative to a multiple of the first current to obtain an operation result of the input data and the matrix; or round the output voltage of each second conductive wire relative to a multiple of the first output voltage to obtain an operation result of the input data and the matrix.

[0016] In an optional implementation, the first voltage is less than a threshold voltage of the memory cell in the first state.

[0017] In an optional implementation, the peripheral circuit is configured as:

[0018] Before applying an input voltage to the first conductive lines in the storage layer based on input data, memory cells in the storage layer are programmed to a first state or a second state based on the matrix to write the matrix into the memory cells.

[0019] In an optional implementation, the input data includes a first bit and a second bit, and a value of the first bit is different from a value of the second bit;

[0020] The input circuit is configured to: apply a first voltage to the first conductive line corresponding to the first bit, and apply a second voltage to the first conductive line corresponding to the second bit; or,

[0021] The input circuit is configured to apply the first voltage only to the first conductive line corresponding to the first bit.

[0022] In an optional implementation, the semiconductor device includes two storage layers stacked and arranged along the first direction and sharing the second conductive line; and the peripheral circuit is configured as follows:

[0023] Simultaneously applying an input voltage to the first conductive lines of the two storage layers based on the input data;

[0024] The operation result of the input data and the matrix stored in the plurality of storage units in the two storage layers is obtained based on the output current or the output voltage of the second conductive line.

[0025] In an optional implementation, the storage unit includes a gating element and a phase change element stacked and arranged along the first direction; the gating element is located between the first conductive line and the phase change element.

[0026] In a second aspect, an embodiment of the present disclosure provides a semiconductor system, including:

[0027] At least one semiconductor device according to any one of the above embodiments;

[0028] The controller is coupled to at least one of the semiconductor devices and is configured to send input data to the semiconductor device and receive operation results of the semiconductor device.

[0029] In the technical solution provided by the present disclosure, the semiconductor device includes at least one storage layer and a peripheral circuit coupled to the storage layer, and the peripheral circuit can be configured to apply an input voltage to a plurality of first conductive lines in the storage layer based on input data; and obtain the operation result of the input data and the matrix stored in the plurality of storage units in the storage layer based on the output current or output voltage of the second conductive line in the storage layer. Further, the subthreshold interval of the counting circuit and / or the storage unit can be used for operation. On the one hand, by applying the input voltage to the first conductive line for multiple times and using the counting circuit to count the number of times the output current of the second conductive line is greater than the preset current or the number of times the output voltage is greater than the preset voltage to obtain the operation result, the accuracy of the operation can be improved; on the other hand, using the subthreshold interval of the storage unit for operation can further reduce the power consumption of the input circuit and reduce the risk of the device coupled to the output end of the second conductive line being broken down, and the voltage establishment time can also be shortened. In summary, the semiconductor device provided by the present disclosure can reduce the power consumption of the operation, reduce the risk of the output end device being broken down, and can improve the accuracy of the operation on the basis of controlling the operation time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 1 ;

[0031] Figure 2 A schematic diagram of a three-dimensional structure of a part of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0032] Figure 3 A current-voltage curve 1 of a memory cell provided in an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 2 ;

[0034] Figure 5 A schematic diagram of the composition of an input circuit provided in an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of a calculation process provided for a specific example of the present disclosure;

[0036] Figure 7 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 3 ;

[0037] Figure 8 A second current-voltage curve of a memory cell provided in an embodiment of the present disclosure;

[0038] Fig. 9A schematic diagram of a three-dimensional structure of a portion of the structure in two storage layers sharing a second conductive line provided by an embodiment of the present disclosure;

[0039] Fig.10 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 4 ;

[0040] Fig.11 A schematic diagram of a semiconductor system provided for an embodiment of the present disclosure;

[0041] Fig.12 A schematic flow chart of an operating method of a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0043] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0044] In the drawings, like reference numerals refer to like elements throughout.

[0045] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] In the classic von Neumann computing architecture, the memory used to store data is separated from the processor used for data processing, and data is transmitted between the two through a data bus. When executing a data processing command, the processor needs to read the data from the memory first, and then write the updated data back to the memory after processing. This requires frequent data transmission between the memory and the processor, which will bring huge power consumption and time overhead. In addition, due to the limited bandwidth of the memory, the processing speed of the processor is limited by the access speed of the memory, which will limit the improvement of computing performance. With the rise of application fields such as big data and artificial intelligence, the demand for processing massive data has made the bottleneck of the von Neumann computing architecture more and more prominent.

[0048] In order to solve the bottleneck of the classic von Neumann computing architecture, the storage and computing integrated chip architecture came into being. Its basic idea is to directly use the memory for logical calculations, thereby reducing the overhead caused by frequent data transmission between the memory and the processor, thereby improving computing performance while reducing power consumption.

[0049] In some embodiments, the storage-computing integrated chip may include one of the memories such as static random access memory (SRAM), dynamic random access memory (DRAM), phase change memory (PCM), NAND flash memory (NAND Flash Memory), etc. Among them, PCM is a storage class memory (SCM), which has non-volatility and large storage capacity, especially three-dimensional PCM with a three-dimensional structure, which has the characteristics of high storage density and fast read and write speed, and has the potential to be developed into a storage-computing integrated chip. The following will introduce the relevant content of three-dimensional PCM.

[0050] Figure 1 A schematic diagram of the composition of the semiconductor device provided by the present disclosure Figure 1 , Figure 2 This is a schematic diagram of a three-dimensional structure of a part of the structure of the semiconductor device provided in the embodiment of the present disclosure. Figure 1 and Figure 2 , the semiconductor device includes at least one storage layer 10 and a peripheral circuit 20 coupled to the at least one storage layer 10; wherein each storage layer 10 includes a plurality of storage cells 100, a plurality of first conductive lines 121 and a plurality of second conductive lines 120; the storage cells 100 are located between the first conductive lines 121 and the second conductive lines 120 in the first direction, the plurality of storage cells 100 arranged along the second direction are coupled to one first conductive line 121, and the plurality of storage cells 100 arranged along the third direction are coupled to one second conductive line 120; the second direction intersects with the third direction and is perpendicular to the first direction. Here, the first direction is the Z direction, the second direction is the X direction, and the third direction is the Y direction as an example.

[0051] It should be noted that the number of first conductive lines, the number of second conductive lines, and the number of storage units shown in the figures are only examples, and the present disclosure does not impose any specific limitations on this.

[0052] In some embodiments, reference Figure 2 The memory cell 100 includes a gating element 102 and a phase change element 104 stacked and arranged along a first direction, and the gating element 102 is located between the first conductive line 121 and the phase change element 104. In addition, the memory cell 100 also includes a first electrode 101, a second electrode 103 and a third electrode 105. The first electrode 101 is located between the gating element 102 and the first conductive line 121, the second electrode 103 is located between the gating element 102 and the phase change element 104, and the third electrode 105 is located between the phase change element 104 and the second conductive line 120.

[0053] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include a conductive material and may serve as a conductive path. Here, the conductive material may be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0054] In some specific examples, the second electrode 103 may further include a thermal insulation material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0055] In some specific examples, the resistance of the gating element 102 may change in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may include a material having an Ovonic Threshold Switch (OTS) property, and the material having the OTS property may include at least one element of oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn x Te y ,Ge x Te y , Nb x O y 、Si x As y Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 may be in a high resistance state that prevents current from flowing, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 may be in a low resistance state that allows current to flow.

[0056] In a specific example, the phase change element 104 can be reversibly switched between a crystalline state and an amorphous state, and the difference in resistivity between the crystalline state and the amorphous state can be used to achieve data storage. Specifically, the crystal phase of the phase change element 104 can be changed by the Joule heat generated by the voltage applied between the second electrode 103 and the third electrode 105 to change the resistance of the phase change element 104, thereby changing the data stored in the phase change memory unit 100. In some embodiments, the phase change element 104 may include a chalcogenide component, such as a binary compound such as GaSb, InSb, InSe, SbTe, and GeTe, a ternary compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe, and a quaternary compound such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS.

[0057] The two ends of the memory cell 100 are respectively connected to a first conductive line 121 and a second conductive line 120, the first electrode 101 is connected to the first conductive line 121, the first conductive line 121 may be a word line (Word Line, WL), the third electrode 105 is connected to the second conductive line 120, the second conductive line 120 may be a bit line (Bit Line, BL). A memory layer 10 may include a plurality of first conductive lines 121 and a plurality of second conductive lines 120, the extension direction of the first conductive line 121 and the extension direction of the second conductive line 120 may intersect, and both are perpendicular to the extension direction of the memory cell 100. The first conductive line 121 and the second conductive line 120 may include conductive materials.

[0058] In some embodiments, when a semiconductor device including at least one memory layer 10 is used as a memory-computing integrated chip, a plurality of memory cells 100 in the memory layer 10 may be configured as a memory matrix. Specifically, each memory cell 100 may be configured as an element in the memory matrix.

[0059] In some embodiments, the peripheral circuit 20 may be configured to program the memory cells 100 in the memory layer 10 to the first state or the second state based on the matrix, so as to write the matrix into the plurality of memory cells 100. Here, the matrix may be a binary matrix including a plurality of 1s and a plurality of 0s, the first state may be a set (SET) state, and the value of the element stored in the memory cell 100 in the first state may be 1, and the second state may be a reset (RESET) state, and the value of the element stored in the memory cell 100 in the second state may be 0.

[0060] In the embodiment of the present disclosure, after the matrix is ​​written into the plurality of storage cells 100 in the storage layer 10 through a programming operation, the peripheral circuit 20 may be configured to: apply an input voltage to the plurality of first conductive lines 121 in the storage layer 10 based on the input data; and obtain the operation result of the input data and the matrix stored in the plurality of storage cells 100 in the storage layer 10 based on the output current or output voltage of the second conductive line 120 in the storage layer 10. Below, the operation scheme provided by the present disclosure will be introduced in conjunction with specific examples.

[0061] Figure 3 The current-voltage curve of the memory cell provided by the embodiment of the present disclosure is Figure 4 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 2 . Reference Figure 3 , the threshold voltage Vt1 of the memory cell in the first state is different from the threshold voltage Vt2 of the memory cell in the second state, and when different input voltages are applied to the memory cells, the current curve of the memory cell in the first state is different from the current curve of the memory cell in the second state. Specifically, the threshold voltage Vt1 of the memory cell in the first state is less than the threshold voltage Vt2 of the memory cell in the second state. When an input voltage less than the subthreshold voltage Vt0 is applied to the memory cell, neither the memory cell in the first state nor the memory cell in the second state outputs current, and when an input voltage greater than the subthreshold voltage Vt0 and less than the threshold voltage Vt2 of the memory cell in the second state is applied to the memory cell, the current output by the memory cell in the first state is greater than the current output by the memory cell in the second state.

[0062] In a specific example, in conjunction with reference Figure 3 and Figure 4, the input voltage applied to a first conductive line 121 can be a first voltage Vin1 or a second voltage Vin0, the first voltage Vin1 is greater than the subthreshold voltage Vt0 of the memory cell and less than the threshold voltage Vt2 of the memory cell in the second state, and the second voltage Vin0 is less than the subthreshold voltage Vt0 of the memory cell. When the second voltage Vin0 is applied to the first conductive line 121, the memory cell in the first state and the memory cell in the second state coupled to the first conductive line 121 do not output current; when the first voltage Vin1 is applied to the first conductive line 121, the memory cell coupled to the first conductive line 121 and in the first state is configured to: output the first current Iout1, and the memory cell coupled to the first conductive line 121 and in the second state is configured to: output the second current Iout0, and the first current Iout1 is much greater than the second current Iout0.

[0063] In some embodiments, in conjunction with reference Figure 1 and Figure 4 The peripheral circuit 20 may include an input circuit 201 and a calculation circuit 202, wherein the input circuit 201 is connected to the first conductive wire 121 and is configured to: simultaneously apply an input voltage to multiple first conductive wires 121 in the storage layer 10 based on input data; the calculation circuit 202 is connected to the second conductive wire 120 and is configured to: round the output current of each second conductive wire 120 relative to a multiple of the first current to obtain an operation result of the input data and the matrix stored in the multiple storage units 100.

[0064] The above embodiment takes the operation result of the input data and the matrix stored in the plurality of storage units in the storage layer obtained based on the output current of the second conductive line 120 as an example. In other embodiments, the operation result of the input data and the matrix stored in the plurality of storage units in the storage layer can also be obtained based on the output voltage of the second conductive line 120. Specifically, the storage unit coupled to the first conductive line 121 to which the first voltage Vin1 is applied and in the first state is configured to: output the first output voltage Vout1; the storage unit coupled to the first conductive line 121 to which the second voltage Vin0 is applied and in the second state is configured to: output the second output voltage Vout0, and the first output voltage Vout1 is greater than the second output voltage Vout0; the calculation circuit 202 is configured to: round the output voltage of each second conductive line 120 relative to the multiple of the first output voltage Vout1 to obtain the operation result of the input data and the matrix.

[0065] In some embodiments, the input data may be a vector including multiple bits. Specifically, the input data may include multiple first bits and multiple second bits, and the value of the first bit is different from the value of the second bit. For example, the value of the first bit may be 1 and the value of the second bit may be 0.

[0066] In some specific examples, Figure 5 A schematic diagram of the composition of the input circuit provided in the embodiment of the present disclosure, combined with reference to Figure 4 and Figure 5 The input circuit 201 may include a control logic 2011, a digital-to-analog conversion circuit 2012, a voltage generator 2013, and a word line driving circuit 2014, wherein the control logic 2011 is coupled to the digital-to-analog conversion circuit 2012, the voltage generator 2013, and the word line driving circuit 2014. The digital-to-analog conversion circuit 2012 may convert a plurality of first bits and a plurality of second bits in the input data into a first voltage signal corresponding to the first bit and a second voltage signal corresponding to the second bit, respectively, and the voltage generator 2013 may be configured to generate an input voltage corresponding to the first bit in response to the first voltage signal, and to generate an input voltage corresponding to the second bit in response to the second voltage signal. The word line driving circuit 2014 may apply the input voltage corresponding to the first bit to the first conductive line 121 corresponding to the first bit, and apply the input voltage corresponding to the second bit to the first conductive line 121 corresponding to the second bit.

[0067] In some specific examples, the output end of the second conductive line 120 can be coupled to a low voltage, for example, the output end of the second conductive line 120 can be coupled to a ground end, and when the storage unit coupled to the second conductive line 120 outputs current, the current will flow toward the ground end. The calculation circuit 202 can be connected between the second conductive line 120 and the ground end, and can measure the output current or output voltage of the second conductive line 120.

[0068] In a specific example, in conjunction with reference Figure 3 and Figure 4, the input circuit 201 can apply different input voltages to different first conductive lines 121, wherein the input voltage corresponding to the first bit in the input data is different from the input voltage corresponding to the second bit in the input data. Here, the input voltage corresponding to the first bit can be the first voltage Vin1, and the input voltage corresponding to the second bit can be the second voltage Vin0. Then, any one of the input voltages V1, V2, V3 and V4 applied to the first conductive line 121 can be the first voltage Vin1 or the second voltage Vin0. For a unit to which the first voltage Vin1 is applied and which is in the first state, the output current is the first current Iout1 or the output voltage is the first output voltage Vout1; for a storage unit to which the first voltage Vin1 is applied and which is in the second state, the output current is the second current Iout0 or the output voltage is the second output voltage Vout0, and the first current Iout1 is much larger than the second current Iout0, and the first output voltage Vout1 is much larger than the second output voltage Vout0; and a storage unit to which the second voltage Vin0 is applied and which is in the first state or the second state does not output a current or a voltage, then when the input circuit 201 applies a plurality of input voltages to the first conductive line 121 at the same time, the output of the second conductive line 120 is a plurality of storage units coupled to the second conductive line 120. The calculation circuit 202 may include a calculation unit 2020 connected to each second conductive line 120, which may be configured to round the output current on each second conductive line 120 relative to the multiple of the first current Iout1, or to round the output voltage on each second conductive line 120 relative to the multiple of the first output voltage Vout1, so as to obtain the multiplication operation of the input data with a column of values ​​in the matrix stored in the storage unit coupled to the second conductive line 120 and accumulate the products, that is, the multiplication and accumulation operation is realized, and the combination of the operation results corresponding to the output currents or output voltages of the plurality of second conductive lines 120 is the operation result of the input data and the matrix stored in the plurality of storage units 100 in the storage layer 10, that is, the vector and matrix operation is realized.

[0069] In some specific examples, the computing unit 2020 may further include a sensing circuit, an analog-to-digital conversion circuit, and an operation circuit, wherein the sensing circuit may be configured to sense the output current or output voltage of the second conductive line 120, the analog-to-digital conversion circuit may be configured to convert the output current or output voltage into a corresponding digital signal, and the operation circuit may be configured to calculate the multiple of the output current relative to the first current Iout1 and round it, or calculate the multiple of the output voltage relative to the first output voltage Vout1 and round it, so as to obtain the operation result of the input data and the matrix.

[0070] It should be noted that the computing circuit may also be any combination of circuit elements that can achieve the same function.

[0071] In a specific example, in conjunction with reference Figure 3 , Figure 4 and Figure 6 , the input data may be a vector

[0111] , then the input voltage V1 may be the second voltage Vin0, and the input voltages V2, V3, and V4 may all be the first voltage Vin1. The matrix stored in the plurality of storage cells 100 may include a plurality of 1s and a plurality of 0s, wherein the storage cell corresponding to 1 is in the first state, and the storage cell corresponding to 0 is in the second state. When the input circuit 201 applies input voltages V1, V2, V3, and V4 simultaneously, one of the plurality of storage cells 100 coupled to the second conductive line 120 having an output current of I1 is a storage cell in the first state and to which the first voltage Vin1 is applied, then the operation result corresponding to the output current I1 is 1, and the operation process is 0*1+1*0+1*0+1*1=1; one of the plurality of storage cells 100 coupled to the second conductive line 120 having an output current of I2 is a storage cell in the first state and to which the first voltage Vin1 is applied, then the operation result corresponding to the output current I2 is 1, and the operation process is 0*0 +1*0+1*0+1*1=1; among the plurality of storage cells 100 coupled to the second conductive line 120 with an output current of I3, there are three storage cells in the first state and applied with the first voltage Vin1, then the operation result corresponding to the output current I3 is 3, and the operation process is 0*1+1*1+1*1+1*1=3; among the plurality of storage cells 100 coupled to the second conductive line 120 with an output current of I4, there is one storage cell in the first state and applied with the first voltage Vin1, then the operation result corresponding to the output current I4 is 1, and the operation process is 0*0+1*1+1*0+1*0=1. Then the operation result of the input data and the matrix stored in the plurality of storage cells 100 is

[1131] .

[0072] In the aforementioned embodiment, the input circuit 201 needs to apply input voltages to multiple first conductive lines 121 at the same time, and the first voltage Vin1 corresponding to the first bit in the input data is greater than the threshold voltage Vt1 of the storage unit in the first state and less than the threshold voltage Vt2 of the storage unit in the second state, then the first current Iout1 output by the storage unit in the first state coupled to the first conductive line 121 to which the first voltage Vin1 is applied is large, and when multiple storage units coupled to the same second conductive line 120 output the first current Iout1, the current at the output end of the second conductive line 120 will be large. In this case, the input circuit 201 will generate a large peak power consumption, and the device coupled to the current output end of the second conductive line 120 (such as the device in the computing circuit 202) faces a high risk of being broken down by a large current. In this regard, the present disclosure further provides the following embodiments.

[0073] Figure 7 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 3 , combined with reference Figure 1 and Figure 7 In some embodiments, the peripheral circuit 20 includes an input circuit 201 and a counting circuit 204, wherein the input circuit 201 is connected to the first conductive wire 121 and is configured to: apply the input voltage to the plurality of first conductive wires 121 in multiple times based on the input data, and apply the input voltage to one first conductive wire 121 each time; the counting circuit 204 is connected to the second conductive wire 120 and is configured to: count the number of times the output current of each second conductive wire 120 is greater than a preset current, or count the number of times the output voltage of each second conductive wire 120 is greater than a preset voltage, so as to obtain the operation result of the input data and the matrix stored in the plurality of storage units 100.

[0074] In the embodiment of the present disclosure, the input circuit 201 can be configured to apply only one input voltage to a corresponding first conductive line 121 at a time, thereby reducing the peak power consumption generated by the input circuit 201 and reducing the working pressure of the word line driving circuit 2014 in the input circuit 201.

[0075] In some specific examples, refer to Figure 7 The counting circuit 204 may include a plurality of counting units 2040 connected to the second conductive line 120. The counting unit 2040 may count the number of times the output current of the second conductive line 120 connected thereto is greater than a preset current, or count the number of times the output voltage of the second conductive line 120 connected thereto is greater than a preset voltage.

[0076] In a specific example, the counting unit 2040 in the counting circuit 204 may be triggered by current, and may count the number of times the output current of the second conductive line 120 is greater than a preset current. Figure 3 , the preset current can be greater than the second current Iout0 and less than the first current Iout1. Then, after the input circuit 201 applies an input voltage to a corresponding first conductive line 121, only the storage unit in the first state coupled to the first conductive line 121 to which the first voltage Vin1 is applied will output the first current Iout1 greater than the preset current, while the current output by the storage unit in the first state coupled to the first conductive line 121 to which the second voltage Vin0 is applied and the current output by the storage unit in the second state are both less than the preset current, and at this time the second The output current of the conductive wire 120 is equal to the output current of a storage unit coupled to both the second conductive wire 120 and the first conductive wire 121 to which the input voltage is applied. Therefore, when the output current of the second conductive wire 120 is greater than the preset current, 1 is counted, which is equivalent to completing one 1*1=1; when the output current of the second conductive wire 120 is less than the preset current, it is counted as 0, which is equivalent to completing one 1*0=0 or 0*1=0 or 0*0=0. The total number of times the output current of the second conductive wire 120 is greater than the preset current is equivalent to the result obtained by adding up all the products.

[0077] In another specific example, the counting unit 2040 in the counting circuit 204 can be triggered by a voltage and can count the number of times the output voltage of the second conductive line 120 is greater than a preset voltage. The preset voltage can be greater than the second output voltage Vout0 and less than the first output voltage Vout1. Then, after the input circuit 201 applies an input voltage to a first conductive line 121 corresponding thereto, only the storage unit coupled to the first conductive line 121 to which the first voltage Vin1 is applied and in the first state will output the first output voltage Vout1 greater than the preset voltage, while the voltage output by the storage unit coupled to the first conductive line 121 to which the second voltage Vin0 is applied and in the first state and the voltage output by the storage unit in the second state are both less than the preset voltage, and this When , the output voltage of the second conductive line 120 is equal to the output voltage of a storage unit coupled to the second conductive line 120 and the first conductive line 121 to which the input voltage is applied. Therefore, when the output voltage of the second conductive line 120 is greater than the preset voltage, 1 is counted, which is equivalent to completing one 1*1=1; when the output voltage of the second conductive line 120 is less than the preset voltage, it is counted as 0, which is equivalent to completing one 1*0=0 or 0*1=0 or 0*0=0. The total number of times the output voltage of the second conductive line 120 is greater than the preset voltage is equivalent to the result obtained by accumulating all the products.

[0078] In some specific examples, the counting circuit 204 can be configured to complete the conversion from the analog signal (the output current or output voltage of the second conductive wire) to the digital signal (the calculation result) while realizing counting, so that there is no need to set a dedicated analog-to-digital conversion circuit at the output end to convert the analog signal to a digital signal.

[0079] It should be noted that the counting circuit may also be any combination of circuit elements that can achieve the same function.

[0080] In some embodiments, the input circuit 201 may also be configured to apply a voltage only to the first conductive line 121 corresponding to the first bit in the input data. Specifically, in the aforementioned embodiment, the input circuit 201 is configured to apply a first voltage Vin1 to the first conductive line 121 corresponding to the first bit in the input data, and to apply a second voltage Vin0 to the first conductive line 121 corresponding to the second bit in the input data, that is, the number of times the input circuit 201 applies the input voltage to the first conductive line 121 is equal to the total number of bits of the input data. In the embodiment of the present disclosure, the input circuit 201 may also be configured to apply a first voltage Vin1 only to the first conductive line 121 corresponding to the first bit in the input data. Thus, the operation time can be shortened and the total power consumption required for the operation can be reduced.

[0081] In a specific example, referring to Figure 5 The digital-to-analog conversion circuit 2012 can convert only the first bit in the input data into a corresponding voltage signal, the voltage generator 2013 can only generate the first voltage Vin1, and the word line driving circuit 2014 can only transmit the first voltage Vin1 to the first conductive line 121 corresponding to the first bit in the input data.

[0082] In the embodiment of the present disclosure, the input circuit is configured to apply an input voltage to the first conductive line multiple times, and the counting circuit is configured to count the number of times the output current of the second conductive line is greater than a preset current or the number of times the output voltage of the second conductive line is greater than a preset voltage. The counting result is the operation result of the input data and the matrix stored in multiple storage units. This operation method can not only reduce the peak power consumption of the input circuit, reduce the risk of breakdown of the device coupled to the output end of the second conductive line, but also improve the calculation accuracy.

[0083] In some embodiments, the semiconductor device including the three-dimensional PCM is further configured to operate using the subthreshold region of the memory cell. Figure 4 and Figure 8, the input voltage may include a first voltage Vina and a second voltage Vinb, the first voltage Vina is greater than the subthreshold voltage Vt0 of the memory cell 100 and less than the threshold voltage Vt1 of the memory cell in the first state, and the second voltage Vinb is less than the subthreshold voltage Vt0 of the memory cell 100. In this case, the memory cell coupled to the first conductive line 121 to which the first voltage Vina is applied and in the first state is configured to: output a first current Iouta or a first output voltage Vouta; the memory cell coupled to the first conductive line 121 to which the first voltage Vina is applied and in the second state is configured to: output a second current Ioutb or a second output voltage Voutb; the second current Ioutb is less than the first current Iouta, and the second output voltage Voutb is less than the first output voltage Vouta. The input circuit 201 is configured to: simultaneously apply an input voltage to multiple first conductive wires 121 in the storage layer 10 based on input data; the calculation circuit 202 is configured to: round the output current of each second conductive wire 120 relative to a multiple of the first current Iouta, or round the output voltage of each second conductive wire 120 relative to a multiple of the first output voltage Voutb, so as to obtain the operation result of the input data and the matrix.

[0084] In the embodiment of the present disclosure, when the subthreshold interval of the storage unit is used for operation, on the one hand, the magnitude of the first voltage can be reduced, and the peak power consumption of the input circuit can be reduced; on the other hand, the output current of the second conductive line can be reduced, thereby reducing the risk of breakdown of the device coupled to the output end of the second conductive line. However, since the difference between the first current and the second current is relatively small in the subthreshold interval of the storage unit, when the output current of the second conductive line is calculated by the calculation circuit and rounded relative to the multiple of the first current to obtain the operation result of the input data and the matrix, the accuracy of the operation result may be low, so this embodiment is suitable for implementing an artificial neural network algorithm with strong robustness.

[0085] In other embodiments, in combination with reference Figure 7 and Figure 8, the input circuit 201 is configured to: apply the first voltage Vina corresponding to the first bit in the input data to the plurality of first conductive lines 121 in multiple times based on the input data, apply the first voltage Vina to one first conductive line 121 each time, and do not apply voltage to the first conductive line 121 corresponding to the second bit in the input data; the counting circuit 204 is configured to: count the number of times the output current of each second conductive line 120 is greater than the preset current or count the number of times the output voltage of each second conductive line 120 is greater than the preset voltage, so as to obtain the operation result of the input data and the matrix. Here, the preset current can be greater than the second current Ioutb and less than the first current Iouta, and the preset voltage can be greater than the second output voltage Voutb and less than the first output voltage Vouta.

[0086] In the embodiment of the present disclosure, the subthreshold interval of the storage unit and the counting circuit can be used to perform the operation at the same time. On the one hand, by applying the input voltage to the first conductive line multiple times and using the counting circuit to count the number of times the output current of the second conductive line is greater than the preset current or the number of times the output voltage is greater than the preset voltage to obtain the operation result, since only one storage unit of the multiple storage units coupled to the same second conductive line participates in the operation at a time, the accuracy of the operation can be improved, and the problem of reduced reliability of the current accumulation result caused by the relatively small difference between the current output by the storage unit in the first state and the current output by the storage unit in the second state in the subthreshold interval can be compensated; on the other hand, using the subthreshold interval of the storage unit for operation can further reduce the power consumption of the input circuit and reduce the risk of the device coupled to the output end of the second conductive line being broken down, and the voltage establishment time of the first voltage can also be shortened, so as to compensate for the problem of extended operation time caused by applying the input voltage to the first conductive line multiple times. In summary, the semiconductor device provided by the present disclosure can reduce the power consumption of the operation, reduce the risk of the output end device being broken down, and can improve the accuracy of the operation on the basis of controlling the operation time.

[0087] In the above embodiments, a scheme for performing operations using a storage layer in a semiconductor device including a three-dimensional PCM is introduced. In some embodiments, the semiconductor device may include a plurality of storage layers stacked and arranged along a first direction, and the plurality of storage layers include at least two storage layers that share a second conductive line.

[0088] In some embodiments, Fig. 9 A schematic diagram of a three-dimensional structure of a part of the structure in two storage layers sharing a second conductive line provided by an embodiment of the present disclosure, Fig.10 A schematic diagram of the composition of a semiconductor device provided in an embodiment of the present disclosure Figure 4 . Combined with reference Fig. 9 and Fig.10The storage layer 10 and the storage layer 11 are stacked and arranged along the first direction, and the storage layer 10 and the storage layer 11 can share the second conductive line 120 .

[0089] In some specific examples, the storage layer 11 includes a plurality of storage units 110, the storage unit 110 includes a first electrode 111, a phase change element 112, a second electrode 113, a gating element 114 and a third electrode 115, and the storage unit 110 is located between a second conductive line 120 and a first conductive line 122. The specific structural composition of the storage unit 110 is similar to the specific structural composition of the storage unit 100 in the aforementioned embodiment, and will not be repeated here.

[0090] In some embodiments, reference Fig.10 , the peripheral circuit includes an input circuit 201 and a calculation circuit 202, and the plurality of first conductive lines 121 in the storage layer 10 and the plurality of first conductive lines 122 in the storage layer 11 are coupled to the input circuit 201. The peripheral circuit can be configured to: simultaneously apply an input voltage to the first conductive lines in the two storage layers sharing the second conductive line 120 based on the input data; obtain the operation result of the input data and the matrix stored in the plurality of storage cells in the two storage layers based on the output current or output voltage of the second conductive line 120 shared by the two storage layers sharing the second conductive line 120, thereby improving the computing power of the semiconductor device.

[0091] In the embodiment of the present disclosure, for two storage layers sharing the second conductive line 120, the input circuit 201 can apply the input voltage to the multiple first conductive lines in the two storage layers in parallel, so as to obtain the operation result of the input data and the matrix stored in the multiple storage units in the two storage layers. In this way, the input data with more elements can be operated with the matrix with more elements, so as to improve the computing power of the semiconductor device.

[0092] In other embodiments, the two storage layers stacked along the first direction may not share the second conductive wire, and the second conductive wire in each storage layer may be coupled to a counting circuit. In this case, the input circuit may be configured to apply an input voltage to one first conductive wire in multiple storage layers at a time, and the counting circuit may be configured to count the number of times the output current of the second conductive wire in the multiple storage layers is greater than a preset current or the number of times the output voltage of the second conductive wire in the multiple storage layers is greater than a preset voltage, so that the input data and the operation results of different matrices stored in multiple storage units in different storage layers can be obtained at the same time, thereby further improving the parallelism of operations and improving the computing power of semiconductor devices.

[0093] Based on the above semiconductor device, the present disclosure also provides a semiconductor system. Fig.11A schematic diagram of a semiconductor system provided for an embodiment of the present disclosure, the semiconductor system may include at least one semiconductor device 1000 and a controller 2000, wherein the semiconductor device 1000 may be a semiconductor device in any of the above embodiments; the controller 2000 is coupled to at least one semiconductor device 1000 and is configured to send input data to the semiconductor device 1000 and receive operation results of the semiconductor device 1000.

[0094] In some specific examples, the semiconductor device 1000 may be a memory including a three-dimensional PCM, the controller 2000 may be a memory controller, and the semiconductor device 1000 and the controller 2000 may be integrated into one package.

[0095] In some other specific examples, the controller 2000 may be located outside the package in which the semiconductor device 1000 is located. For example, the controller 2000 may be a central processing unit (CPU) of a terminal device. Here, the terminal device may include but is not limited to mobile phones, smart TVs, smart speakers, wearable devices, tablet computers, desktop computers, all-in-one computers, handheld computers, laptops, servers, ultra-mobile personal computers (UMPC), netbooks, personal digital assistants (PDA), laptops, mobile computers, augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, and any other terminal devices or portable terminal devices.

[0096] Based on the above semiconductor device, the present disclosure also provides an operating method of the semiconductor device. Fig.12 A schematic diagram of a process flow of a semiconductor device operating method provided by an embodiment of the present disclosure, such as Fig.12 As shown, the operating method of the semiconductor device includes: applying an input voltage to multiple first conductive lines in a storage layer based on input data; and obtaining an operation result of the input data and a matrix stored in multiple storage units in the storage layer based on an output current or an output voltage of a second conductive line in the storage layer.

[0097] In some embodiments, the memory cell has a first state and a second state; the threshold voltage of the memory cell in the first state is less than the threshold voltage of the memory cell in the second state and is greater than the subthreshold voltage of the memory cell; the input voltage applied to one of the first conductive lines includes a first voltage and a second voltage; the first voltage is greater than the subthreshold voltage of the memory cell; the second voltage is less than the subthreshold voltage of the memory cell; the memory cell coupled to the first conductive line to which the first voltage is applied and in the first state outputs a first current or a first output voltage; the memory cell coupled to the first conductive line to which the first voltage is applied and in the second state outputs a second current or a second output voltage; the second current is less than the first current, and the second output voltage is less than the first output voltage.

[0098] In some embodiments, the step of applying an input voltage to a plurality of first conductive lines in a storage layer based on input data and obtaining a result of an operation between the input data and a matrix stored in a storage unit in the storage layer based on an output current or an output voltage of a second conductive line in the storage layer includes: applying the input voltage to a plurality of first conductive lines in multiple times, applying the input voltage to one first conductive line each time; counting the number of times the output current of each second conductive line is greater than a preset current, the preset current being greater than the second current and less than the first current; or, counting the number of times the output voltage of each second conductive line is greater than a preset voltage, so as to obtain a result of an operation between the input data and the matrix, the preset voltage being greater than the second output voltage and less than the first output voltage.

[0099] In some embodiments, the method of applying an input voltage to multiple first conductive lines in a storage layer based on input data and obtaining an operation result of the input data and a matrix stored in a storage unit in the storage layer based on an output current or an output voltage of a second conductive line in the storage layer includes: simultaneously applying the input voltage to multiple first conductive lines in the storage layer; rounding the output current of each second conductive line relative to a multiple of the first current to obtain an operation result of the input data and the matrix; or rounding the output voltage of each second conductive line relative to a multiple of the first output voltage to obtain an operation result of the input data and the matrix.

[0100] In some embodiments, the first voltage is less than a threshold voltage of the memory cell in the first state.

[0101] In some embodiments, the operating method of the semiconductor device also includes: before applying an input voltage to multiple first conductive lines in the storage layer based on input data, programming the storage cells in the storage layer to a first state or a second state based on the matrix to write the matrix into the multiple storage cells.

[0102] In some embodiments, the input data includes a first bit and a second bit; the value of the first bit is different from the value of the second bit; the operating method of the semiconductor device includes: applying the first voltage to the first conductive line corresponding to the first bit, and applying the second voltage to the first conductive line corresponding to the second bit; or, applying the first voltage only to the first conductive line corresponding to the first bit.

[0103] In some embodiments, the method of applying an input voltage to multiple first conductive lines in a storage layer based on input data and obtaining the operation result of the input data and the matrix stored in the storage cells in the storage layer based on the output current or output voltage of the second conductive line in the storage layer includes: simultaneously applying an input voltage to the first conductive lines in two storage layers that share the second conductive line based on the input data; and obtaining the operation result of the input data and the matrix stored in the storage cells in the two storage layers based on the output current or output voltage of the second conductive line.

[0104] The features disclosed in several device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new device embodiments.

[0105] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The method comprises at least one storage layer and a peripheral circuit coupled to the storage layer; wherein, Each of the storage layers comprises a plurality of storage units, a plurality of first conductive lines and a plurality of second conductive lines; the storage units are located between the first conductive lines and the second conductive lines in a first direction; a plurality of storage units arranged along a second direction are coupled to a first conductive line, and a plurality of storage units arranged along a third direction are coupled to a second conductive line; the second direction intersects the third direction and is perpendicular to the first direction; the plurality of storage units are configured as a storage matrix; The peripheral circuit is configured to: apply an input voltage to the first conductive lines in the storage layer based on input data; and obtain an operation result of the input data and the matrix stored in the plurality of storage cells in the storage layer based on an output current or an output voltage of a second conductive line in the storage layer.

2. The semiconductor device according to claim 1, wherein: The memory cell has a first state and a second state; a threshold voltage of the memory cell in the first state is less than a threshold voltage of the memory cell in the second state and greater than a subthreshold voltage of the memory cell; The input voltage applied to one of the first conductive lines includes a first voltage and a second voltage; the first voltage is greater than a subthreshold voltage of the memory cell and less than a threshold voltage of the memory cell in the second state; the second voltage is less than the subthreshold voltage of the memory cell; The memory cell coupled to the first conductive line to which the first voltage is applied and in the first state is configured to: output a first current or a first output voltage; The memory cell coupled to the first conductive line to which the first voltage is applied and in the second state is configured to: output a second current or a second output voltage; The second current is smaller than the first current, and the second output voltage is smaller than the first output voltage.

3. The semiconductor device according to claim 2, characterized in that The peripheral circuit includes an input circuit and a counting circuit; wherein, The input circuit is connected to the first conductive line and is configured to: apply the input voltage to the plurality of first conductive lines respectively in multiple times based on the input data, and apply the input voltage to one first conductive line each time; The counting circuit is connected to the second conductive line and is configured to: count the number of times the output current of each second conductive line is greater than a preset current to obtain a calculation result of the input data and the matrix, wherein the preset current is greater than the second current and less than the first current; or count the number of times the output voltage of each second conductive line is greater than a preset voltage to obtain a calculation result of the input data and the matrix, wherein the preset voltage is greater than the second output voltage and less than the first output voltage.

4. The semiconductor device according to claim 2, characterized in that The peripheral circuit includes an input circuit and a calculation circuit; wherein, The input circuit is connected to the first conductive line and is configured to: simultaneously apply the input voltage to a plurality of the first conductive lines in the storage layer based on the input data; The calculation circuit is connected to the second conductive wires and is configured to: round the output current of each second conductive wire relative to a multiple of the first current to obtain an operation result of the input data and the matrix; or round the output voltage of each second conductive wire relative to a multiple of the first output voltage to obtain an operation result of the input data and the matrix.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: The first voltage is less than a threshold voltage of the memory cell in the first state.

6. The semiconductor device according to claim 1, wherein: The peripheral circuit is configured as: Before applying an input voltage to the first conductive lines in the storage layer based on input data, memory cells in the storage layer are programmed to a first state or a second state based on the matrix to write the matrix into the memory cells.

7. The semiconductor device according to claim 1, wherein: The input data includes a first bit and a second bit, and a value of the first bit is different from a value of the second bit; The input circuit is configured to: apply a first voltage to the first conductive line corresponding to the first bit, and apply a second voltage to the first conductive line corresponding to the second bit; or, The input circuit is configured to apply the first voltage only to the first conductive line corresponding to the first bit.

8. The semiconductor device according to claim 1, wherein: The semiconductor device includes two storage layers stacked and arranged along the first direction and sharing the second conductive line; the peripheral circuit is configured as follows: Simultaneously applying an input voltage to the first conductive lines of the two storage layers based on the input data; The operation result of the input data and the matrix stored in the plurality of storage units in the two storage layers is obtained based on the output current or the output voltage of the second conductive line.

9. The semiconductor device according to claim 1, wherein: The storage unit includes a gating element and a phase change element stacked and arranged along the first direction; the gating element is located between the first conductive line and the phase change element.

10. A semiconductor system, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 9; The controller is coupled to at least one of the semiconductor devices and is configured to send input data to the semiconductor device and receive operation results of the semiconductor device.

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