Miniature low-sensitivity double-sided heat dissipation type semiconductor power discrete device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor devices, and discloses a miniature low-sensitivity double-sided heat dissipation type semiconductor power discrete device and a preparation method thereof.The miniature low-sensitivity double-sided heat dissipation type semiconductor power discrete device comprises a TEC substrate, a chip, a plurality of molybdenum particles and a plastic package body, the TEC substrate comprises a heat dissipation plate, a PN junction layer and a heat collection plate, the chip is attached to the bottom of the heat collection plate, the molybdenum particles are connected with all electrodes of the chip in a welding and attaching mode, and the heat dissipation plate is connected with the heat collection plate through the plastic package body. The plastic package body wraps the TEC substrate, the chip and the molybdenum particles, and the top of the heat dissipation plate and the bottoms of the molybdenum particles are exposed; according to the structural design, active heat dissipation is achieved through the TEC substrate, meanwhile, the molybdenum particles are used for replacing traditional pins, internal leads or conducting strips are omitted, parasitic parameters are reduced, and the advantages of being good in heat dissipation performance, excellent in electrical characteristic and small in size are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a miniature low-inductive double-sided heat dissipation type semiconductor power discrete device and a preparation method thereof. Background Art

[0002] The structure of traditional power discrete devices is as follows Fig.14 As shown, it includes a heat sink 1', a chip 2', a conductive sheet 3' or welding wires, pins 4' and a plastic package (not shown in the figure). The chip 2' is mounted on the heat sink 1' and is electrically connected to the pins 4' through the conductive sheet 3' or welding wires; wherein the heat sink 1' is usually a simple plate structure (such as a copper plate, a copper-clad ceramic plate, etc.).

[0003] When this type of power discrete device is working, heat is generated from the inside of the chip 2'. Relying on the characteristics of heat conduction from high temperature to low temperature, the heat is diffused to the heat sink 1', and then dissipated from the heat sink 1' to the external heat dissipation structure. This heat dissipation method completely relies on passive heat dissipation by contact heat conduction, which is limited by the specific heat capacity of the heat sink 1' in the device. When the heat fills the heat sink 1' in the device, the internal heat will form a thermal equilibrium with the external heat, limiting the continuous dissipation of heat, resulting in poor heat dissipation performance.

[0004] In addition, due to the existence of the pin 4' and the conductive sheet 3' or bonding wire between the pin 4' and the chip 2', parasitic parameters such as parasitic inductance, parasitic resistance, and parasitic capacitance will be generated. These parasitic parameters will cause problems such as reduced device stability, increased power consumption, noise interference, and reduced switching speed.

[0005] The power discrete devices in the prior art also have the disadvantages of large size, low heat dissipation efficiency, poor electrical performance, etc. As electronic products develop towards miniaturization and high performance, the requirements for the heat dissipation performance, electrical characteristics and size of power discrete devices are getting higher and higher.

[0006] In view of the above problems, the existing technology needs to be improved urgently. Summary of the invention

[0007] The purpose of the present application is to provide a miniature low-inductive double-sided heat dissipation type semiconductor power discrete device and a preparation method thereof, which has the advantages of good heat dissipation performance, excellent electrical characteristics and small size.

[0008] In a first aspect, the present application provides a miniature low-inductance double-sided heat dissipation semiconductor power discrete device, comprising: A TEC substrate, wherein the TEC substrate comprises a heat sink, a PN junction layer and a heat collecting plate stacked in sequence from top to bottom; a first copper cladding layer is provided on the lower surface of the heat collecting plate; a positive electrode pad and a negative electrode pad are also provided downwardly on the TEC substrate, and the positive electrode pad and the negative electrode pad are electrically connected to the positive and negative current input terminals of the PN junction layer respectively; A chip, wherein the chip is mounted on the bottom of the heat collecting plate, a drain is arranged on the top of the chip, a gate, a Kelvin source and a source are arranged on the bottom of the chip, and the drain is connected to the first copper cladding layer by welding; A plurality of molybdenum particles, including gate molybdenum particles connected to the gate welding paste, Kelvin source molybdenum particles connected to the Kelvin source welding paste, source molybdenum particles connected to the source welding paste, drain molybdenum particles connected to the first copper clad layer welding paste, positive electrode molybdenum particles connected to the positive electrode welding pad welding paste, and negative electrode molybdenum particles connected to the negative electrode welding pad welding paste; the molybdenum particles are used to be electrically connected to an external circuit; A plastic package body is provided, wherein the plastic package body wraps the TEC substrate, the chip and the molybdenum particles, and the top of the heat sink and the bottom of each of the molybdenum particles are exposed.

[0009] This structural design achieves active heat dissipation through the TEC substrate, while using molybdenum particles to replace traditional pins and eliminating internal leads or conductive sheets, reducing parasitic parameters. It has the advantages of good heat dissipation performance, excellent electrical characteristics and small size.

[0010] Preferably, the chip is a silicon carbide MOSFET chip.

[0011] Silicon carbide MOSFET chips can work stably at higher temperatures, which complements the device's double-sided heat dissipation design and further improves heat dissipation efficiency. At the same time, silicon carbide MOSFET chips have faster switching speeds and lower switching losses, which helps reduce the overall power consumption of the device and improve energy conversion efficiency. In addition, the breakdown voltage of silicon carbide MOSFET chips is higher, allowing the device to withstand higher operating voltages and expand its application range.

[0012] Preferably, the positive electrode pad is arranged on the lower surface of the heat dissipation plate or the lower surface of the heat collecting plate; the negative electrode pad is arranged on the lower surface of the heat dissipation plate or the lower surface of the heat collecting plate.

[0013] Preferably, one side of the heat dissipation plate extends out of the range of the heat collecting plate, and the positive electrode pad and the negative electrode pad are arranged on the lower surface of the portion of the heat dissipation plate extending out of the range of the heat collecting plate.

[0014] This arrangement provides additional installation space for the positive and negative pads by extending one side of the heat sink beyond the range of the heat collector. Placing these two pads on the lower surface of the extended portion of the heat sink can effectively utilize the space of the device without affecting the installation and heat dissipation of the chip. This design solves the problem of arranging pads in a limited space, so that the positive and negative pads can be easily connected to the external circuit without interfering with the installation and function of the chip. In addition, since the positive and negative pads are located in the extended portion of the heat sink, they are kept at a certain distance from the chip, which can reduce electromagnetic interference and improve the overall performance of the device.

[0015] Preferably, the gate electrode and the gate platinum particle are each provided with one, the Kelvin source electrode and the Kelvin source platinum particle are each provided with two, the source electrode and the source platinum particle are each provided with two, and the drain electrode platinum particle is provided with two; the center of the gate electrode and the center of the gate platinum particle are located on a symmetry plane perpendicular to the bottom surface of the chip, and the two Kelvin source electrodes, the two Kelvin source platinum particles, the two source electrodes, the two source platinum particles, the two drain electrode platinum particles, and the positive electrode platinum particles and the negative electrode platinum particles are all symmetrically arranged about the symmetry plane.

[0016] Preferably, a second copper cladding layer is provided on the top of the heat sink; and a third copper cladding layer is provided on the bottom of each of the molybdenum particles.

[0017] Preferably, the chip occupies more than 95% of the area of ​​the bottom of the heat collecting plate.

[0018] In a second aspect, the present application provides a preparation method for preparing the aforementioned miniature low-inductance double-sided heat dissipation semiconductor power discrete device, comprising the steps of: A1. Place the TEC substrate with the top surface facing down into the positioning fixture; A2. stacking a first solder sheet on the first copper-clad layer on the bottom surface of the TEC substrate; A3. Place the top of the chip face down on the first solder pad, so that the drain electrode at the top of the chip contacts the first solder pad, and the first solder pad is partially exposed outside the chip; A4. A second solder sheet is stacked on the gate, Kelvin source and source at the bottom of the chip and on the positive pad and negative pad of the TEC substrate; A5. stacking corresponding molybdenum particles on each of the second soldering sheets and at a position where the first soldering sheet is exposed outside the chip to obtain a first semi-finished product; A6. While applying pressure downward to the first semi-finished product, the first semi-finished product is reflowed using a vacuum reflow technique to obtain a second semi-finished product; A7. Plastic-sealing the second semi-finished product to obtain a finished product; A8. Test taping and packaging of the finished products.

[0019] Preferably, step A6 comprises: superimposing an auxiliary counterweight on the first semi-finished product to apply pressure to the first semi-finished product; The auxiliary counterweight, the first semi-finished product and the positioning fixture are sent together into a vacuum reflow soldering device for reflow soldering to obtain a second semi-finished product.

[0020] Preferably, step A7 comprises: Plastic-sealing the second semi-finished product so that the plastic-sealed body completely covers the second semi-finished product; Etching the plastic package on the top of the second semi-finished product to expose the top of the TEC substrate; The plastic sealing body at the bottom of the second semi-finished product is etched to expose the bottom of each of the molybdenum particles.

[0021] Beneficial effects: The miniature low-inductive double-sided heat dissipation semiconductor power discrete device and preparation method provided in the present application include a TEC substrate, a chip, multiple molybdenum particles and a plastic package, wherein the TEC substrate includes a heat sink, a PN junction layer and a heat collecting plate, the chip is mounted on the bottom of the heat collecting plate, multiple molybdenum particles are welded to each electrode of the chip, the plastic package wraps the TEC substrate, the chip and the molybdenum particles, and the top of the heat sink and the bottom of the molybdenum particles are exposed; this structural design realizes active heat dissipation through the TEC substrate, and at the same time uses molybdenum particles to replace traditional pins and eliminates internal leads or conductive sheets, thereby reducing parasitic parameters, and has the advantages of good heat dissipation performance, excellent electrical characteristics and small size. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A cross-sectional view of a miniature low-inductance double-sided heat dissipation semiconductor power discrete device provided in an embodiment of the present application.

[0023] Figure 2 A three-dimensional diagram of the upright state of the miniature low-inductance double-sided heat dissipation semiconductor power discrete device provided in an embodiment of the present application.

[0024] Figure 3 A three-dimensional diagram of an inverted state of a miniature low-inductance double-sided heat dissipation semiconductor power discrete device provided in an embodiment of the present application.

[0025] Figure 4 A three-dimensional diagram of the internal structure of a miniature low-inductance double-sided heat dissipation semiconductor power discrete device provided in an embodiment of the present application.

[0026] Figure 5 A side view of the internal structure of a miniature low-inductance double-sided heat dissipation semiconductor power discrete device provided in an embodiment of the present application.

[0027] Figure 6 A flow chart of the preparation method provided in the embodiments of the present application.

[0028] Figure 7 This is the state diagram of the TEC substrate before it is placed in the positioning fixture.

[0029] Figure 8 This is the state diagram after the TEC substrate is placed in the positioning fixture.

[0030] Fig. 9 This is a diagram of the state after stacking the first welding sheet.

[0031] Fig.10 This is the state diagram after stacking chips.

[0032] Fig.11 This is a diagram of the state after stacking the second welding sheet.

[0033] Fig.12 This is the state diagram after superimposing molybdenum particles.

[0034] Fig.13 This is a diagram of the state after stacking the auxiliary counterweights.

[0035] Fig.14 It is a schematic diagram of the structure of an existing power discrete device.

[0036] Explanation of reference numerals: 1. TEC substrate; 101. heat sink; 102. PN junction layer; 103. heat collecting plate; 104. first copper clad layer; 105. second copper clad layer; 2. chip; 201. gate; 202. Kelvin source; 203. source; 3. molybdenum particles; 301. gate molybdenum particles; 302. Kelvin source molybdenum particles; 303. source molybdenum particles; 304. drain molybdenum particles; 305. positive electrode molybdenum particles; 306. negative electrode molybdenum particles; 307. third copper clad layer; 4. plastic package; 5. first welding piece; 6. second welding piece; 90. positioning fixture; 91. positioning groove; 92. auxiliary counterweight. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0038] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0039] In power discrete devices, heat dissipation and parasitic parameters are key factors affecting their performance and reliability. Traditional power discrete devices use passive heat dissipation, relying on the natural conduction of heat from the chip to the heat sink. However, this method is limited by the specific heat capacity of the heat sink. When the heat sink is saturated, the internal and external heat reaches a balance, limiting the continuous heat dissipation capability. In addition, the pins, conductive sheets or wires used in traditional designs introduce significant parasitic parameters, including parasitic inductance, resistance and capacitance, which negatively affect the stability, power consumption, noise characteristics and switching speed of the device.

[0040] When faced with the problem of heat dissipation performance and parasitic parameters of power discrete devices, several possible solutions were considered. One idea is to improve the traditional passive heat dissipation structure by increasing the surface area of ​​the heat sink or using materials with higher thermal conductivity to improve the heat dissipation efficiency. However, although this method can improve the heat dissipation performance to a certain extent, it is still limited by the inherent defects of passive heat dissipation and cannot completely solve the heat dissipation problem in high power density applications. Another idea is to introduce a liquid cooling system and use circulating liquid to quickly remove heat. This method can significantly improve the heat dissipation efficiency, but it will greatly increase the complexity and cost of the system, and may also introduce new reliability issues. In response to the problem of parasitic parameters, methods of optimizing circuit layout and reducing the length of connecting wires were considered. However, this method has limited room for improvement under the traditional packaging structure and is difficult to meet the needs of high-frequency and high-power applications.

[0041] In order to solve the two key problems of heat dissipation and parasitic parameters at the same time, the present application proposes a miniature low-inductance double-sided heat dissipation type semiconductor power discrete device solution.

[0042] Please refer to Figure 1-Figure 5 In some embodiments of the present application, a miniature low-inductance double-sided heat dissipation semiconductor power discrete device includes: A TEC substrate 1 (i.e., a thermoelectric cooling substrate), the TEC substrate 1 comprises a heat sink 101, a PN junction layer 102, and a heat collecting plate 103 stacked in sequence from top to bottom; a first copper cladding layer 104 is provided on the lower surface of the heat collecting plate 103; a positive electrode pad and a negative electrode pad are also provided downward on the TEC substrate 1, and the positive electrode pad and the negative electrode pad are electrically connected to the positive and negative current input terminals of the PN junction layer 102, respectively; Chip 2 is mounted on the bottom of the heat collecting plate 103. The top of chip 2 is provided with a drain electrode, and the bottom of chip 2 is provided with a gate electrode 201, a Kelvin source electrode 202 and a source electrode 203 (such as Fig.10 As shown), the drain electrode is connected with the first copper cladding layer 104 by welding; A plurality of molybdenum particles 3, including a gate molybdenum particle 301 connected to the gate 201 solder paste, a Kelvin source molybdenum particle 302 connected to the Kelvin source 202 solder paste, a source molybdenum particle 303 connected to the source 203 solder paste, a drain molybdenum particle 304 connected to the first copper clad layer 104 solder paste, a positive electrode molybdenum particle 305 connected to the positive electrode pad solder paste, and a negative electrode molybdenum particle 306 connected to the negative electrode pad solder paste; the molybdenum particles 3 are used to be electrically connected to an external circuit; The plastic package 4 wraps the TEC substrate 1, the chip 2 and the molybdenum particles 3, and the top of the heat sink 101 and the bottom of each molybdenum particle 3 are exposed.

[0043] This structural design realizes active heat dissipation through the TEC substrate 1, and uses molybdenum particles 3 to replace traditional pins and eliminates internal leads or conductive sheets, thereby reducing parasitic parameters and having the advantages of good heat dissipation performance, excellent electrical characteristics and small size.

[0044] It should be noted that the up and down directions in this application are based on Figure 1 The placement direction is based on (therefore the description of top and bottom is also based on Figure 1 The direction of placement is based on the above), which is only for the convenience of description and is not a limitation on the direction in actual use. When in use, the exposed side of the molybdenum particle 3 can be mounted on the PCBA circuit board (so that no additional leads are required for circuit connection), and a heat sink can be mounted on the exposed side of the heat sink 101. Another heat sink can be further mounted on the side of the PCBA circuit board that is away from the miniature low-inductive double-sided heat dissipation type semiconductor power discrete device to further improve the heat dissipation effect; however, the installation method of the miniature low-inductive double-sided heat dissipation type semiconductor power discrete device is not limited to this.

[0045] Among them, the TEC substrate 1 is one of the core components of the solution. The PN junction layer 102 generates a temperature difference through current input, and actively transfers heat from the heat collector 103 to the heat sink 101. This structure can adjust the heat dissipation efficiency according to actual needs, such as increasing the current input during high-power operation to improve the heat dissipation capacity. The heat sink 101 and the heat collector 103 can use ceramic materials with moderate thermal conductivity but good insulation performance. The chip 2 is directly mounted on the bottom of the heat collector 103. This design eliminates the thermal interface material between the chip 2 and the heat sink in the traditional package, greatly reducing the thermal resistance. The drain is set on the top of the chip 2, and the gate 201, Kelvin source 202 and source 203 are set on the bottom. This layout can optimize the current distribution and reduce the hot spots inside the chip 2.

[0046] Among them, the application of molybdenum particles 3 is another key innovation. Multiple molybdenum particles 3 are used to replace traditional pins and leads, including gate molybdenum particles 301, Kelvin source molybdenum particles 302, source molybdenum particles 303, drain molybdenum particles 304, positive molybdenum particles 305 and negative molybdenum particles 306. The molybdenum particles 3 are directly connected to the electrode solder pastes of the chip 2, which significantly shortens the current path. Molybdenum has excellent electrical conductivity and can effectively reduce resistance losses. At the same time, the size and shape of the molybdenum particles 3 can be precisely controlled, which helps to reduce parasitic inductance. Generally, the length and width of the molybdenum particles 3 are the same as the length and width of the corresponding electrodes or pads (for the drain molybdenum particles 304, the length and width can be adjusted according to the space size of the first copper-clad layer 104 for the drain molybdenum particles 304 to connect). For thickness, the thickness of the molybdenum particles 3 can be controlled within the range of 1mm-5mm, which can not only achieve electrical connection and reduce parasitic parameters, but also act as a heat sink to help the chip 2 dissipate heat.

[0047] The first copper clad layer 104 disposed on the lower surface of the heat collecting plate 103 plays a dual role: on the one hand, it improves the efficiency of heat conduction, and on the other hand, it serves as a medium for electrical connection. The thickness of the first copper clad layer 104 can be adjusted as needed, preferably greater than 200μm. The plastic package 4 wraps the TEC substrate 1, chip 2 and molybdenum particles 3, but the top of the heat sink 101 and the bottom of each molybdenum particle 3 are exposed. This design achieves double-sided heat dissipation and greatly increases the heat dissipation area. The exposed heat sink 101 can directly contact the external heat dissipation system, and the exposed molybdenum particles 3 are not only convenient for electrical connection, but also can serve as additional heat dissipation channels.

[0048] There is a close relationship and interaction between these features. The TEC substrate 1 provides the basis for active heat dissipation for the entire structure, and the chip 2 is directly mounted on the heat collector 103 to maximize the heat transfer efficiency. The application of molybdenum particles 3 not only reduces parasitic parameters, but also provides the possibility of double-sided heat dissipation. The first copper cladding layer 104 acts as a bridge between heat conduction and electrical connection.

[0049] Among them, a plurality of P-type semiconductor components and N-type semiconductor components are arranged in the PN junction layer 102, and these P-type semiconductor components and N-type semiconductor components are alternately connected in series in sequence to form a plurality of PN junctions connected in series. Preferably, these semiconductor components are arranged in a serpentine manner (such as an S-shaped arrangement or a serpentine arrangement, etc.) to form more PN junctions in a certain space to improve heat dissipation efficiency.

[0050] The type of chip 2 can be selected according to actual needs. Preferably, chip 2 is a silicon carbide MOSFET chip.

[0051] The use of silicon carbide MOSFET chips as the core components of micro-low-inductive double-sided heat dissipation semiconductor power discrete devices has many advantages. Silicon carbide materials have the characteristics of wide bandgap, high breakdown electric field, high thermal conductivity, etc., which makes silicon carbide-based MOSFET chips perform well in high-temperature, high-frequency, and high-voltage applications. Specifically, silicon carbide MOSFET chips can work stably at higher temperatures, which complements the double-sided heat dissipation design of the device and further improves the heat dissipation efficiency. At the same time, silicon carbide MOSFET chips have faster switching speeds and lower switching losses, which helps to reduce the overall power consumption of the device and improve energy conversion efficiency. In addition, the breakdown voltage of silicon carbide MOSFET chips is higher, which enables the device to withstand higher operating voltages and expands the scope of application. The use of silicon carbide MOSFET chips, combined with the double-sided heat dissipation structure of the TEC substrate 1, the low-inductive design of multiple molybdenum particles 3, and the protection of the plastic package 4, together constitutes a micro-low-inductive double-sided heat dissipation semiconductor power discrete device with excellent performance. This design not only improves the power density and reliability of the device, but also reduces parasitic inductance and improves the switching characteristics of the device, making it have significant advantages in high-frequency, high-temperature, and high-voltage applications.

[0052] Among them, the performance and size of chip 2 can be set according to actual needs. For example, a silicon carbide MOSFET chip with a rated voltage of 650V, an on-resistance of 32mΩ, and a size of 3.1mm*2.3mm is selected (selecting this chip 2 can prepare a miniature low-inductance double-sided heat dissipation semiconductor power discrete device with a size of 3.3mm*2.5mm), but it is not limited to this.

[0053] The positive electrode pad is arranged on the lower surface of the heat dissipation plate 101 or the lower surface of the heat collecting plate 103 ; the negative electrode pad is arranged on the lower surface of the heat dissipation plate 101 or the lower surface of the heat collecting plate 103 .

[0054] By arranging the positive electrode pad and the negative electrode pad on the lower surface of the heat sink 101 or the lower surface of the heat collecting plate 103, the structural characteristics of the TEC substrate 1 can be fully utilized to optimize the electrical and thermal performance, providing a new idea for the development of high-performance semiconductor power devices.

[0055] In the present application, the positive electrode pad and the negative electrode pad can be arranged in a variety of ways. One way is to arrange both pads on the lower surface of the heat sink 101, another way is to arrange both pads on the lower surface of the heat collector 103, and the positive electrode pad can also be arranged on the lower surface of the heat sink 101 and the negative electrode pad can be arranged on the lower surface of the heat collector 103, or vice versa. These different arrangement methods can be selected according to the specific device structure and application requirements.

[0056] In some preferred embodiments, see Figure 4 , Figure 5One side of the heat sink 101 extends out of the range of the heat collecting plate 103 , and the positive electrode pad and the negative electrode pad are arranged on the lower surface of the portion of the heat sink 101 extending out of the range of the heat collecting plate 103 .

[0057] This arrangement provides additional installation space for the positive electrode pad and the negative electrode pad by extending one side of the heat sink 101 beyond the range of the heat collecting plate 103. The two pads are arranged on the lower surface of the extended portion of the heat sink 101, which can effectively utilize the space of the device without affecting the installation and heat dissipation effect of the chip 2. This design solves the problem of arranging pads in a limited space, so that the positive electrode pad and the negative electrode pad can be conveniently connected to the external circuit without interfering with the installation and function of the chip 2. In addition, since the positive electrode pad and the negative electrode pad are located in the extended portion of the heat sink 101, they maintain a certain distance from the chip 2, which can reduce electromagnetic interference and improve the overall performance of the device.

[0058] This design cooperates with the layout of the TEC substrate 1, chip 2 and molybdenum particles 3 to form a compact and efficient structure. The extension of the heat sink 101 not only provides installation space for the pads, but also increases the heat dissipation area and improves the overall heat dissipation efficiency. At the same time, since the positive and negative pads are located in the extended part of the heat sink 101, the distance between them and the chip 2 is optimized, which helps to reduce parasitic inductance and improve the switching speed of the device.

[0059] In practical applications, this layout enables the miniature low-inductive double-sided heat dissipation semiconductor power discrete device to better adapt to various complex circuit environments. The location of the positive pad and the negative pad is convenient for connection with the external circuit without interfering with the normal operation of the chip 2. This design also improves the reliability of the device because the appropriate distance between the positive pad and the negative pad and the chip 2 can reduce the impact of thermal stress on the connection.

[0060] The number and layout of the gate 201, Kelvin source 202 and source 203 on the chip 2 and the corresponding molybdenum particles 3 can be adjusted according to actual needs, and the number and layout of the drain molybdenum particles 304 can also be adjusted according to actual needs.

[0061] In one possible implementation, see Figure 4 , Fig.10, the gate 201 and the gate molybdenum particle 301 are each provided with one, the Kelvin source 202 and the Kelvin source molybdenum particle 302 are each provided with two, the source 203 and the source molybdenum particle 303 are each provided with two, and the drain molybdenum particle 304 is provided with two; the center of the gate 201 and the center of the gate molybdenum particle 301 are located on a symmetry plane perpendicular to the bottom surface of the chip 2, and the two Kelvin source electrodes 202, the two Kelvin source molybdenum particles 302, the two source electrodes 203, the two source molybdenum particles 303, the two drain molybdenum particles 304, and the positive electrode molybdenum particles 305 and the negative electrode molybdenum particles 306 are all symmetrically arranged about the symmetry plane.

[0062] This layout design achieves the symmetry of the device structure by precisely controlling the number and position of each electrode and platinum particle 3. The center of the gate 201 and the gate platinum particle 301 is located on the symmetry plane, ensuring the uniform distribution of the gate signal. The symmetrical arrangement of the two Kelvin source electrodes 202, the source electrode 203 and the corresponding platinum particles 3 helps to reduce the parasitic inductance and improve the switching speed of the device. The symmetrical arrangement of the two drain platinum particles 304 is conducive to uniform heat dissipation and current distribution. The symmetrical arrangement of the positive platinum particles 305 and the negative platinum particles 306 helps to reduce the parasitic inductance of the device and improve the electrical performance. Through this symmetrical layout, the technical solution effectively solves the problems of uneven current distribution, uneven heat dissipation and large parasitic inductance inside the device. The symmetrical structure makes the current and heat more evenly distributed inside the device, reduces the generation of local hot spots, and improves the heat dissipation efficiency of the device. At the same time, the symmetrical layout also helps to reduce the parasitic inductance of the device, improve the switching speed and overall electrical performance. This design not only optimizes the electrical characteristics of the device, but also improves its reliability and service life, making this miniature low-inductance double-sided heat dissipation semiconductor power discrete device have better performance in high-frequency, high-power applications.

[0063] Further, see Figure 4 , Fig.10 The molybdenum particles 3 and the corresponding electrodes or pads located on one side of the above-mentioned symmetry plane are arranged in sequence along a straight line direction parallel to the symmetry plane, and the molybdenum particles 3 and the corresponding electrodes or pads located on the other side of the above-mentioned symmetry plane are arranged in sequence along another straight line direction parallel to the symmetry plane; thereby, it is more conducive to improving the compactness of the structure and reducing the size of the product.

[0064] It should be noted that the bottom surfaces of all the molybdenum particles 3 are flush (in the same plane) to ensure that each molybdenum particle 3 can be reliably attached to the PCBA circuit board during use to achieve good electrical connection.

[0065] Preferably, see Figure 1 A second copper cladding layer 105 is disposed on the top of the heat sink 101 ; a third copper cladding layer 307 is disposed on the bottom of each molybdenum particle 3 .

[0066] The second copper clad layer 105 and the third copper clad layer 307 are provided to facilitate solder connection with external devices (heat sink or PCBA circuit board), improve connection reliability, and also achieve better heat conduction and electrical connection. The thickness of the second copper clad layer 105 and the third copper clad layer 307 can be adjusted as needed, preferably greater than 200 μm.

[0067] In practical applications, the heat dissipation efficiency of the TEC substrate 1 is positively correlated with the contact area between the chip 2 and the TEC substrate 1. The larger the contact area, the higher the heat dissipation efficiency. Therefore, the area of ​​the chip 2 at the bottom of the heat collecting plate 103 preferably accounts for more than 95%.

[0068] By setting the area ratio of chip 2 at the bottom of the heat collecting plate 103 to more than 95%, the heat dissipation area of ​​the heat collecting plate 103 is fully utilized. This design can significantly improve the heat dissipation efficiency of chip 2, because the larger the contact area between chip 2 and the heat collecting plate 103, the better the heat conduction effect. At the same time, this design also helps to achieve the miniaturization of the device. Since chip 2 occupies almost the entire area of ​​the bottom of the heat collecting plate 103, unnecessary space waste is reduced, making the size of the entire device more compact. In addition, the large area contact between chip 2 and the heat collecting plate 103 may also bring other benefits, such as reducing thermal resistance, improving device reliability and service life. This design fully considers the balance between heat dissipation requirements and space utilization, and is an optimized solution. Compared with traditional designs, this high-proportion layout method may have significant improvements in heat dissipation efficiency and space utilization, reflecting the innovativeness and practical value of this technical solution.

[0069] Since the area ratio of chip 2 at the bottom of the heat collecting plate 103 is set to be more than 95%, the size of chip 2 is not much different from the size of the packaged product, and the area ratio of chip 2 is also almost the same as that of WLCSP packaging (i.e., wafer-level chip packaging), but compared with WLCSP packaging, the process is simpler and the cost is lower; and the product of the present application can achieve double-sided heat dissipation, greatly improving the heat dissipation capacity, and combined with the use of silicon carbide MOSFET chips, it provides very important support for the realization of ultra-high power density.

[0070] The connection between the chip 2 and the heat collecting plate 103 and between each molybdenum particle 3 and the corresponding electrode (or pad, or first copper clad layer 104) can be achieved in a variety of ways, such as welding, crimping or conductive adhesive bonding.

[0071] In some preferred embodiments, the connection is performed by welding with a welding sheet, which is conducive to ensuring the consistency of the height of the bottom surface of each molybdenum particle 3 and ensuring that the bottom surface of each molybdenum particle 3 is in the same plane. Figure 1 , Figure 5In the embodiment, the chip 2 and the first copper-clad layer 104 at the bottom of the heat collecting plate 103 and the drain molybdenum particles 304 and the first copper-clad layer 104 are welded and connected by the same first welding piece 5, and the other molybdenum particles 3 are each welded and connected to the corresponding electrode or pad by the corresponding second welding piece 6. The material of the first welding piece 5 and the second welding piece 6 is preferably tin or silver.

[0072] refer to Figure 6 The present application provides a preparation method for preparing the aforementioned miniature low-inductance double-sided heat dissipation semiconductor power discrete device, comprising the steps of: A1. Place the TEC substrate 1 with the top surface facing downward into the positioning fixture 90 (eg Figure 7 , Figure 8 shown); A2. A first solder sheet 5 is stacked on the first copper-clad layer 104 on the bottom surface of the TEC substrate 1 (eg Fig. 9 shown); A3. Place the chip 2 with the top facing downward on the first solder pad 5, so that the drain electrode on the top of the chip 2 is in contact with the first solder pad 5, and the first solder pad 5 is partially exposed outside the chip 2 (such as Fig.10 shown); A4. A second soldering sheet 6 is stacked on the gate 201, the Kelvin source 202 and the source 203 at the bottom of the chip 2 and on the positive and negative pads of the TEC substrate 1 (eg Fig.11 shown); A5. Overlay corresponding molybdenum particles 3 on each second soldering sheet 6 and the first soldering sheet 5 exposed outside the chip 2 to obtain a first semi-finished product (such as Fig.12 shown); A6. While applying downward pressure to the first semi-finished product, the first semi-finished product is reflowed using a vacuum reflow technology to obtain a second semi-finished product; A7. Plastic-sealing the second semi-finished product to obtain a finished product; A8. Test taping and packaging of finished products.

[0073] The preparation method manufactures a miniature low-inductive double-sided heat dissipation semiconductor power discrete device through a series of precise steps. First, the TEC substrate 1 is placed in a positioning fixture 90 to ensure the accuracy of subsequent operations. Then, electrical connections and heat conduction paths are established by stacking solder sheets and chips 2. Next, molybdenum particles 3 are placed at key positions to provide interfaces for external circuit connections. Vacuum reflow soldering technology is used for soldering, which is crucial to ensure reliable connections between components. The vacuum environment can reduce oxidation during the soldering process and improve the soldering quality. At the same time, applying pressure to the semi-finished product can ensure close contact between the components and further improve the soldering effect. Using solder sheets for soldering can better ensure the high consistency of each molybdenum particle 3 compared with using solder paste, and there is no need for vacuum sintering and post-sintering cleaning processes, which can reduce cleaning and wire bonding processes and avoid quality problems caused by these processes, greatly simplifying the process links and improving product reliability. The plastic encapsulation molding step provides protection for the device and also fixes the internal structure. The final testing and packaging steps ensure the quality and reliability of the product.

[0074] Among them, see Figure 7 The positioning jig 90 is provided with a plurality of positioning grooves 91 adapted to the TEC substrate 1. In step A1, a plurality of TEC substrates 1 are placed into the positioning grooves 91 with the top surface facing downward to achieve positioning, and multiple products can be prepared at the same time, thereby improving preparation efficiency. The positioning jig 90 can be made of precision-machined metal or ceramic material with a high degree of dimensional accuracy to ensure the position stability of the TEC substrate 1 in subsequent steps.

[0075] Preferably, step A6 comprises: The auxiliary weight 92 is stacked on the first semi-finished product to apply pressure to the first semi-finished product (such as Fig.13 shown); The auxiliary counterweight 92, the first semi-finished product and the positioning fixture 90 are sent together into a vacuum reflow soldering device for reflow soldering to obtain a second semi-finished product.

[0076] The auxiliary weight 92 is used to apply pressure to the first semi-finished product to ensure that the components are in close contact during the reflow process. The vacuum reflow device provides a vacuum environment for the welding process, which helps to reduce welding defects. These two features work together to effectively solve the key problems in the preparation process.

[0077] The auxiliary counterweight 92 can be implemented in various forms. For example, it can be a metal plate of moderate weight, which is slightly larger than the first semi-finished product to ensure uniform pressure. It can also be designed as a pressure plate with multiple protrusions, which correspond to key welding points on the first semi-finished product to achieve local pressure. In addition, a pneumatic or hydraulic device with adjustable pressure can also be used to flexibly control the pressure according to the needs of different products.

[0078] A layer of high temperature resistant, non-sticky isolation material, such as a polytetrafluoroethylene film, may be added between the auxiliary counterweight 92 and the first semi-finished product to prevent adhesion during high temperature welding.

[0079] The vacuum degree of the vacuum reflow device can be adjusted according to product requirements, usually within 1×10 -2 to 1×10 -4 Pa range. A temperature gradient can also be set inside the device to achieve more precise welding temperature control. For example, the temperature can be slowly increased from 150°C to a maximum of 320°C and then gradually cooled. The whole process may last 5 minutes to 10 minutes.

[0080] This technical solution effectively prevents the displacement or deformation of each component at high temperature through the pressure of the auxiliary counterweight 92, ensures the close contact of the welding surface, and significantly improves the welding quality. The vacuum environment greatly reduces the risk of oxidation, reduces the generation of bubbles and impurities, and further improves the welding effect. This combination not only improves the welding quality and reliability of the product, but also helps to improve the overall performance and service life of the device.

[0081] Among them, the weight of the auxiliary counterweight 92 can be adjusted according to actual needs. Since the present solution uses a welding sheet for welding, the solder will not overflow due to excessive pressure (if a solder paste is used, this situation will exist, resulting in the need for cleaning after welding, and it is difficult to control the thickness of the remaining solder, so it is difficult to ensure that the bottom surface height of each molybdenum particle 3 is consistent), so the pressure range is less restricted, as long as it does not cause damage to the structure and function of each part. For example, when the size of the chip 2 is 3.1mm*2.3mm, and the size of the finished product after plastic molding is 3.3mm*2.5mm, the weight of the auxiliary counterweight 92 can be set according to the product size and the required pressure (to ensure that the pressure on the product is the required pressure), wherein the required pressure is generally 10MPa-25MPa, which can ensure close contact of the welding surface and will not damage the structure and function of each part.

[0082] Further, step A7 includes: Plastic-sealing the second semi-finished product so that the plastic-sealed body 4 completely wraps the second semi-finished product; Etching the plastic package 4 at the top of the second semi-finished product to expose the top of the TEC substrate 1; The plastic sealing body 4 at the bottom of the second semi-finished product is etched to expose the bottom of each molybdenum particle 3.

[0083] This solution solves the problem of how to accurately control the exposed parts during the plastic encapsulation process. By completely encapsulating first and then etching, the problem of incomplete coverage or inaccurate exposed parts that may occur during direct plastic encapsulation is avoided. This method not only improves the accuracy and consistency of manufacturing, but also enhances the overall structural strength and sealing of the device. At the same time, the exposure of the top of the TEC substrate 1 is conducive to heat dissipation, and the exposure of the bottom of the molybdenum particles 3 facilitates electrical connection with the external circuit, thereby realizing the functional requirements of a miniature low-inductive double-sided heat dissipation semiconductor power discrete device.

[0084] In a specific implementation, the second semi-finished product can be encapsulated in a variety of ways. For example, the injection molding technology can be used to inject the molten encapsulation material into the mold to completely wrap the second semi-finished product. Another method is to use the compression molding technology to place the preheated encapsulation material in the mold, and then pressurize it to make it flow and wrap the second semi-finished product. Both methods can ensure that the plastic encapsulation body 4 evenly covers the entire second semi-finished product, providing a good foundation for the subsequent etching steps.

[0085] The etching process can be dry etching or wet etching. Dry etching is usually performed using plasma or ion beams, which can achieve high-precision etching effects. Wet etching uses chemical solutions, which has slightly lower precision but lower costs and is suitable for large-scale production. Regardless of which etching method is chosen, the key is to accurately control the etching depth and range to ensure that the top of the TEC substrate 1 and the bottom of the molybdenum particles 3 are just exposed without over-etching and affecting device performance.

[0086] It is worth noting that the material properties of the TEC substrate 1 and the molybdenum particles 3 need to be considered during the etching process, and appropriate etching parameters and protective measures need to be selected. For example, photoresist or other protective layers can be applied to the areas that need protection before etching to prevent over-etching. The control of the etching rate is also crucial, and usually a step-by-step etching method is used, and each etching is performed after a certain depth to ensure that the etching effect meets the requirements.

[0087] The second copper clad layer 105 and the third copper clad layer 307 may be prepared in advance on the corresponding parts, or may be prepared in step A7. In the latter case, step A7 further includes: A second copper clad layer 105 is prepared on the top of the TEC substrate 1; A third copper coating layer 307 is prepared at the bottom of each molybdenum particle 3 .

[0088] For example, the second copper clad layer 105 and the third copper clad layer 307 may be prepared by chemical vapor deposition or physical vapor deposition, but are not limited thereto.

[0089] Among them, in step A8, the existing technology can be used to test the finished product for taping and packaging, which is not limited here.

[0090] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0091] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A miniature low-inductance double-sided heat dissipation semiconductor power discrete device, characterized in that: include: A TEC substrate (1), the TEC substrate (1) comprising a heat sink (101), a PN junction layer (102) and a heat collecting plate (103) stacked in sequence from top to bottom; a first copper cladding layer (104) is provided on the lower surface of the heat collecting plate (103); a positive electrode pad and a negative electrode pad are also provided downwardly on the TEC substrate (1), the positive electrode pad and the negative electrode pad being electrically connected to the positive and negative current input terminals of the PN junction layer (102) respectively; A chip (2), the chip (2) being mounted on the bottom of the heat collecting plate (103), the top of the chip (2) being provided with a drain electrode, the bottom of the chip (2) being provided with a gate electrode (201), a Kelvin source electrode (202) and a source electrode (203), the drain electrode being connected to the first copper cladding layer (104) by soldering; A plurality of molybdenum particles (3), including a gate molybdenum particle (301) connected to the gate (201) solder paste, a Kelvin source molybdenum particle (302) connected to the Kelvin source (202) solder paste, a source molybdenum particle (303) connected to the source (203) solder paste, a drain molybdenum particle (304) connected to the first copper cladding layer (104) solder paste, a positive electrode molybdenum particle (305) connected to the positive electrode pad solder paste, and a negative electrode molybdenum particle (306) connected to the negative electrode pad solder paste; the molybdenum particles (3) are used to be electrically connected to an external circuit; A plastic packaging body (4), wherein the plastic packaging body (4) wraps the TEC substrate (1), the chip (2) and the molybdenum particles (3), and the top of the heat sink (101) and the bottom of each of the molybdenum particles (3) are exposed.

2. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The chip (2) is a silicon carbide MOSFET chip.

3. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The positive electrode welding pad is arranged on the lower surface of the heat dissipation plate (101) or the lower surface of the heat collecting plate (103); and the negative electrode welding pad is arranged on the lower surface of the heat dissipation plate (101) or the lower surface of the heat collecting plate (103).

4. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 3, characterized in that: One side of the heat dissipation plate (101) extends out of the range of the heat collecting plate (103), and the positive electrode pad and the negative electrode pad are arranged on the lower surface of the portion of the heat dissipation plate (101) extending out of the range of the heat collecting plate (103).

5. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The gate electrode (201) and the gate electrode platinum particle (301) are each provided with one, the Kelvin source electrode (202) and the Kelvin source electrode platinum particle (302) are each provided with two, the source electrode (203) and the source electrode platinum particle (303) are each provided with two, and the drain electrode platinum particle (304) is provided with two; the center of the gate electrode (201) and the center of the gate electrode platinum particle (301) are located on a symmetric plane perpendicular to the bottom surface of the chip (2); the two Kelvin source electrodes (202), the two Kelvin source electrode platinum particles (302), the two source electrodes (203), the two source electrode platinum particles (303), the two drain electrode platinum particles (304), and the positive electrode platinum particles (305) and the negative electrode platinum particles (306) are all symmetrically arranged about the symmetric plane.

6. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: A second copper-clad layer (105) is provided on the top of the heat dissipation plate (101); and a third copper-clad layer (307) is provided on the bottom of each of the molybdenum particles (3).

7. The miniature low-inductance double-sided heat dissipation semiconductor power discrete device according to claim 1, characterized in that: The chip (2) accounts for more than 95% of the area of ​​the bottom of the heat collecting plate (103).

8. A preparation method, characterized in that: The method for preparing the miniature low-inductive double-sided heat dissipation semiconductor power discrete device according to any one of claims 1 to 7 comprises the following steps: A1. Place the TEC substrate (1) with the top surface facing downward into the positioning fixture (90); A2. stacking a first solder sheet (5) on the first copper-clad layer (104) on the bottom surface of the TEC substrate (1); A3. stacking the chip (2) with the top facing downward on the first soldering pad (5), so that the drain electrode on the top of the chip (2) contacts the first soldering pad (5), and the first soldering pad (5) is partially exposed outside the range of the chip (2); A4. stacking a second soldering sheet (6) on the gate (201), the Kelvin source (202) and the source (203) at the bottom of the chip (2) and on the positive electrode pad and the negative electrode pad of the TEC substrate (1); A5. stacking corresponding molybdenum particles (3) on each of the second soldering sheets (6) and at positions of the first soldering sheets (5) protruding outside the range of the chip (2) to obtain a first semi-finished product; A6. While applying pressure downward to the first semi-finished product, the first semi-finished product is reflowed using a vacuum reflow technique to obtain a second semi-finished product; A7. Plastic-sealing the second semi-finished product to obtain a finished product; A8. Test taping and packaging of the finished products.

9. The preparation method according to claim 8, characterized in that: Step A6 includes: superimposing an auxiliary counterweight (92) on the first semi-finished product to apply pressure to the first semi-finished product; The auxiliary counterweight (92), the first semi-finished product and the positioning jig (90) are sent together into a vacuum reflow soldering device for reflow soldering to obtain a second semi-finished product.

10. The preparation method according to claim 8, characterized in that: Step A7 includes: Plastic-sealing the second semi-finished product so that the plastic-sealed body (4) completely wraps the second semi-finished product; Etching the plastic packaging body (4) at the top of the second semi-finished product so that the top of the TEC substrate (1) is exposed; The plastic sealing body (4) at the bottom of the second semi-finished product is etched to expose the bottom of each of the molybdenum particles (3).

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