Level shift circuit for switching converter
By designing voltage sampling modules and level down shift modules in switch converters, using components such as PMOS and NMOS tubes, efficient level shifting is achieved, and the speed and power consumption of existing level down shift circuits in high-voltage environments is solved. The disadvantages in this paper realize high-speed, low-power consumption and anti-interference level conversion.
Patent Information
- Application Number
- CN202411662230.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-20
- Publication Date
- 2025-01-03
AI Technical Summary
The existing level down shift circuits are difficult to achieve high-speed, low-power and anti-interference conversion from high-voltage domain to low-voltage domain in high-voltage environments, and the integration and cost are low.
A level displacement circuit including a voltage sampling module and a level down shift module is designed. Through the sampling input unit, a speed-up unit, a voltage limiting unit, an anti-interference unit and a level output unit, PMOS and NMOS tubes and voltage buffers are used. , capacitors and resistors components to achieve efficient level displacement and work in high voltage environments.
The level displacement time from high power rail to low power rail is less than 2ns, the quiescent current is only 2μA, the power consumption is low, the integration is high, and it has good anti-interference ability. It is suitable for the level from high voltage domain to low voltage domain. Convert.
Smart Images
Figure CN119253979A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of switching power supplies, in particular to a level shift circuit for a switching converter. Background Art
[0002] In the switching converter, the level shift circuit is an important component. It is mainly used to solve the signal level conversion problem between different voltage domains. As an important link in the drive logic chain, its operating frequency must be consistent with the power tube. Since the drive logic chain enters the high power rail first and then the low power rail, the level shift circuit is divided into a level up circuit and a level down circuit. The level up circuit transmits the control signal to the high voltage side, and the level down circuit transmits the output pulse of the PWM comparator to the low voltage side.
[0003] In order to ensure the high-speed and reliable operation of the overall circuit, the level shift circuit should have the following characteristics: (1) Transfer the level to be transmitted to other power rails as quickly as possible for circuit control; (2) It should have sufficient anti-interference capability. Each key node should have an active low-resistance path connected to the power rail potential during the dV / dt phase, and a latching structure should be formed during the steady-state phase to prevent the circuit from flipping by mistake. (3) During the state switching stage, there is a large transient current used for charging and discharging when each node switches its potential. After the state switching is completed, only static leakage current should exist to reduce circuit power consumption.
[0004] In current technical literature, although there are a variety of circuit architectures to achieve level shifting functions, most research and innovation focus on the design and optimization of level-up shifting circuits, while relatively insufficient attention is paid to level-down shifting circuits. The design requirements of level-down shifting circuits are significantly different from those of level-up shifting circuits, which requires targeted optimization design.
[0005] At present, the common design of the level-down shift circuit can take the form of a simple resistor divider network, which can achieve the reduction of the signal voltage by using only two resistors, but this design often performs poorly in terms of efficiency and may not be sufficient to provide the necessary current driving capability. Alternatively, the design using a dedicated level shift chip can provide more efficient and more accurate level conversion, and usually has better electrical isolation characteristics, but the integrated circuit of this design has a low degree of integration and high cost. In the field of integrated circuit design, there are many circuit schemes for implementing level down shifting. For example, by combining two inverters with different power supply voltages into a simple level down shift circuit, although this implementation method is extremely simple in operation, it has the limitation of being unable to be used under high power supply voltage. In conventional high-voltage processes, if the high power supply voltage is connected to the gate of the MOSFET, it may cause the high-voltage MOSFET to be damaged, so that the level down shift circuit cannot operate normally. Another method is to reverse the use of the level up shift circuit, that is, to exchange the positions of the high and low voltage power supplies to achieve level shifting, but using this method, there are problems such as the improved level up shift circuit does not support direct power supply position exchange, and the classic level up shift circuit is not suitable for high power supply voltage. Therefore, it is particularly important to design a dedicated level-down shift circuit to meet specific design requirements. Summary of the invention
[0006] The purpose of the present invention is to provide a level shift circuit for a switching converter, which can operate in a high-voltage environment, realize the conversion of the level from the high-voltage domain to the low-voltage domain, and has the characteristics of high speed, low power consumption and anti-interference.
[0007] In order to achieve the above-mentioned purpose, the technical methods adopted by the present invention are as follows: A level shift circuit for a switching converter comprises a voltage sampling module and a level down-shift module. The voltage sampling module comprises a sampling input unit, a speed-up unit and a sampling output unit. The level down-shift unit comprises a level input unit, a voltage limiting unit, an anti-interference unit and a level output unit. The input end of the sampling input unit is connected to the gate of an upper power tube in the switching converter. The output end of the sampling input unit is respectively connected to the input end of the speed-up unit and the input end of the sampling output unit. The output end of the speed-up unit and the output end of the sampling output unit are both connected to the input end of the level input unit. The output end of the level input unit is respectively connected to the input end of the voltage limiting module, the anti-interference module and the level output unit. The voltage sampling module and the level input unit work on a high power rail, and the voltage limiting unit, the anti-interference unit and the level output unit work on a low power rail.
[0008] As a limitation: the sampling input unit includes a first PMOS tube and a first NMOS tube, the speed-up unit includes a first voltage buffer, a first capacitor, a first resistor, and a second PMOS tube, and the sampling output unit includes a third PMOS tube, a fourth PMOS tube, and a second NMOS tube; the gate of the first PMOS tube and the gate of the first NMOS tube are both connected to the gate of the upper power tube in the switching converter, the source of the first PMOS tube is connected to the voltage BST, the drain of the first PMOS tube is respectively connected to the input end of the first voltage buffer, the gate of the third PMOS tube, the gate of the second NMOS tube, and the drain of the first NMOS tube, and the source of the first NMOS tube is connected to the input end of the first voltage buffer, the gate of the third PMOS tube, the gate of the second NMOS tube, and the drain of the first NMOS tube. The electrodes are respectively connected to the source of the second NMOS tube and the control end of the level input unit, the source of the third PMOS tube is connected to the voltage BST, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the drain of the fourth PMOS tube is respectively connected to the drain of the second PMOS tube, the input end of the level input unit and the drain of the second NMOS tube, the gate of the fourth PMPOS tube is connected to the voltage PBIAS, the output end of the first voltage buffer is connected to one end of the first capacitor, the other end of the first capacitor is respectively connected to one end of the first resistor and the gate of the second PMOS tube, and the other end of the first resistor and the source of the second PMOS tube are both connected to the voltage BST.
[0009] As a further limitation: the level input unit includes a first high-voltage PMOS tube, the voltage limiting unit includes a fifth PMOS tube and a third NMOS tube, the anti-interference unit includes a unidirectional delay reverse circuit, a fourth NMOS tube and a second resistor, and the level output unit includes a second voltage buffer and a third resistor; the output end of the sampling input unit is connected to the gate of the first high-voltage PMOS tube, the output ends of the speed-up unit and the sampling output unit are both connected to the source of the first high-voltage PMOS tube, the drain of the first high-voltage PMOS tube is respectively connected to the drain of the fifth PMOS tube, the drain of the third NMOS tube, one end of the second resistor, the input end of the second voltage buffer and one end of the third resistor, the gate and source of the fifth PMOS tube are both connected to the internal power supply voltage VDD, the gate of the third NMOS tube is connected to the voltage NBIAS, the source of the third NMOS tube is grounded, the other end of the second resistor is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is connected to the output end of the unidirectional delay reverse circuit, the input end of the unidirectional delay reverse circuit is connected to the NBIAS voltage, and the output end of the second voltage buffer is connected to the other end of the third resistor to output a level signal.
[0010] As a further limitation: the unidirectional delayed reverse circuit includes a sixth PMOS tube, a fifth NMOS tube, a fourth resistor and a second capacitor, the gate of the sixth PMOS tube and the gate of the fifth NMOS tube are connected to the NBIAS voltage, the source of the sixth PMOS tube is connected to the internal power supply voltage VDD, the drain of the sixth PMOS tube is respectively connected to one end of the fourth resistor, one end of the second capacitor and the gate of the fourth NMOS tube, the other end of the fourth resistor is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube and the other end of the second capacitor are both grounded.
[0011] Due to the adoption of the above scheme, the present invention has the following beneficial effects compared with the prior art: (1) The present invention provides a level shift circuit for a switching converter. The circuit samples the gate signal of the upper power tube in the switching converter through a voltage sampling module and outputs the sample to the level down shift module. The circuit can accurately reflect the state signal of the upper power tube in the switching converter to the subsequent circuit without affecting the driving capability of the upper power tube. The level shift time from the high power rail to the low power rail is less than 2ns, and the level shift rate is fast. The static current is only 2μA, and the power consumption is low. Due to the particularity of the power tube gate signal, a voltage sampling module is used to avoid affecting the state of the upper power tube. The circuit occupies a small area and has a high degree of integration. (2) The present invention provides a level shift circuit for a switching converter, wherein a first voltage buffer, a first capacitor, a first resistor and a second PMOS transistor cooperate with each other to improve the level shift rate; the fourth PMOS transistor and its input bias voltage PBIAS together limit the maximum current output by the third PMOS transistor to avoid the situation where the voltage BST is directly connected to the ground; the voltage NBIAS controls the third NMOS transistor to be turned on in advance, ensuring that the initial potential at the connection node of the third NMOS transistor, the fifth PMOS transistor and the first high-voltage PMOS transistor is 0. At the same time, the potential of the voltage NBIAS is relatively low, and the current flowing through the third NMOS transistor is very small, thereby reducing power consumption; the unidirectional delayed reverse circuit outputs a delayed inverted signal only when the voltage NBIAS changes from 0 to high, thereby improving the anti-interference ability. When the voltage NBIAS changes from high to low, there is no delay, thereby improving the level shift speed when the input voltage changes from high to low; the second voltage buffer and the third resistor play a positive feedback role, thereby improving the level shift speed.
[0012] The present invention is applicable to level conversion from a high voltage domain to a low voltage domain. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0014] Figure 1 A circuit diagram of a level shift circuit for a switching converter according to an embodiment of the present invention; Figure 2 A circuit diagram of a one-way delayed reverse circuit according to an embodiment of the present invention; Figure 3 This is a waveform diagram of one cycle during the Buck switching process of an embodiment of the present invention; In the figure: 1. Sampling input unit; 2. Speed-up unit; 3. Sampling output unit; 4. Level input unit; 5. Voltage limiting unit; 6. Anti-interference unit; 7. Level output unit. DETAILED DESCRIPTION
[0015] The present invention is further described below in conjunction with embodiments, but those skilled in the art should understand that the present invention is not limited to the following embodiments, and any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.
[0016] Embodiment A level shift circuit for a switching converter A level shift circuit for a switching converter comprises a voltage sampling module and a level down-shift module. The voltage sampling module comprises a sampling input unit 1, a speed-up unit 2 and a sampling output unit 3. The level down-shift unit comprises a level input unit 4, a voltage limiting unit 5, an anti-interference unit 6 and a level output unit 7. The sampling input unit 1 comprises a first PMOS tube P1 and a first NMOS tube N1. The speed-up unit 2 comprises a first voltage buffer B1, a first capacitor C1, a first resistor R1, and a second PMOS tube P2. The sampling output unit 3 comprises a third PMOS tube P3, a fourth PMOS tube P4 and a second NMOS tube N2. The level input unit 4 comprises a first high-voltage PMOS tube HP1. The voltage limiting unit 5 comprises a fifth PMOS tube P5 and a third NMOS tube N3. The anti-interference unit 6 comprises a unidirectional delay reverse circuit, a fourth NMOS tube N4 and a second resistor R2. The level output unit 7 comprises a second voltage buffer B2 and a third resistor R3. The voltage sampling module and the level input unit 4 work on a high power rail, and the voltage limiting unit 5, the anti-interference unit 6 and the level output unit 7 work on a low power rail.
[0017] like Figure 1As shown, the gate of the first PMOS transistor P1 and the gate of the first NMOS transistor N1 are both connected to the gate of the upper power transistor in the switching converter, the source of the first PMOS transistor P1 is connected to the voltage BST, the drain of the first PMOS transistor P1 is respectively connected to the input end of the first voltage buffer B1, the gate of the third PMOS transistor P3, the gate of the second NMOS transistor N2 and the drain of the first NMOS transistor N1, the output end of the first voltage buffer B1 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is respectively connected to one end of the first resistor R1 and the gate of the second PMOS transistor P2, the other end of the first resistor R1 and the source of the second PMOS transistor P2 are both connected to the voltage BST, the source of the first NMOS transistor N1 is respectively connected to the source of the second NMOS transistor N2 and the gate of the first high-voltage PMOS transistor HP1, the source of the third PMOS transistor P3 is connected to the voltage BST, the drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4, the drain of the fourth PMOS transistor P4 is connected to the source of the fourth PMOS transistor P4. The gate of the fourth PMPOS tube is connected to the voltage PBIAS; the drain of the first high-voltage PMOS tube HP1 is connected to the drain of the fifth PMOS tube P5, the drain of the third NMOS tube N3, one end of the second resistor R2, the input end of the second voltage buffer B2 and one end of the third resistor R3 respectively; the gate and source of the fifth PMOS tube P5 are both connected to the internal power supply voltage VDD; the gate of the third NMOS tube N3 is connected to the voltage NBIAS; the source of the third NMOS tube N3 is grounded; the other end of the second resistor R2 is connected to the drain of the fourth NMOS tube N4; the source of the fourth NMOS tube N4 is grounded; the gate of the fourth NMOS tube N4 is connected to the output end of the one-way delay reverse circuit; the input end of the one-way delay reverse circuit is connected to the NBIAS voltage; the output end of the second voltage buffer B2 is connected to the other end of the third resistor R3 to output the level signal.
[0018] like Figure 2 As shown, the unidirectional delayed reverse circuit in this embodiment includes a sixth PMOS tube P6, a fifth NMOS tube N5, a fourth resistor R4 and a second capacitor C2. The gate of the sixth PMOS tube P6 and the gate of the fifth NMOS tube N5 are connected to the NBIAS voltage, the source of the sixth PMOS tube P6 is connected to the internal power supply voltage VDD, the drain of the sixth PMOS tube P6 is respectively connected to one end of the fourth resistor R4 and one end of the second capacitor C2 as the output end OUT1 of the unidirectional delayed reverse circuit, and outputs a delayed inverted signal to the gate of the fourth NMOS tube N4 to improve the anti-interference ability of the circuit. The other end of the fourth resistor R4 is connected to the drain of the fifth NMOS tube N5, and the source of the fifth NMOS tube N5 and the other end of the second capacitor C2 are both grounded.
[0019] The level shift circuit of this embodiment samples the gate signal IN of the upper power tube in the switching converter through a voltage sampling module and outputs it to the level down-shift module, which can accurately reflect the state signal of the upper power tube in the switching converter to the subsequent circuit without affecting the driving capability of the upper power tube. When the power tube on the switch converter starts to turn on, the voltage at the SW node is the power supply voltage VIN of the input switch converter; the voltage BST is the power supply voltage VIN of the input switch converter plus an internal power supply voltage VDD, that is, BST=VIN+VDD; the input voltage IN is close to the voltage BST, which is equivalent to the high level on the high power rail. At this time, the input voltage of the first voltage buffer B1 is a low level, which pulls down the gate voltage of the second PMOS tube P2, and the second PMOS tube P2 is turned on to provide current for the level shift circuit. The voltage at the VH node becomes a high level. The first voltage buffer B1, the first capacitor C1, the first resistor R1 and the second PMOS tube P2 play a role in increasing the rate. The gate of the second PMOS tube P2 is connected to the voltage BST through the first resistor R1, which is usually a high level. Only when the input voltage IN is a high level, the first voltage buffer B1 temporarily pulls down the voltage of the second PMOS tube P2 through the first capacitor C1, so that the voltage at the VH node becomes a high level faster, thereby increasing the level shift speed. Subsequently, the gate voltage of the second PMOS tube P2 increases, and the second PMOS tube P2 is turned off. At the same time, the third PMOS tube P3 begins to conduct, and the voltage BST outputs current through the third PMOS tube P3 and the fourth PMOS tube P4. The voltage at the VH node maintains a high level, so the voltage at the VH node is the sampling output result of the voltage sampling module for the gate signal IN of the upper power tube in the switching converter. The fourth PMOS tube P4 and its input bias voltage PBIAS together limit the maximum current output by the third PMOS tube P3 to the VH node, avoiding the situation where the voltage BST is directly connected to the ground. When the voltage at the VH node becomes a high level, the current flows into the level down-shifting module through the first high-voltage PMOS tube HP1. Since the current flowing in from the first high-voltage PMOS tube HP1 is greater than the current flowing out to the ground, the voltage at the VL node becomes a high level, and the level output unit 7 outputs the signal OUT as a high level. The fifth PMOS tube P5 limits the maximum voltage value at the VL node. The excess current flowing in through the second PMOS tube P2 flows to VDD through the body diode of the fifth PMOS tube P5, so the maximum voltage at the VL node is about VDD+0.7V, realizing the conversion from the high voltage domain to the low voltage domain. The voltage NBIAS is slightly ahead of the input voltage IN in phase. Before the voltage at the VL node rises, the third NMOS tube N3 is turned on in advance, ensuring that the initial potential at the VL node is 0. At the same time, the NBIAS potential is relatively low, and the current flowing through the third NMOS tube N3 is very small, reducing power consumption.After the voltage NBIAS passes through a unidirectional delayed reverse circuit, it is connected to the gate of the fourth NMOS tube N4. When the input voltage IN is at a high level for a certain period of time, the fourth NMOS tube N4 is still in the on state. During the process of the voltage at the SW node rising from 0 to VDD at a very fast speed, the dV / dt between the gate and the drain of the first high-voltage PMOS tube HP1 is very large, and its parasitic capacitance is discharged. The fourth NMOS tube N4 is turned on to provide a discharge path, which improves the anti-interference ability. After the parasitic capacitance of the first high-voltage PMOS tube HP1 is discharged, the fourth NMOS tube N4 is turned off, and no current flows, which reduces the static power consumption. The second resistor R2 limits the DC current flowing through the fourth NMOS tube N4. The unidirectional delayed reverse circuit only outputs a delayed inverted signal when the voltage NBIAS changes from 0 to high, which improves the anti-interference ability; when the voltage NBIAS changes from high to low, there is no delay, which improves the level shift speed when the input voltage IN changes from high to low. The second voltage buffer B2 and the third resistor R3 play a positive feedback role, which improves the speed of level shift. When the upper power tube in the switching converter starts to turn off, the first high-voltage PMOS tube HP1 is turned off, and after a very short delay, the voltage NBIAS becomes a low level, the third NMOS tube N3 is turned off, and the fourth NMOS tube N4 is turned on, instantly pulling down the voltage at the VL node, and the level output unit 7 outputs a signal OUT of a low level.
[0020] The level shift circuit of this embodiment is designed using 0.18μm BCD technology and is integrated in the Buck chip. During the Buck switching process, the gate signal of the upper power tube continuously switches between high level, low level, high power rail, and low power rail. The waveform of one cycle (1μs) is shown as follows: Figure 3 As shown, when the input voltage IN changes from low level to high level, the output signal OUT also changes from low level to high level after about 1.5ns, and the voltage at the VL node has two spikes. The first spike is because the second PMOS tube P2 is briefly turned on, and the second spike is the reason why the third PMOS tube P3 and the fourth PMOS tube P4 start to turn on. Obviously, the first voltage buffer B1, the first capacitor C1, the first resistor R1 and the second PMOS tube P2 play a role in increasing the rate, so that the level shift can be quickly achieved even when the current size of the third PMOS tube P3 is limited. When the input voltage IN changes from high level to low level, the output signal OUT also changes from high level to low level after about 1ns. At this time, the voltage at the VL node is quickly pulled down mainly by the fourth NMOS tube N4, thereby quickly pulling down the output signal OUT.
Claims
1. A level shift circuit for a switching converter, characterized in that: The invention comprises a voltage sampling module and a level down-shifting module. The voltage sampling module comprises a sampling input unit, a speed-up unit and a sampling output unit. The level down-shifting unit comprises a level input unit, a voltage limiting unit, an anti-interference unit and a level output unit. The input end of the sampling input unit is connected to the gate of the upper power tube in the switching converter. The output end of the sampling input unit is respectively connected to the input end of the speed-up unit and the input end of the sampling output unit. The output end of the speed-up unit and the output end of the sampling output unit are both connected to the input end of the level input unit. The output end of the level input unit is respectively connected to the input end of the voltage limiting module, the anti-interference module and the level output unit. The voltage sampling module and the level input unit work on a high power rail, and the voltage limiting unit, the anti-interference unit and the level output unit work on a low power rail.
2. A level shift circuit for a switching converter according to claim 1, characterized in that: The sampling input unit includes a first PMOS tube and a first NMOS tube, the speed-up unit includes a first voltage buffer, a first capacitor, a first resistor and a second PMOS tube, and the sampling output unit includes a third PMOS tube, a fourth PMOS tube and a second NMOS tube; the gate of the first PMOS tube and the gate of the first NMOS tube are both connected to the gate of the upper power tube in the switching converter, the source of the first PMOS tube is connected to the voltage BST, the drain of the first PMOS tube is respectively connected to the input end of the first voltage buffer, the gate of the third PMOS tube, the gate of the second NMOS tube and the drain of the first NMOS tube, and the source of the first NMOS tube is respectively connected to the input end of the first voltage buffer, the gate of the third PMOS tube, the gate of the second NMOS tube and the drain of the first NMOS tube. The first transistor is connected to the source of the second NMOS tube and the control end of the level input unit, the source of the third PMOS tube is connected to the voltage BST, the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the drain of the fourth PMOS tube is respectively connected to the drain of the second PMOS tube, the input end of the level input unit and the drain of the second NMOS tube, the gate of the fourth PMPOS tube is connected to the voltage PBIAS, the output end of the first voltage buffer is connected to one end of the first capacitor, the other end of the first capacitor is respectively connected to one end of the first resistor and the gate of the second PMOS tube, and the other end of the first resistor and the source of the second PMOS tube are both connected to the voltage BST.
3. A level shift circuit for a switching converter according to claim 1 or 2, characterized in that: The level input unit includes a first high-voltage PMOS tube, the voltage limiting unit includes a fifth PMOS tube and a third NMOS tube, the anti-interference unit includes a unidirectional delay reverse circuit, a fourth NMOS tube and a second resistor, and the level output unit includes a second voltage buffer and a third resistor; the output end of the sampling input unit is connected to the gate of the first high-voltage PMOS tube, the output ends of the speed-up unit and the sampling output unit are both connected to the source of the first high-voltage PMOS tube, the drain of the first high-voltage PMOS tube is respectively connected to the drain of the fifth PMOS tube, the drain of the third NMOS tube, one end of the second resistor, the input end of the second voltage buffer and one end of the third resistor, the gate and source of the fifth PMOS tube are both connected to the internal power supply voltage VDD, the gate of the third NMOS tube is connected to the voltage NBIAS, the source of the third NMOS tube is grounded, the other end of the second resistor is connected to the drain of the fourth NMOS tube, the source of the fourth NMOS tube is grounded, the gate of the fourth NMOS tube is connected to the output end of the unidirectional delay reverse circuit, the input end of the unidirectional delay reverse circuit is connected to the NBIAS voltage, and the output end of the second voltage buffer is connected to the other end of the third resistor to output a level signal.
4. A level shift circuit for a switching converter according to claim 3, characterized in that: The unidirectional delayed reverse circuit includes a sixth PMOS tube, a fifth NMOS tube, a fourth resistor and a second capacitor. The gate of the sixth PMOS tube and the gate of the fifth NMOS tube are connected to the NBIAS voltage, the source of the sixth PMOS tube is connected to the internal power supply voltage VDD, the drain of the sixth PMOS tube is respectively connected to one end of the fourth resistor, one end of the second capacitor and the gate of the fourth NMOS tube, the other end of the fourth resistor is connected to the drain of the fifth NMOS tube, and the source of the fifth NMOS tube and the other end of the second capacitor are both grounded.