Delay chain type timing core circuit
Through phase selection connection method and pseudo-differential gate delay unit design, the parity delay difference and high power consumption problems of time measurement circuits in the prior art are solved, and the time measurement effect with higher accuracy and low power consumption is achieved.
Patent Information
- Application Number
- CN202411416961.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-11
- Publication Date
- 2025-01-03
AI Technical Summary
While the existing delay chain-type time measurement circuits improve time resolution and reduce power consumption, there are problems such as parity delay differences, signal offset accumulation and high power consumption, especially in multi-channel design and long delay chain conditions. and power consumption increases.
The second-level interpolation circuit is realized by using phase selection connection method, combined with the pseudo-differential gate delay unit design, reduces the delay unit delay and reduces power consumption, and forms the delay chain-type timing core through a variety of connection methods of ring vibration mode and differential delay chain Circuit, enabling low power consumption and high precision time measurement.
Break through the limit of minimum gate unit delay, reduce parity and even delay differences and signal offset accumulation, improve the ability to resist process, temperature and power supply deviations, and achieve lower power consumption and higher precision time measurements.
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Figure CN119254199A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of circuit design and relates to a delay chain type timing core circuit. Background Art
[0002] In high-energy physics experiments, many detectors need to measure the flight time of particles; in positron emission tomography, lesions are also located by measuring time information. Applications such as these involving time measurement require time-to-digital conversion chips. There are many technical paths that can be implemented by this chip, and different technical paths have their own advantages and disadvantages. A large number of scientific researchers have carried out targeted research based on demand. The timing core of the delay chain type time measurement circuit usually includes ordinary delay chain, ring oscillation type delay chain, controlled (ring oscillation) delay chain, vernier delay chain, etc. The first three can usually also be combined with interpolation circuits to obtain smaller time resolution. There are three types of design routes similar to the present invention:
[0003] First, several variables are uniformly defined: the time delay from the input to the output of the gate delay unit or the differential delay unit or the voltage-controlled differential delay unit is Td, the number of units used in the delay chain is M (where M is usually an odd number ≥3 for the ring oscillator type gate delay chain structure, but M can also be an even number for the differential ring oscillator type structure), the ring oscillator period is Tosc, the number of interpolation unit levels is N, and the minimum time interval is LSB.
[0004] Design route 1 is a ring oscillator delay chain, which is usually implemented by gate circuits (such as NOT gates, NAND gates, NOT gates with switches, and such gate circuits), or by differential circuits. Taking gate circuits as an example, a ring oscillator (or ring oscillator delay chain) can be composed of M gate units (M is an odd number ≥ 3), so LSB = Td = Tosc / 2M. Taking the ETROC chip as an example, a time measurement resolution of 18ps is achieved under a 65nm process. Figure 1 It is the implementation scheme of its core circuit, in which the ring oscillator delay chain is its timing core circuit.
[0005] The second design route is to use differential delay units to form a delay chain, combined with a timing core circuit implemented by resistor-capacitor interpolation, and its LSB = Td / N. In order to improve the measurement accuracy, a voltage-controlled differential delay unit is usually used in combination with a delay phase-locked loop structure. Its Td can be adjusted by controlling the voltage, and then using the feedback adjustment of the delay phase-locked loop to obtain a more accurate Td, which is theoretically equal to the reference clock period, minus the phase error when the delay phase-locked loop is locked, and then divided by M. Taking the PicoTDC developed by the European Organization for Nuclear Research as an example, it has recently achieved a time measurement resolution of 3ps on a 65nm process. Figure 2 The implementation scheme adopted for its core circuit.
[0006] Design route three is similar to design route two, such as Figure 3As shown, the differential delay unit and the interpolation unit are used; the difference is that the differential delay unit is connected into a ring oscillator structure, and the interpolation unit is independently inserted between the input and output of each delay unit. If the oscillation period is Tosc, then: Td = Tosc / 2M and LSB = Td / N. On the one hand, this scheme is easy to connect the coarse and fine counting, and on the other hand, when Td and M are the same as those in scheme 2, the range can be doubled, and the utilization rate is higher.
[0007] Disadvantages of technical route 1: Under the same process, the limitation of gate unit delay (Td) needs to be solved to further reduce the time resolution; its structural characteristics have obvious differences in odd and even delays, and vary greatly with process parameters, temperature, and voltage. For example, the ETROC chip controls the switching of the delay chain to reduce power consumption at low event rates (the power consumption of a single channel at event rates of 1% and 100% is approximately 2.13mW and 97μW, respectively), but the disadvantage is that the resolution of 18ps is not easy to be further reduced under this process and this architecture, and the single-ended signal noise resistance performance is poor.
[0008] Disadvantages of technical route 2: The differential delay chain controlled by a delay-locked loop has strong anti-noise performance, but the differential delay chain consumes a lot of power. When designing multiple channels, a common delay chain is required. Therefore, when the scale is large, the long-distance propagation and precise calibration of the multi-phase clock will greatly increase the complexity of the design, and also increase the power consumption. For example, when PicoTDC works at LSB of 12ps and 3ps, the power consumption of a single channel is about 13.3mW and 20.3mW respectively. Moreover, compared with the ring oscillator, the range is only half of that under the same conditions. On the other hand, if the differential units are connected in the same phase, it is easy to cause differential signal imbalance and accumulation step by step; when a long delay chain is formed, there is a difference in the delay between the head and the tail, and multiple repeated units need to be connected as buffers, and the duty cycle imbalance of the later stage will be aggravated step by step. On the other hand, when the voltage-controlled delay unit Td changes, the difference and duty cycle accumulation problems will be aggravated due to deviation from the optimized value, so the working range is narrow and the adaptability is poor.
[0009] Disadvantages of technical route three: The interpolation circuits are independent of each other, so larger resistors and buffers are required, which will increase power consumption, and the delay information transmitted to the interpolation circuit is also prone to large errors, which is also related to the buffer driving capability. In addition, the adjacent interpolated signals are inverted, which increases the complexity of the subsequent encoding circuit on the one hand, and also has odd-even delay differences on the other hand. This structure is significantly affected by the process angle, temperature, and power supply voltage. Summary of the invention
[0010] In view of the problems existing in the prior art, the purpose of the present invention is to provide a delay chain type timing core circuit. The present invention proposes a phase selection method to connect the interpolation unit. On the one hand, it solves the problem that the delay unit cannot realize interpolation due to the inversion of the input and output of the unit itself, or the inversion between adjacent signals or the inversion of signals between half cycles and cycles caused by the interconnection method (including gate delay units and differential delay units); on the other hand, while reducing the basic unit delay Td, the odd-even delay difference and signal offset accumulation can be further reduced. At the same time, a circuit design of a pseudo-differential gate delay unit is proposed, which can also realize the second-level interpolation, and has lower power consumption than the differential delay unit under the same conditions.
[0011] The technical solution of the present invention is:
[0012] Solution 1: A delay chain type timing core circuit, characterized in that it includes a ring oscillator type delay chain composed of M gate delay units and M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, and M is an odd number greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit;
[0013] The adjacent signals appearing in time sequence in each oscillation cycle of the ring oscillator delay chain are inverted to each other, and the input signal V i After being delayed by a buffer, a corresponding delayed signal CO is obtained. i ; Wherein, i = 1 ~ M;
[0014] Each delayed signal CO i According to the setting order "CO1, CO3, ..., CO M , CO2, ..., CO M-1 " are sequentially used as the A-end input signals of the 1st to Mth interpolation units; wherein "CO1, CO3, ..., CO M " is the odd-numbered delayed signal arranged in sequence, "CO2, ..., CO M-1 ” is the even-numbered delayed signal arranged in sequence.
[0015] When the interpolation unit is composed of N series-connected resistors and N buffers, the timing core circuit obtains 2MN delayed signal outputs after interpolation.
[0016] Solution 2: A delay chain type timing core circuit, characterized in that it includes a ring oscillator type differential delay chain composed of M differential delay units with double buffer outputs and 2M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, and M is an integer greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit;
[0017] The differential signal V output by the ith differential delay unit in the ring oscillator type differential delay chain i The differential signal V is input to the i+1th differential delay unit and output by the Mth differential delay unit. M Input to the first differential delay unit V1, i=1~M-1; the differential delay unit outputs a pair of single-ended signals with zero delay and opposite phases through a double buffer, which are called complementary single-ended signals, and the jth differential delay unit outputs complementary single-ended signals CO through a double buffer j Including positive phase signal CO j正 , inverted signal CO j反 , CO j正 and CO j反 The delay between them is zero, j = 1 ~ M;
[0018] The positive phase signal and the negative phase signal in each complementary single-ended signal are respectively sent in a set order "CO 1正 , CO 2正 ,……,CO M正 , CO 1反 , CO 2反 ……、CO M反 " is sequentially used as the A-end input signal of the 1st to 2Mth interpolation units, and "CO 2正 、VCO 3正 ,……,CO M正 , CO 1反 , CO 2反 ……、CO M反 , CO 1正 " is sequentially used as the B-end input signal of the 1st to 2Mth interpolation units.
[0019] When the interpolation unit is composed of N series-connected resistors and N buffers, the timing core circuit obtains 2MN delayed signal outputs after interpolation.
[0020] Solution 3: A delay chain type timing core circuit, characterized in that it includes a ring oscillator type differential delay chain composed of M differential delay units with double buffer outputs and 2M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, and M is an integer greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit;
[0021] The differential signal V output by the ith differential delay unit in the ring oscillator type differential delay chain i The differential signal V is input to the i+1th differential delay unit and output by the Mth differential delay unit. M Input to the first differential delay unit V1, i=1~M-1; the differential delay unit outputs a pair of delayed single-ended signals with the same phase through a double buffer, and the single-ended signals output by adjacent differential delay units have opposite phases; the single-ended signal CO output by the jth differential delay unit through the double buffer j Including CO j正 , CO' j正 , CO' j正 For CO j正 The delayed signal has a delay size equal to the delay of a differential delay unit, j = 1 to M;
[0022] Assume that the single-ended signal CO1 output by the first differential delay unit through the double buffer includes a positive phase signal CO 1正 , CO' 1正 , the positive phase signal and the negative phase signal in each single-ended signal are set in the order of "CO 1正 , CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 " is sequentially used as the A-end input signal of the 1st to 2Mth interpolation units, and "CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 , CO 1正" are sequentially used as the B-end input signals of the 1st to 2Mth interpolation units; the timing core circuit obtains 2MN delayed signal outputs after interpolation.
[0023] When the interpolation unit is composed of N series-connected resistors and N buffers, the timing core circuit obtains 2MN delayed signal outputs after interpolation.
[0024] Further, the differential delay unit is a pseudo differential gate delay unit, which includes four inverters and two buffers; the four inverters are denoted as a first inverter I1, a second inverter I2, a third inverter I3, and a fourth inverter I4; the two buffers are denoted as a first buffer I5 and a second buffer I6;
[0025] The first inverter I1 responds to the input signal IN p After inversion, the input signals are respectively input to the third inverter I3 and the first buffer I5; the third inverter I3 inverts the input signals and then inputs the signals to the second buffer I6;
[0026] The second inverter I2 responds to the input signal IN n After inversion, the input signals are respectively input to the fourth inverter I4 and the second buffer I6; the fourth inverter I4 inverts the input signals and then inputs the input signals to the first buffer I5;
[0027] The first buffer I5 inverts the input signal twice to obtain an output signal COn, and the second buffer I6 inverts the input signal twice to obtain an output signal Cop;
[0028] Among them, the input signal IN p With input signal IN n The phases are opposite, and the output signal COp is opposite to the output signal COn.
[0029] Furthermore, each of the buffers is composed of two inverters.
[0030] Furthermore, the driving capability of the third inverter I3 is the same as that of the fourth inverter I4, the driving capability of the first buffer I5 is twice that of the third inverter I3, the driving capability of the second buffer I6 is twice that of the third inverter I3, and the driving capability of the first inverter I1 and the second inverter I2 is eight times that of the third inverter I3.
[0031] Furthermore, the differential delay unit may be a five-tube amplifier, a symmetrical load amplifier, or a cross-coupled load amplifier.
[0032] Furthermore, for scheme 2, the connection mode of the ring oscillator type differential delay chain is ring oscillator in-phase connection + cross feedback + output stage double buffering, ring oscillator full cross connection + output stage double buffering, ring oscillator cross interconnection + in-phase feedback + output stage double buffering.
[0033] Furthermore, for solution three, the connection mode of the ring oscillator type differential delay chain is ring oscillator full cross connection + input stage and output stage buffer.
[0034] A time measurement TDC chip, characterized in that it comprises the above-mentioned delay chain type timing core circuit and a quantization readout circuit; the quantization readout circuit is used to quantize, encode and read out the signal output by the timing core circuit.
[0035] The present invention realizes the second-level interpolation circuit by phase selection connection mode in the delay chain type timing core circuit, which is applicable to the ring oscillator delay chain composed of gate delay units, and the delay chain or ring oscillator delay chain composed of (voltage-controlled) differential delay units through various connection modes.
[0036] The present invention realizes an interpolable, low-power-consumption pseudo-differential gate delay unit circuit design through a digital gate unit.
[0037] The advantages of the present invention are as follows:
[0038] The present invention provides a method for realizing an interpolation circuit, namely, a phase selection interpolation method, which is used in a delay chain type time-to-digital conversion circuit, and can break through the limitation of the minimum gate unit delay (or differential unit delay) to a certain extent, and further reduce the difference in odd-even delay and the minimum time interval (LSB); it can also be flexibly combined with the differential delay unit and the delay chain design to further improve the circuit's resistance to process, temperature and power supply deviation and noise, and can also reduce asymmetry and offset accumulation. The circuit implementation of the pseudo-differential gate delay unit proposed by the present invention has lower power consumption than the differential delay unit under the same conditions. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1 Diagram of the implementation scheme used by the delay chain core of the ETROC chip.
[0040] Figure 2 This is the implementation scheme used by the PicoTDC chip delay chain core.
[0041] Figure 3 The timing core circuit diagram of a ring oscillator type differential delay chain.
[0042] Figure 4 This is the circuit diagram of the ring oscillator gate delay chain and interpolation.
[0043] Figure 5It is a design diagram of a differential delay chain (or a ring oscillator type differential delay chain);
[0044] (a) Long chain in-phase connection, (b) long chain cross connection, (c) ring oscillator in-phase connection + cross feedback, (d) ring oscillator full cross connection, (e) ring oscillator cross interconnection + in-phase feedback, (f) ring oscillator in-phase connection + cross feedback + output stage double buffering, (g) ring oscillator full cross connection + output stage double buffering, (h) ring oscillator cross interconnection + in-phase feedback + output stage double buffering, (i) ring oscillator full cross connection + input stage and output stage buffering.
[0045] Figure 6 It is a ring oscillator type differential delay chain and interpolation circuit diagram;
[0046] (a) Interpolation implementation of double buffering at the output stage, (b) Interpolation implementation of input and output stage buffering.
[0047] Figure 7 A circuit diagram of a low-power improved pseudo-differential gate delay unit;
[0048] (a) Circuit diagram of pseudo-differential gate delay unit, (b) symbol of pseudo-differential gate delay unit. DETAILED DESCRIPTION
[0049] The present invention is further described in detail below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention but not to limit the scope of the present invention.
[0050] The present invention is based on a delay chain type time measurement architecture and proposes a phase selection interpolation circuit implementation method to obtain a circuit with better performance and smaller time interval (LSB), namely the timing core mentioned above. The actual circuit implementation involves two types based on gate units and differential units, which will be explained separately below.
[0051] 1. Ring oscillator gate delay chain and interpolation circuit implementation
[0052] For architectures based on gate delay chains, Figure 4 Taking the example shown in the figure, the timing core part includes a ring oscillator type delay chain composed of 5 gate delay units and 5 closed-loop connected interpolation units. In this example, the gate delay unit is composed of an inverter (also called a NOT gate), and can also be implemented by other gate circuits, such as a NAND gate, an inverter with enable control, an inverter with voltage-controlled delay adjustment, or a NAND gate. The output of the delay unit is defined as Vi, and the buffer output is COi, i=1~M. First, let's look at the ring oscillator. Assuming that the initial V1 is a positive phase, the signal edges and their phases that appear in time sequence within the entire oscillation period (also its range) are "V 1正 -V 2反 -V 3正 -V 4反 -V 5正 -V1反 -V 2正 -V 3反 -V 4正 -V 5反 ", it can be seen that adjacent signals are inverted, and the resistive interpolation unit requires the signals at both ends A and B to be in phase, so it is impossible to directly interpolate between adjacent signals. Figure 4 The V2 and V4 output buffers are replaced with inverters, and the buffers and inverters are designed to have the same delay, and the interpolated signal becomes "CO 1正 -CO 2正 -CO 3正 -CO 4正 -CO 5正 -CO 1反 -CO 2反 -CO 3反 -CO 4反 -CO 5反 ”, where “CO 5正 -CO 1反 ” and “CO 5反 -CO for the next cycle 1正 "The two sets of adjacent signals still cannot be interpolated, and the measurement range cannot cover the entire oscillation period.
[0053] The present invention is based on the phase relationship of one cycle of the original node "V 1正 -V 2反 -V 3正 -V 4反 -V 5正 -V 1反 -V 2正 -V 3反 -V4 正 -V 5反 ", select the in-phase signal from it and connect it with the start signal of the next cycle to form a closed loop, that is, "V1-V3-V5-V2-V4-V1". In terms of time sequence, the in-phase relationship of the signals at each level is realized, and interpolation can be performed between two adjacent signals, and the entire cycle can be covered. At this time, the interpolated time interval becomes 2Td, then LSB=2Td / N. Theoretically, as long as N>2, the limitation of the original design gate delay can be broken; and because the delay of the odd-even gate delay unit is combined into 2Td and then interpolated, there is no problem of parity difference. Therefore, when the number of ring-oscillation gate delay chain units is M (M is an odd number ≥3), the first-stage input signal is defined as V1, and the closed-loop signal for interpolation obtained by phase selection is: "V1, V3,..., V M , V2, ..., V M-1 , V1". The interpolation unit is as follows Figure 4As shown in the figure, it consists of N resistors and N buffers. The resistance of the N resistors increases gradually from port A to port B, but is not completely proportional. When designing, it is necessary to adjust the resistance value in combination with the actual circuit and layout to obtain N relatively uniform delayed outputs. Therefore, the timing core will output M×N clock signals into the quantization circuit.
[0054] The quantization circuit is usually composed of one or more groups of triggers and counters (depending on the specific application and design). The trigger group can use D-type triggers or dynamic triggers; the counter is usually composed of triggers and logic gates to realize the addition or subtraction counting of K-bit data, and re-counting when the count is full. The data input end of the trigger group is connected to M×N clock signals respectively, and its clock input end is simultaneously connected to the hit signal to be measured (the hit signal drive and fan-out need to be considered). In the trigger group, when the upper edge (or lower edge) of the hit signal comes, it is judged whether the input clock signal is low or high level, and the corresponding output digital signal is 0 or 1; and the place where the "10" jump edge appears in the M×N quantization outputs of each group of triggers is the arrival time of the measured hit signal. This data is binary encoded, added to the output of the counter, and the complete time information can be obtained after data integration. If the number of parallel output data is large, it can also be further converted into a serial data stream output. These parallel or serial output data are the time information obtained by quantization of the hit signal.
[0055] 2. Ring oscillator differential delay chain and interpolation circuit implementation
[0056] For architectures based on differential delay chains, the phase selection interpolation method remains essentially the same, but the specific implementation method is slightly different, depending on how the units are interconnected and whether they are connected as a ring oscillator. Figure 5 Most of the connection methods and phase relationships are listed, where the large triangle represents the differential delay unit (also the voltage-controlled differential delay unit), the small triangle represents the differential-to-single-ended buffer, and CO is the output signal; the differential units are numbered 1, 2, ... M in sequence. As mentioned above, technical route 2 adopts Figure 5 (a) Connection method, there is a problem of imbalance accumulation, use Figure 5 (b) Cross-connection can reduce offset accumulation, but the input terminals of even-numbered buffers need to be reversed.
[0057] Ring oscillators have a larger measurement range, but they also have many connection options, and conventional designs only have one buffer output. Figure 5 (c) In the case shown, M ≥ 3, the first to M levels are interconnected in the same direction, and the feedback from the Mth level to the first level is cross-interconnected, i.e., cross-feedback mode; Figure 5 (d) and Figure 5(e) shows the interconnection modes when M is an odd number and an even number, namely, full cross connection and cross connection combined with in-phase feedback. The outputs of these three connection modes will produce inverted adjacent signals at each half cycle, which cannot be interpolated. Therefore, the present invention adopts a double buffer output mode, which provides positive and negative phase signals of each level while ensuring the consistency of delay at each level, and uses a phase selection method to select the in-phase signal that can cover the entire cycle for interpolation. Technical route three also adopts double buffer output, such as Figure 3 As shown, the connection method and interpolation method are different, and its disadvantages are also obvious.
[0058] Double buffered output combined with phase selection interpolation, according to Figure 5 (f) Figure 5 (g) Figure 5 (h) and Figure 5 (i) The delay chain shown in the figure has slightly different circuit implementations. The double buffer can be divided into two categories according to the different connection methods. Figure 5 (f) Figure 5 (g) and Figure 5 As shown in (h), each unit simultaneously outputs a positive phase signal COp and a negative phase signal Con; Figure 5 As shown in (i), the double buffer is connected to the input and output stages of the unit respectively, and the corresponding output signals are Cin and Cout.
[0059] like Figure 5 As shown in (f), when a ring oscillator is formed by connecting the same phase with the other phases and combining cross feedback, the positive phase output can be selected in the first half cycle and the negative phase output can be selected in the second half cycle, so that the timing can be in phase and the entire range can be covered; the interpolation unit is connected between adjacent signals, and a closed loop is also formed physically; the signals used for interpolation selected by phase are: COp1, COp2, ..., COp M 、COn1、COn2、……、COn M 、COp1.
[0060] When M is an odd number, a full cross-connection method is used, such as Figure 5 As shown in (g), the signals with the same output polarity (such as positive phase) are also selected for interpolation, namely COp1, COn2, COp3, COn4, ..., COp M-2 , COn M-1 , COp M ,COn1,COp2,COn3,…,COp M-1 , COn M 、COp1.
[0061] When M is an even number, a cross-connection combined with in-phase feedback method is used, such as Figure 5As shown in (h), the signals selected by phase are: COp1, COn2, COp3, COn4, ..., COp M-1 , COn M ,COn1,COp2,COn3,COp4,…,COn M-1 , COp M 、COp1.
[0062] When M is an odd number and full cross-connection is used, Figure 5 (i) is implemented, and the phase selected signals are: Cin1, Cout1, Cin3, Cout3, ..., Cin M , Cout M ,Cin2,Cout2,…,Cin M-1 , Cout M-1 、Cin1.
[0063] Figure 6 The block diagram of the ring oscillator differential delay chain and interpolation circuit is given, where the triangle represents the (voltage-controlled) differential delay unit with double buffer output, and the interconnected signals are all differential signals (V1, V2...V M ),in Figure 6 (a) is the implementation scheme of double buffer output at the output stage, that is, each differential delay unit simultaneously outputs the positive phase and negative phase signals relative to its input, which can be called a pair of complementary single-ended signals (CO i正 and CO i反 ), corresponding to Figure 5 Cop in (f), (g) and (h) i and Con i ;and Figure 6 (b) is a scheme with one buffer at the input stage and one buffer at the output stage. The output single-ended signal pair is CO i and CO' i , corresponding to Figure 5 Cini and Couti in (i).
[0064] Assuming the initial V1 phase is positive, Figure 6 (a) CO i正 Represents that all outputs have the same positive phase as V1, CO i反 It represents a signal that is inverted with V1. When designing, it is necessary to determine Cop based on the specific connection relationship of the differential delay chain. i and Con i Which is the positive or negative phase signal of V1. During the second-level interpolation, the selected positive and negative phase signals are placed in the set order “CO 1正 , CO 2正 ,……,CO M正 , CO1反 , CO 2反 ……、CO M反 " is used as the A end of the 1st to 2Mth interpolation units, and "CO 2正 , CO 3正 ,……,CO M正 , CO 1反 , CO 2反 ……、CO M反 , CO 1正 " serves as the B ends of the 1st to 2Mth interpolation units in sequence.
[0065] Figure 6 As shown in (b), when the initial phase of V1 is positive, CO i正 and CO' i正 Both represent signals with the same positive phase as V1, CO i反 and CO' i反 Then it is the inverted signal of V1, CO' i Relative CO i The delay is one Td behind. During the second-level interpolation, the order of positive phase first and negative phase second is also followed. 1正 , CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 " is used as the A end of the 1st to 2Mth interpolation units, and "CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 , CO 1正 " serves as the B terminal of the 1st to 2Mth interpolation units in sequence. Each interpolation unit outputs N data, so the timing core will output 2M×N clock signals into the quantization circuit.
[0066] The phase selection interpolation method can be flexibly applied to various ring-oscillator differential delay chains with various interconnection modes, but the cross-connection mode will have better symmetry (including full cross-connection and cross-connection combined with in-phase feedback mode), and the parity difference will be smaller when the appropriate signal is selected in combination with double buffer output. Figure 5 (g) and Figure 5(i) The phase selection interpolation method verifies Figure 6 Compared with the third technical route, which is also a ring oscillator delay chain, the two design architectures have smaller parity delay difference, smaller time resolution (LSB), and lower power consumption under the same conditions; and there is almost no offset accumulation when connected into a long chain.
[0067] Figure 6 The differential delay unit in the circuit can usually be composed of a differential amplifier, and there are many implementation structures, such as an ordinary five-tube amplifier, a symmetrical load amplifier, a cross-coupled load amplifier, etc. By adding a voltage-controlled transistor to the load branch of the differential amplifier, a voltage-controlled differential delay unit can be realized. The buffer is realized by an analog single-ended to differential circuit. The dual buffer can be connected to the output at the same time, or to the input and output ends respectively. The differential delay unit combined with the dual buffer output can be applied to both Figure 6 (a) and Figure 6 (b) Circuit scheme.
[0068] However, the differential delay unit has a bias current, and the power consumption is difficult to further reduce. Based on this, the present invention proposes a low-power improved pseudo differential gate delay unit, such as Figure 7 As shown, used for Figure 6 (a) Verification of the scheme. The circuit consists of an inverter and a buffer. The inverter is also called a NOT gate, which converts the input logic signal into an opposite signal. The buffer is composed of two cascaded inverters; ×1, ×2 and ×8 are the driving capabilities of the inverter, which are generally equivalent to multiples of the size of the transistor inside it. Inverters I1 and I2 are the main delay units, and inverters I3 and I4 form latches, so that the differential signals Vi (VOn and VOp) interconnected between each stage when forming a ring oscillator maintain an anti-phase relationship. Different from conventional analog differential delay units, they are all implemented by digital gates, which are called pseudo-differential gate delay units here; and buffers I5 and I6 provide dual-channel buffer outputs, and their representative symbols are as follows: Figure 7 As shown in the figure on the right, it is equivalent to Figure 6 The differential delay cell in (a) is used.
[0069] The main delay unit of this structure is an inverter, which has no static power consumption, and the dynamic power consumption is only at the edge of the signal change, so the power consumption is relatively small. The pseudo-differential gate delay unit has a small number of transistors and a relatively small area. During the design, by increasing the size (driving force) of I1 and I2 and reducing the size of I3 and I4 as well as the first stage of I5 and I6, the VOn and VOp node loads are minimized to ensure that Td is as small as possible. In addition, compared with this solution, Figure 4 The solution can provide a smaller in-phase time interval - Td ( Figure 4 = 2Td), so the LSB obtained after interpolation = Td / N, which can also achieve a smaller time resolution.
[0070] Figure 7 The inverters (mainly I1 and I2) can also be implemented using other gate circuits, such as NAND gates, inverters with enable control, inverters with voltage-controlled delay adjustment, or NAND gates.
[0071] Although the specific embodiments of the present invention are disclosed for the purpose of illustration, the purpose is to help understand the content of the present invention and implement it accordingly, those skilled in the art will understand that various substitutions, changes and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the best embodiment, and the scope of the present invention is subject to the scope defined in the claims.
Claims
1. A delay chain timing core circuit, characterized in that: It comprises a ring oscillator type delay chain composed of M gate delay units and M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, and M is an odd number greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit; The adjacent signals appearing in time sequence in each oscillation cycle of the ring oscillator delay chain are inverted to each other, and the input signal V i After being delayed by a buffer, a corresponding delayed signal CO is obtained. i ; Wherein, i = 1 ~ M; Each delayed signal CO i According to the setting order "CO1, CO3, ..., CO M , CO2, ..., CO M-1 " are sequentially used as the A-end input signals of the 1st to Mth interpolation units; wherein "CO1, CO3, ..., CO M " is the odd-numbered delayed signal in sequence, "CO2, ..., CO M-1 ” is the even-numbered delayed signal arranged in sequence.
2. A delay chain timing core circuit, characterized in that: A ring oscillator type differential delay chain consisting of M differential delay units with double buffer outputs and 2M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, M is an integer greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit; The differential signal V output by the ith differential delay unit in the ring oscillator type differential delay chain i The differential signal V is input to the i+1th differential delay unit and output by the Mth differential delay unit. M Input to the first differential delay unit V1, i=1~M-1; the differential delay unit outputs a pair of single-ended signals with zero delay and opposite phases through a double buffer, which are called complementary single-ended signals, and the jth differential delay unit outputs complementary single-ended signals CO through a double buffer j Including positive phase signal CO j正 , inverted signal CO j反 , CO j正 and CO j反 The delay between them is zero, j = 1 ~ M; The positive phase signal and the negative phase signal in each complementary single-ended signal are respectively controlled in a set order. 1正 , CO 2正 ,……,CO M正 , CO 1反 , CO 2反 ……、CO M反 " is sequentially used as the A-end input signal of the 1st to 2Mth interpolation units, and "CO 2正 、VCO 3正 ,……,CO M正 , CO 1反 , CO 2反 ……、CO M反 , CO 1正 " is sequentially used as the B-end input signal of the 1st to 2Mth interpolation units.
3. A delay chain timing core circuit, characterized in that: A ring oscillator type differential delay chain consisting of M differential delay units with double buffer outputs and 2M interpolation units connected in a closed loop, the B end of the previous interpolation unit is connected to the A end of the next interpolation unit, M is an integer greater than or equal to 3; the resistance of the interpolation unit gradually increases from the A end to the B end, the A end of the interpolation unit is the end with the smallest resistance value of the interpolation unit, and the B end of the interpolation unit is the end with the largest resistance value of the interpolation unit; The differential signal V output by the ith differential delay unit in the ring oscillator type differential delay chain i The differential signal V is input to the i+1th differential delay unit and output by the Mth differential delay unit. M Input to the first differential delay unit V1, i=1~M-1; the differential delay unit outputs a pair of delayed single-ended signals with the same phase through a double buffer, and the single-ended signals output by adjacent differential delay units have opposite phases; the single-ended signal CO output by the jth differential delay unit through the double buffer j Including CO j正 , CO' j正 , CO' j正 For CO j正 The delayed signal has a delay size equal to the delay of a differential delay unit, j = 1 to M; Assume that the single-ended signal CO1 output by the first differential delay unit through the double buffer includes a positive phase signal CO 1正 , CO' 1正 , the positive phase signal and the negative phase signal in each single-ended signal are set in the order "CO 1正 , CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 " is sequentially used as the A-end input signal of the 1st to 2Mth interpolation units, and "CO' 1正 , CO 3正 , CO' 3正 ,……,CO M正 , CO' M正 , CO 2反 , CO 2反 ……、CO M-1反 , CO' M-1反 , CO 1正 " is sequentially used as the B-end input signal of the 1st to 2Mth interpolation units.
4. The delay chain timing core circuit according to claim 2 or 3, characterized in that: The differential delay unit is a pseudo differential gate delay unit, which includes four inverters and two buffers; the four inverters are denoted as a first inverter I1, a second inverter I2, a third inverter I3, and a fourth inverter I4; the two buffers are denoted as a first buffer I5 and a second buffer I6; The first inverter I1 responds to the input signal IN p After inversion, the input signals are respectively input to the third inverter I3 and the first buffer I5; the third inverter I3 inverts the input signals and then inputs the input signals to the second buffer I6; The second inverter I2 responds to the input signal IN n After inversion, the input signals are respectively input to the fourth inverter I4 and the second buffer I6; the fourth inverter I4 inverts the input signals and then inputs the input signals to the first buffer I5; The first buffer I5 inverts the input signal twice to obtain an output signal COn, and the second buffer I6 inverts the input signal twice to obtain an output signal Cop; Among them, the input signal IN p With input signal IN n The phases are opposite, and the output signal COp is opposite to the output signal COn.
5. The delay chain timing core circuit according to claim 4, characterized in that: Each of the buffers is composed of two inverters.
6. The delay chain timing core circuit according to claim 5, characterized in that: The driving capability of the third inverter I3 is the same as that of the fourth inverter I4, the driving capability of the first buffer I5 is twice that of the third inverter I3, the driving capability of the second buffer I6 is twice that of the third inverter I3, and the driving capability of the first inverter I1 and the second inverter I2 is eight times that of the third inverter I3.
7. The delay chain timing core circuit according to claim 2 or 3, characterized in that: The differential delay unit is a five-tube amplifier, a symmetrical load amplifier, and a cross-coupled load amplifier.
8. The delay chain timing core circuit according to claim 2, characterized in that: The connection mode of the ring oscillator type differential delay chain is ring oscillator in-phase connection + cross feedback + output stage double buffering, ring oscillator full cross connection + output stage double buffering, ring oscillator cross interconnection + in-phase feedback + output stage double buffering.
9. The delay chain timing core circuit according to claim 3, characterized in that: The connection mode of the ring oscillator type differential delay chain is ring oscillator full cross connection + input stage and output stage buffer.
10. A time measurement TDC chip, characterized in that: It comprises the delay chain type timing core circuit and quantization readout circuit as described in any one of claims 1 to 3; the quantization readout circuit is used for quantizing, encoding and reading out the signal output by the timing core circuit.