Series mode interference suppression circuit suitable for Sigma-delta ADC

Abstract

The invention discloses a series-mode interference suppression circuit suitable for a Sigma-delta ADC (analog-to-digital converter), which comprises an SINC3 filter, a modified SINC3 filter, an SINC4 filter and an integrator, the input ends of the SINC3 filter, the modified SINC3 filter, the SINC4 filter and the integrator are respectively connected with the output end of an ADC modulator, and the output ends of the SINC3 filter, the modified SINC3 filter, the SINC4 filter and the integrator are respectively connected with a gate MUX through a mean filter and an extraction module in sequence. And the gate MUX outputs an ADC final signal. The multi-stage SINC filter is adopted, power frequency suppression can be completed under the set output sampling frequency, and filters of different architectures can be selected according to the system rate to optimize suppression of quantization noise, device noise and 50Hz and 60Hz power frequency interference. The whole series-mode interference suppression circuit is basically composed of an integrator, a comb-shaped device, a mean value filter and an extraction module, and circuit design can be completed only through a small number of summators in the aspect of algorithm. The area and the power consumption of the circuit are greatly reduced while the suppression of series mode interference and noise is realized.

Description

Technical Field

[0001] The invention relates to the field of common mode interference suppression, and in particular to a common mode interference suppression circuit suitable for Sigma-delta ADC. Background Art

[0002] Cross-mode interference refers to the interference noise superimposed on the measured signal. In high-precision multi-rate signal acquisition systems such as sigma-delta ADC, cross-mode interference will affect the accuracy of the measurement results. It will directly act on the input end after being superimposed on the useful signal, resulting in measurement errors. The most common interference is 50Hz or 60Hz power frequency signals. To suppress cross-mode interference, a filter can be designed in the circuit to filter out the corresponding interference frequency signal.

[0003] Sigma-delta ADC is often used for high-precision signal measurement, and a digital filter circuit is usually integrated inside it. By setting an accurate notch point according to the frequency of the crosstalk signal, a digital filter can be designed through digital filtering technology to suppress such crosstalk interference signals.

[0004] The simplest notch filter structure is implemented using a second-order single-pole IIR filter, and its transfer function is as follows:

[0005]

[0006] Where ω0=2πf0 / f s , represents the notch digital frequency (rad); f0 is the notch frequency (Hz), fs is the sampling frequency (Hz), r represents the notch depth, the larger the number, the deeper the notch depth. This transfer function can calculate the specific coefficients through software, which is convenient for circuit implementation. The transfer function of the generated parameters is as follows:

[0007]

[0008] Its implementation structure is as follows Figure 1 As shown in Equation (2), it can be seen that the system structure of the IIR digital filter IIR is a zero-pole structure, that is, there is a feedback loop in the system structure, and the positions of the zeros and poles are determined by the coefficients. Therefore, the stability of the IIR filter system needs to be considered during the design, and it is more susceptible to the finite length algorithm problem; at the same time, for multi-rate signal processing applications such as Sigma-delta ADC, the calculation of the IIR filter has no advantage. Summary of the invention

[0009] The purpose of the present invention is to provide a common mode interference suppression circuit suitable for Sigma-delta ADC, which can optimize the suppression of quantization noise, device noise and 50Hz and 60Hz power frequency interference by selecting filters with different architectures according to the system rate.

[0010] The technical solution of the present invention is:

[0011] A common mode interference suppression circuit suitable for Sigma-delta ADC, comprising:

[0012] The input of the SINC3 filter is connected to the output of the Sigma-delta ADC modulator, and the output is connected to the gate MUX through a mean filter and a decimation module M1 in sequence;

[0013] The input end of the modified SINC3 filter is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate MUX through a mean filter and a decimation module M2 in sequence;

[0014] The input of the SINC4 filter is connected to the output of the Sigma-delta ADC modulator, and the output is connected to the gate MUX through a mean filter and a decimation module M3 in sequence;

[0015] The integrator, the input end is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate MUX through a mean filter and a decimation module M4 in sequence;

[0016] The gate MUX outputs the final signal of the Sigma-delta ADC.

[0017] Preferably, the SINC3 filter is composed of three first-order integrators, three comb filters and an extraction module. The SINC3 filter suppresses 50Hz and 60Hz power frequency crosstalk according to the output rate, and the output rate is between 4.17Hz and 12.5Hz.

[0018] Preferably, the modified SINC3 filter selects different SINC3 filter architectures and decimation rates according to different output rates and requirements, and the output rate ranges from 16.7 Hz to 39 Hz; when the output rate is selected to be 16.7 Hz, 50 Hz and 60 Hz power frequency crosstalk are simultaneously suppressed.

[0019] Preferably, the SINC4 filter is composed of 4 first-order integrators, 4 comb filters and an extraction module, and the output rate of the SINC4 filter is 50 Hz to 242 Hz.

[0020] Preferably, the integrator is composed of a first-level integrator and an extraction module, the integrator scaling factor k1 is implemented by a multiplier or a shift, and the filter output rate of the integration function is up to 470 Hz.

[0021] The advantages of the present invention are:

[0022] The whole common mode interference suppression circuit of the present invention is basically composed of an integrator, a comb, a mean filter and an extraction module, and only a small number of adders are needed to complete the circuit design in terms of algorithm. While suppressing common mode interference and noise, the area and power consumption of the circuit are greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments:

[0024] Figure 1 The figure shows a typical IIR notch filter direct type II implementation architecture diagram in the prior art;

[0025] Figure 2 The figure shows a principle block diagram of the common mode interference suppression circuit of the present invention;

[0026] Figure 3 The figure shows the implementation architecture of the mean filter according to the present invention;

[0027] Figure 4 The SI NC3 filter implementation architecture of the present invention;

[0028] Figure 5 The modified SI NC3 filter implementation architecture of the present invention;

[0029] Figure 6 The SI NC4 implementation architecture of the present invention;

[0030] Figure 7 The integration filter implementation architecture of the present invention;

[0031] Figure 8 This is an amplitude-frequency response diagram of the common mode interference suppression filter circuit of the present invention at an output rate of 4.17 Hz;

[0032] Fig. 9 This is an amplitude-frequency response diagram of the common mode interference suppression filter circuit of the present invention at an output rate of 16.7 Hz;

[0033] Fig.10 This is an amplitude-frequency response diagram of the common mode interference suppression filter circuit of the present invention at an output rate of 242 Hz;

[0034] Fig.11 This is the amplitude-frequency response diagram of the common mode interference suppression filter circuit of the present invention at an output rate of 470 Hz. DETAILED DESCRIPTION

[0035] like Figure 2 As shown, the sampling rate of the Sigma-delta ADC is taken as 64kHz as an example. The cross-mode interference suppression circuit applicable to the Sigma-delta ADC proposed in the present invention includes:

[0036] SI NC3 filter, the input end is connected to the output end of the Sigma-delta ADC modulator, and the output end is passed through a mean filter (such as Figure 3 As shown), the extraction module M1 is connected to the gate M UX;

[0037] The input end of the modified SI NC3 filter is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate M UX through a mean filter and a decimation module M2 in sequence;

[0038] SI NC4 filter, the input end is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate M UX through a mean filter and the extraction module M3 in sequence;

[0039] The integrator, the input end is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate M UX through a mean filter and a decimation module M4 in sequence;

[0040] The gate M UX outputs the final signal of the Sigma-delta ADC.

[0041] like Figure 4 As shown, the SI NC3 filter is composed of three first-order integrators, three comb filters and an extraction module. The SI NC3 filter suppresses 50Hz and 60Hz power frequency crosstalk according to the output rate, and the output rate is between 4.17Hz and 12.5Hz.

[0042] like Figure 5 As shown, the modified SINC3 filter selects different SINC3 filter architectures and decimation rates according to different output rates and requirements, and the output rate ranges from 16.7Hz to 39Hz; when the output rate is selected to be 16.7Hz, 50Hz and 60Hz power frequency crosstalk are simultaneously suppressed.

[0043] like Figure 6 As shown, the SI NC4 filter is composed of 4 first-order integrators, 4 comb filters and an extraction module, and the output rate of the SI NC4 filter is 50 Hz to 242 Hz.

[0044] like Figure 7 As shown, the integrator is composed of a 1-stage integrator and an extraction module, the integrator scaling factor k1 is realized by a multiplier or a shift, and the filter output rate of the integration function is up to 470 Hz.

[0045] It can be seen that the entire common mode interference suppression circuit is basically composed of an integrator, a comb filter, a mean filter, and an extraction module. In terms of algorithm, only a small number of adders are needed to complete the circuit design. While suppressing common mode interference and noise, the circuit area and power consumption are greatly reduced.

[0046] Figure 8-11 The figure shows the amplitude-frequency response simulation results of the common mode interference suppression filter of the present invention at several output rates. Figure 8 and Fig. 9 It can be seen that when the data output rate is not higher than 16.67 Hz, 50 Hz and 60 Hz power frequency interference can be suppressed simultaneously. The circuit described in the present invention is particularly suitable for multi-rate signal processing systems such as Sigma-delta ADC, and can achieve downsampling filter output while achieving cross-mode interference suppression.

[0047] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any modifications made according to the spirit of the main technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A common mode interference suppression circuit suitable for Sigma-delta ADC, characterized in that: include: The input of the SINC3 filter is connected to the output of the Sigma-delta ADC modulator, and the output is connected to the gate MUX through a mean filter and a decimation module M1 in sequence; The input end of the modified SINC3 filter is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate MUX through a mean filter and a decimation module M2 in sequence; The input of the SINC4 filter is connected to the output of the Sigma-delta ADC modulator, and the output is connected to the gate MUX through a mean filter and a decimation module M3 in sequence; The integrator, the input end is connected to the output end of the Sigma-delta ADC modulator, and the output end is connected to the gate MUX through a mean filter and a decimation module M4 in sequence; The gate MUX outputs the final signal of the Sigma-delta ADC.

2. The common mode interference suppression circuit suitable for Sigma-delta ADC according to claim 1, characterized in that: The SINC3 filter is composed of three first-order integrators, three comb filters and an extraction module. The SINC3 filter suppresses 50Hz and 60Hz power frequency crosstalk according to the output rate, and the output rate is between 4.17Hz and 12.5Hz.

3. The common mode interference suppression circuit suitable for Sigma-delta ADC according to claim 2, characterized in that: The modified SINC3 filter selects different SINC3 filter architectures and decimation rates according to different output rates and requirements, and the output rate ranges from 16.7 Hz to 39 Hz. When the output rate is 16.7 Hz, 50 Hz and 60 Hz power frequency crosstalk are suppressed simultaneously.

4. The common mode interference suppression circuit suitable for Sigma-delta ADC according to claim 3, characterized in that: The SINC4 filter is composed of four first-order integrators, four comb filters and an extraction module. The output rate of the SINC4 filter reaches 50 Hz to 242 Hz.

5. The common mode interference suppression circuit suitable for Sigma-delta ADC according to claim 4, characterized in that: The integrator is composed of a first-level integrator and an extraction module. The integrator scaling factor k1 is realized by a multiplier or a shifter. The filter output rate of the integration function is up to 470 Hz.

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