An audio data transmission bus interface for abnormal timing processing

Abstract

The present application provides an audio data transmission bus interface for abnormal timing processing, wherein the bus clock module is used to provide a fixed number of bus clocks in each frame synchronization cycle; the synchronization signal module is used to send a frame synchronization signal, and accumulate the error between the actual number of bus clocks in a specified number of frame synchronization cycles and the standard value of the bus clock, and generate a fault tolerance adjustment value based on the obtained error accumulation value; the abnormal detection module is used to generate a bus transmission situation based on the actual number of bus clocks and the fault tolerance adjustment value; the data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission situation when it is an abnormal transmission, and receive data according to the data receiving logic; the data sending module is used to determine the data sending logic according to the bus transmission situation when it is an abnormal transmission, and send data according to the data sending logic. By distinguishing the different degrees of clock abnormality, the influence of abnormal timing on data transmission can be reduced.

Description

Technical Field

[0001] The present application relates to the field of bus interface timing processing, and in particular to an audio data transmission bus interface for abnormal timing processing. Background Art

[0002] HDA (High Definition Audio) is an interface protocol released by Intel to support the transmission of high-quality voice in PC environment. Codec is a specific chip that supports this protocol to convert voice into data stream, or convert data stream into sound.

[0003] Its bus interface signal and timing are as follows Figure 1 As shown in the figure, bclk is the bus clock, which is usually 6M, 12M, or 24M; sync is the frame synchronization signal, which is fixed at 48K; sdo is the input data signal; sdi is the send data signal; and rstn is the bus reset signal. The codec sends and receives audio data through this bus interface.

[0004] The codec implements the above interface based on the frequency multiplication relationship between sync and bclk. A counter is used to detect whether the frequency multiplication relationship is satisfied. If it is not satisfied, a reset is generated to re-establish the link and initialize. The set cycle counter cnt is used to mark the corresponding relationship between the current clock bclk and sync. The implementation structure is as follows Figure 2 shown.

[0005] Figure 2 The implementation structure is for Figure 3 In the case 1 timing where the sync and bclk frequency ratio is normal, data can be sent and received correctly. However, in the case 2 timing where one or more bclk cycles are missing in one sync cycle due to interference such as ESD (Electrostatic Discharge), and in the case 3 timing where one bclk or more bclk cycles are added, it is judged as abnormal timing, triggering a reset and bus initialization request.

[0006] In actual circuits, the abnormal timing of case 2 and case 3 caused by interference such as ESD only affects the transmission of one or more frames of data. After the interference disappears, the bus can continue to send and receive data normally. The above reset processing method will cause a long interruption in audio data transmission, and the processing cost is too high. Summary of the invention

[0007] In view of the above problems, the present application is proposed to provide an audio data transmission bus interface for abnormal timing processing that overcomes the above problems or at least partially solves the above problems. The data transmission bus interface includes a bus clock module, a synchronization signal module, an abnormality detection module, a data receiving module and a data sending module. The bus clock module, the abnormality detection module, the data receiving module and the data sending module are respectively connected to the synchronization signal module signal;

[0008] The bus clock module is used to provide a fixed number of bus clocks in each frame synchronization period;

[0009] The synchronization signal module is used to send a frame synchronization signal, accumulate the error between the actual number of bus clocks in a specified number of frame synchronization cycles and the standard value of the bus clock to generate an error accumulation value, and adjust the fault tolerance value according to the error accumulation value to generate a fault tolerance adjustment value;

[0010] The abnormality detection module is used to generate the bus transmission status of the bus clock module according to the actual number of bus clocks, the fault tolerance adjustment value and the bus clock standard value; wherein the bus transmission status includes normal transmission and abnormal transmission;

[0011] The data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission situation when the transmission is abnormal, and receive data according to the data receiving logic;

[0012] The data sending module is used to determine the data sending logic according to the bus transmission situation when the transmission is abnormal, and send data according to the data sending logic.

[0013] Furthermore, the bus clock module includes a clock detector for detecting whether the clock is stopped.

[0014] Further, the synchronization signal module includes a counting unit, a calculation unit and an adjustment unit;

[0015] The counting unit is used to calculate the number of frame cycles and the number of actual bus clocks of the synchronization cycle;

[0016] The calculation unit is used to determine the error of the corresponding frame synchronization period according to the actual number of bus clocks in the frame synchronization period and the standard value of the bus clock, and accumulate the errors of a specified number of frame synchronization periods to generate the error accumulation value;

[0017] The adjustment unit generates the error tolerance adjustment value according to the error accumulation value.

[0018] Further, the counting unit includes a frame counter and a frame period counter;

[0019] The frame counter is used to store the frame number parameter and calculate the frame period number, and the frame period counter is used to calculate the actual bus clock number within the frame synchronization period.

[0020] Furthermore, the calculation unit includes an error accumulator, which is used to accumulate the difference between the actual number of bus clocks in a specified number of frame synchronization cycles and the standard value of the bus clock. When the number of frame cycles is equal to the frame number parameter, a new round of accumulation is performed.

[0021] Further, the adjustment unit includes a parameter register and a fault tolerance adjustment subunit;

[0022] The parameter register is used to store threshold parameters and step parameters;

[0023] The fault tolerance adjustment subunit is used to generate the fault tolerance adjustment value according to the step parameter, the threshold parameter and the error accumulation value.

[0024] Further, the fault-tolerant adjustment subunit includes a fault-tolerant register and a first comparator;

[0025] The fault tolerance register is used to store the initial fault tolerance value;

[0026] The first comparator is used for comparing the error accumulation value with the threshold parameter to generate a first comparison result, and adjusting the initial fault tolerance value according to the first comparison result and the step parameter to generate the fault tolerance adjustment value.

[0027] Further, the abnormality detection module includes a second comparator, a detection unit and a signal generation unit;

[0028] The second comparator is used to generate a calculation result according to the actual number of bus clocks in the frame synchronization period and the fault tolerance adjustment value, and compare the calculation result with the bus clock standard value to generate a second comparison result;

[0029] The detection unit is used to determine the current frame bus transmission status according to the second comparison result;

[0030] The signal generating unit is used to generate a control signal when abnormal transmission occurs.

[0031] Further, the data receiving module includes a parameter control unit and a receiving logic unit;

[0032] The parameter control unit is used to adjust the control parameter according to the control signal when abnormal transmission occurs;

[0033] The receiving logic unit is used to determine the data receiving logic according to the bus transmission situation, and perform data reception according to the data receiving logic.

[0034] Further, the data sending module includes a feedback unit and a sending logic unit;

[0035] The feedback unit is used to determine feedback information according to the bus transmission situation when the transmission is abnormal;

[0036] The sending logic unit is used to determine the data sending logic according to the feedback information when the transmission is abnormal, and send data according to the data sending logic.

[0037] This application has the following advantages:

[0038] In the embodiment of the present application, with respect to the technical problem in the prior art that "the reset processing method will cause a long interruption in audio data transmission and the processing cost is too high", the present application provides a solution to the interface fault tolerance design structure with a self-adjusting function, specifically: the bus clock module is used to provide a fixed number of bus clocks in each frame synchronization period; the synchronization signal module is used to send a frame synchronization signal, and accumulate the error between the actual number of bus clocks in a specified number of frame synchronization periods and the standard value of the bus clock to generate an error accumulation value, and adjust the fault tolerance value according to the error accumulation value to generate a fault tolerance adjustment value; the abnormality detection module is used to generate the bus transmission status of the bus clock module according to the actual number of bus clocks, the fault tolerance adjustment value and the standard value of the bus clock; wherein the bus transmission status includes normal transmission and abnormal transmission; the data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission status when it is an abnormal transmission, and receive data according to the data receiving logic; the data sending module is used to determine the data sending logic according to the bus transmission status when it is an abnormal transmission, and send data according to the data sending logic. By distinguishing the different degrees of clock abnormality, the influence of abnormal timing on data transmission can be reduced. The audio data transmission bus interface for timing abnormality processing proposed by the present invention can effectively increase the fault tolerance of the bus to abnormal interference, reduce the probability of transmission interruption, and improve the continuity of audio data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the description of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 This is a HDA interface bus timing diagram provided by an embodiment of the present application;

[0041] Figure 2 This is a structural diagram of an HDA bus interface implementation provided by an embodiment of the present application;

[0042] Figure 3 are three bus timing diagrams provided by an embodiment of the present invention;

[0043] Figure 4 This is a HDA interface fault tolerance design structure diagram provided by an embodiment of the present invention;

[0044] Figure 5 The present invention is a schematic diagram of the structure of an audio data transmission bus interface for abnormal timing processing provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to make the objects, features and advantages of the present application more obvious and understandable, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0046] The inventors have analyzed the prior art and found that the reasons why the audio data transmission is interrupted for a long time in the prior reset processing method when facing abnormal timing in case 2 and case 3 caused by ESD interference are as follows:

[0047] 1. If Figure 3 As shown in the figure, a reset is triggered immediately when a sync cycle is detected to have a missing or extra bclk cycle. Although this reset method can ensure that the system state is quickly restored when severe interference occurs, it also increases the sensitivity to slight or short-term interference. ESD interference may only temporarily affect the transmission of a few frames of data, but the stability of the entire system is not threatened. Therefore, this reset method may cause unnecessary system reset, thereby interrupting normal audio data transmission.

[0048] 2. Once the reset request is triggered, the system needs to go through a series of initialization processes before it can re-enter the normal working state. This initialization process may include reconfiguring bus parameters, re-establishing synchronization signals, reloading necessary data, etc. These operations all take a certain amount of time to complete, so during the reset process, the transmission of audio data will be completely interrupted.

[0049] In an actual circuit, when the HDA master sends bclk and sync, it strictly follows its inherent frequency multiplication relationship. The reasons for cases 2 and 3 mostly come from sudden ESD or other interferences. The inventor found that if the loss or increase of the clock signal is within a certain value range, no reset and initialization requests are made, and the subsequent sync signal synchronization logic is waited for to re-transmit and receive data, which can reduce the impact of the above timing on data transmission.

[0050] Refer to Figure 4 , which is a structural diagram of an HDA interface fault tolerance design studied by the inventor. In a normal frequency multiplication relationship corresponding to one frame synchronization period, the number of bus clock cycles is denoted as Nr, and the fault tolerance value is configured as Tv. In the interface fault tolerance design structure without configuring the self-adjustment function, the number of bus clocks N within one frame synchronization period should satisfy (Nr - Tv) < N < (Nr + Tv) to avoid triggering the error Err and generating reset and initialization requests. Otherwise, Err is triggered and reset and initialization requests are generated. For example, when the bus clock is 24M, one frame synchronization period corresponds to 500 bus clocks. If the fault tolerance value is configured as 10, then within one frame synchronization period, 491 - 509 bus clocks are not judged as incorrect timing, do not trigger Err, and do not generate reset and initialization requests. Beyond this range, reset and initialization requests are generated. This structural design can increase the fault tolerance performance of the bus to abnormal interferences to a certain extent.

[0051] To further improve the fault tolerance performance of the bus to abnormal interferences and the continuity of audio data transmission, the inventor provides an audio data transmission bus interface for abnormal timing processing.

[0052] It should be noted that this application can be used for HDA and any similar timing processing of serial or parallel interfaces containing synchronous clock signals other than HDA.

[0053] Refer to Figure 5 , which shows an audio data transmission bus interface for abnormal timing processing provided by an embodiment of the present application; the data transmission bus interface includes a bus clock module, a synchronization signal module, an abnormal detection module, a data receiving module, and a data sending module, and the bus clock module, the abnormal detection module, the data receiving module, and the data sending module are respectively signal-connected to the synchronization signal module;

[0054] The bus clock module is used to provide a fixed number of bus clocks in each frame synchronization period;

[0055] The synchronization signal module is used to send a frame synchronization signal, accumulate the error between the actual number of bus clocks in a specified number of frame synchronization cycles and the standard value of the bus clock to generate an error accumulation value, and adjust the fault tolerance value according to the error accumulation value to generate a fault tolerance adjustment value;

[0056] The abnormality detection module is used to generate the bus transmission status of the bus clock module according to the actual number of bus clocks, the fault tolerance adjustment value and the bus clock standard value; wherein the bus transmission status includes normal transmission and abnormal transmission;

[0057] The data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission situation when the transmission is abnormal, and receive data according to the data receiving logic;

[0058] The data sending module is used to determine the data sending logic according to the bus transmission situation when the transmission is abnormal, and send data according to the data sending logic.

[0059] In the embodiment of the present application, with respect to the technical problem in the prior art that "the reset processing method will cause a long interruption in audio data transmission and the processing cost is too high", the present application provides a solution to the interface fault tolerance design structure with a self-adjusting function, specifically: the bus clock module is used to provide a fixed number of bus clocks in each frame synchronization period; the synchronization signal module is used to send a frame synchronization signal, and accumulate the error between the actual number of bus clocks in a specified number of frame synchronization periods and the standard value of the bus clock to generate an error accumulation value, and adjust the fault tolerance value according to the error accumulation value to generate a fault tolerance adjustment value; the abnormality detection module is used to generate the bus transmission status of the bus clock module according to the actual number of bus clocks, the fault tolerance adjustment value and the standard value of the bus clock; wherein the bus transmission status includes normal transmission and abnormal transmission; the data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission status when it is an abnormal transmission, and receive data according to the data receiving logic; the data sending module is used to determine the data sending logic according to the bus transmission status when it is an abnormal transmission, and send data according to the data sending logic. By distinguishing the different degrees of clock abnormality, the influence of abnormal timing on data transmission can be reduced. The audio data transmission bus interface for timing abnormality processing proposed by the present invention can effectively increase the fault tolerance of the bus to abnormal interference, reduce the probability of transmission interruption, and improve the continuity of audio data transmission.

[0060] Next, an audio data transmission bus interface for abnormal timing processing in this exemplary embodiment will be further described.

[0061] In an embodiment of the present application, the bus clock module includes a clock detector for detecting whether the clock is stopped.

[0062] It should be noted that the bus clock module is used to synchronize the bit transmission of audio data. At the rising or falling edge of each bus clock, a certain bit of audio data is transmitted. The bus clock module supports multiple frequencies, such as 6MHz, 12MHz, 24MHz, etc. The specific frequency depends on the system design requirements and the transmission rate of audio data. The bus clock module includes a clock detector. The frame synchronization signal drives the clock detector to start working and detect whether the internal clock stops. If the internal clock stops, the signal is sent to the abnormality detection module.

[0063] In an embodiment of the present application, the synchronization signal module includes a counting unit, a calculation unit and an adjustment unit;

[0064] The counting unit is used to calculate the number of frame cycles and the number of actual bus clocks of the synchronization cycle;

[0065] The calculation unit is used to determine the error of the corresponding frame synchronization period according to the actual number of bus clocks in the frame synchronization period and the standard value of the bus clock, and accumulate the errors of a specified number of frame synchronization periods to generate the error accumulation value;

[0066] The adjustment unit generates the error tolerance adjustment value according to the error accumulation value.

[0067] It should be noted that the synchronization signal module is used to provide a frame synchronization signal to indicate the start of an audio frame or data block; it is fixed at 48kHz; the synchronization signal module ensures that the sending and receiving devices start processing the frames or blocks of audio data at the same time point, thereby maintaining audio synchronization.

[0068] In an embodiment of the present application, the counting unit includes a frame counter and a frame period counter;

[0069] The frame counter is used to store the frame number parameter and calculate the frame period number, and the frame period counter is used to calculate the actual bus clock number within the frame synchronization period.

[0070] It should be noted that when a frame synchronization signal is received, the frame counter calculates the number of frame cycles and the actual number of bus clocks within the frame synchronization cycle, and the frame cycle counter calculates the difference between the actual number of bus clocks within the frame synchronization cycle and the standard value of the bus clock in the frame synchronization cycle.

[0071] The frame counter stores a frame number parameter, which is a custom data used to determine the timing of the cumulative counter to re-accumulate, that is, when the current frame period number is the same as the frame number parameter value, the control error accumulator restarts a new accumulation calculation. The frame period number is the number of the current frame period.

[0072] The frame cycle counter stores the bus clock standard value of the frame synchronization cycle, which is used to compare with the actual bus clock number of the frame synchronization cycle to obtain the bus clock error of each frame synchronization cycle.

[0073] In one embodiment of the present application, the calculation unit includes an error accumulator, which is used to accumulate the difference between the actual number of bus clocks of a specified number of frame synchronization cycles and the standard value of the bus clock. When the number of frame cycles is equal to the frame number parameter, a new round of accumulation is performed.

[0074] As an example, the frame synchronization signal drives the frame counter to start counting. When the number of the current frame period counted by the frame counter is the same as the frame number parameter, the error accumulator is controlled to restart a new accumulation calculation, thereby achieving the purpose of dynamically controlling the error calculation process. The frame period counter is used to count the number of bus clocks during a frame synchronization period, and uses this value to control the data receiving and sending logic. At the same time, at the beginning of the next frame synchronization, the difference between the count value and the standard value of the bus clock of the frame synchronization period is accumulated through the error accumulator to obtain a new error accumulation value.

[0075] In a specific implementation, the initial state is: frame counter = 0, error accumulator = 0, and frame cycle counter is ready to start counting. After receiving the frame synchronization signal, the receiving end drives the frame counter to start counting, and the frame cycle counter starts to record the number of bus clocks. If each frame contains 1024 data bits, the frame counter will start counting from 0, and the counter will increase by 1 after each frame of data is received. Assuming that the frequency of the bus clock is 1MHz (i.e., 1 million clock cycles per second), and the transmission time of a frame of data is 1ms (i.e., 1000 microseconds), the standard value of the frame cycle counter should be 1000. At the receiving end, whenever the value of the frame counter is the same as the preset frame number parameter (set to N), the error accumulator will restart a new accumulation calculation. Assuming N=10, that is, after receiving 10 frames of data, the error accumulator will calculate the difference between the frame cycle counter value and the standard value of the bus clock (1000) during these 10 frames, and accumulate this difference to the previous error accumulation value. The frame counter is reset to 0, ready to receive the next set of 10 frames of data, and the error accumulator continues to monitor and accumulate new error values.

[0076] In one embodiment of the present application, the adjustment unit includes a parameter register and a fault tolerance adjustment subunit;

[0077] The parameter register is used to store threshold parameters and step parameters;

[0078] The fault tolerance adjustment subunit is used to generate the fault tolerance adjustment value according to the step parameter, the threshold parameter and the error accumulation value.

[0079] It should be noted that the threshold parameter and the step parameter are both used to adjust the fault tolerance value. According to the current hardware circuit working environment, the fault tolerance adjustment subunit sets different fault tolerance configuration values ​​to reduce the impact of abnormal timing to the optimal state.

[0080] In one embodiment of the present application, the fault tolerance adjustment subunit includes a fault tolerance register and a first comparator;

[0081] The fault tolerance register is used to store the initial fault tolerance value;

[0082] The first comparator is used for comparing the error accumulation value with the threshold parameter to generate a first comparison result, and adjusting the initial fault tolerance value according to the first comparison result and the step parameter to generate the fault tolerance adjustment value.

[0083] As an example, the above-mentioned bus clock accumulated error value is compared with the threshold parameter through the first comparator. When it is greater than the positive threshold, the fault tolerance value is increased by 1 step parameter to increase the fault tolerance capability. Otherwise, the step parameter is reduced by 1 to reduce the fault tolerance capability, so as to realize dynamic adjustment of the fault tolerance parameter.

[0084] In a specific implementation, the positive threshold is set to 100, indicating that when the error accumulation value exceeds 100, it is considered that the system needs to increase the fault tolerance. The step parameter is set to 5, indicating that each time the fault tolerance value is adjusted, the step amount of increase or decrease is 5. The initial fault tolerance value is set to 50, indicating the initial fault tolerance of the system. If the value of the error accumulator is greater than the positive threshold 100, it is considered that the current error of the system is large and the fault tolerance needs to be increased. At this time, the initial fault tolerance value is increased by 1 step parameter 5, that is, the fault tolerance adjustment value is = 50+5=55. If the value of the error accumulator is close enough to 0, it is considered that the system is currently relatively stable and the fault tolerance can be appropriately reduced to optimize the performance. At this time, the initial fault tolerance value is reduced by 1 step parameter 5, that is, the fault tolerance adjustment value = 50-5=45. In the next few rounds, if the error continues to remain at a high level, the fault tolerance value will continue to increase; if the error decreases, the fault tolerance value will decrease.

[0085] In an embodiment of the present application, the abnormality detection module includes a second comparator, a detection unit and a signal generation unit;

[0086] The second comparator is used to generate a calculation result according to the actual number of bus clocks in the frame synchronization period and the fault tolerance adjustment value, and compare the calculation result with the bus clock standard value to generate a second comparison result;

[0087] The detection unit is used to determine the current frame bus transmission status according to the second comparison result; wherein the bus transmission status includes normal transmission and abnormal transmission;

[0088] The signal generating unit is used to generate a control signal when abnormal transmission occurs.

[0089] It should be noted that the second comparator adds the actual number of bus clocks in the frame synchronization period obtained by the frame cycle counter to the fault tolerance adjustment value to obtain a second comparison result; or, subtracts the actual number of bus clocks in the frame synchronization period from the fault tolerance adjustment value to obtain a second comparison result.

[0090] The detection unit compares the sum of the actual number of bus clocks in the frame synchronization period obtained by the frame cycle counter and the fault tolerance adjustment value with the bus clock standard value. If their sum is still less than the bus clock standard value, it is determined that the current frame bus transmission is erroneous; or, compares the difference between the actual number of bus clocks in the frame synchronization period and the fault tolerance adjustment value with the bus clock standard value. If their difference is still greater than the bus clock standard value, it is determined that the current frame bus transmission is erroneous. When it is determined that the current frame bus transmission is erroneous, the signal generation unit generates a control signal and sends the control signal to the data receiving module.

[0091] In an embodiment of the present application, the data receiving module includes a parameter control unit and a receiving logic unit;

[0092] The parameter control unit is used to adjust the control parameter according to the control signal when abnormal transmission occurs;

[0093] The receiving logic unit is used to determine the data receiving logic according to the bus transmission situation, and perform data reception according to the data receiving logic.

[0094] It should be noted that when the parameter control unit receives the control signal, the frame number parameter, bus clock standard value, threshold parameter, step parameter and fault tolerance initial value can be adjusted according to the bus transmission situation. When it is an abnormal transmission, the receiving logic unit determines the data receiving logic to receive data according to the bus transmission situation.

[0095] In an embodiment of the present application, the data sending module includes a feedback unit and a sending logic unit;

[0096] The feedback unit is used to determine feedback information according to the bus transmission situation when the transmission is abnormal;

[0097] The sending logic unit is used to determine the data sending logic according to the feedback information when the transmission is abnormal, and send data according to the data sending logic.

[0098] It should be noted that, when it is an abnormal transmission, the feedback unit generates feedback information such as interruption, which is sent through the sending logic unit.

[0099] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0100] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0101] The above is a detailed introduction to an audio data transmission bus interface for abnormal timing processing provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An audio data transmission bus interface for abnormal timing processing, characterized in that: The data transmission bus interface comprises a bus clock module, a synchronization signal module, an abnormality detection module, a data receiving module and a data sending module, wherein the bus clock module, the abnormality detection module, the data receiving module and the data sending module are respectively connected to the synchronization signal module by signal; The bus clock module is used to provide a fixed number of bus clocks in each frame synchronization period; The synchronization signal module is used to send a frame synchronization signal, accumulate the error between the actual number of bus clocks in a specified number of frame synchronization cycles and the standard value of the bus clock to generate an error accumulation value, and adjust the fault tolerance value according to the error accumulation value to generate a fault tolerance adjustment value; The abnormality detection module is used to generate the bus transmission status of the bus clock module according to the actual number of bus clocks, the fault tolerance adjustment value and the bus clock standard value; wherein the bus transmission status includes normal transmission and abnormal transmission; The data receiving module is used to adjust the control parameters and determine the data receiving logic according to the bus transmission situation when the transmission is abnormal, and receive data according to the data receiving logic; The data sending module is used to determine the data sending logic according to the bus transmission situation when the transmission is abnormal, and send data according to the data sending logic.

2. The audio data transmission bus interface according to claim 1, characterized in that: The bus clock module includes a clock detector for detecting whether the clock is stopped.

3. The audio data transmission bus interface according to claim 1, characterized in that: The synchronization signal module includes a counting unit, a calculation unit and an adjustment unit; The counting unit is used to calculate the number of frame cycles and the number of actual bus clocks of the synchronization cycle; The calculation unit is used to determine the error of the corresponding frame synchronization period according to the actual number of bus clocks in the frame synchronization period and the standard value of the bus clock, and accumulate the errors of a specified number of frame synchronization periods to generate the error accumulation value; The adjustment unit generates the error tolerance adjustment value according to the error accumulation value.

4. The audio data transmission bus interface according to claim 3, characterized in that: The counting unit includes a frame counter and a frame period counter; The frame counter is used to store the frame number parameter and calculate the frame period number, and the frame period counter is used to calculate the actual bus clock number within the frame synchronization period.

5. The audio data transmission bus interface according to claim 3, characterized in that: The calculation unit includes an error accumulator, which is used to accumulate the difference between the actual number of bus clocks of a specified number of frame synchronization cycles and the standard value of the bus clock. When the number of frame cycles is equal to the frame number parameter, a new round of accumulation is performed.

6. The audio data transmission bus interface according to claim 3, characterized in that: The adjustment unit includes a parameter register and a fault-tolerant adjustment subunit; The parameter register is used to store threshold parameters and step parameters; The fault tolerance adjustment subunit is used to generate the fault tolerance adjustment value according to the step parameter, the threshold parameter and the error accumulation value.

7. The audio data transmission bus interface according to claim 6, characterized in that: The fault-tolerant adjustment subunit includes a fault-tolerant register and a first comparator; The fault tolerance register is used to store the initial fault tolerance value; The first comparator is used for comparing the error accumulation value with the threshold parameter to generate a first comparison result, and adjusting the initial fault tolerance value according to the first comparison result and the step parameter to generate the fault tolerance adjustment value.

8. The audio data transmission bus interface according to claim 1, characterized in that: The abnormality detection module includes a second comparator, a detection unit and a signal generation unit; The second comparator is used to generate a calculation result according to the actual number of bus clocks in the frame synchronization period and the fault tolerance adjustment value, and compare the calculation result with the bus clock standard value to generate a second comparison result; The detection unit is used to determine the current frame bus transmission status according to the second comparison result; The signal generating unit is used to generate a control signal when abnormal transmission occurs.

9. The audio data transmission bus interface according to claim 8, characterized in that: The data receiving module includes a parameter control unit and a receiving logic unit; The parameter control unit is used to adjust the control parameter according to the control signal when abnormal transmission occurs; The receiving logic unit is used to determine the data receiving logic according to the bus transmission situation, and perform data reception according to the data receiving logic.

10. The audio data transmission bus interface according to claim 1, characterized in that: The data sending module includes a feedback unit and a sending logic unit; The feedback unit is used to determine feedback information according to the bus transmission situation when the transmission is abnormal; The sending logic unit is used to determine the data sending logic according to the feedback information when the transmission is abnormal, and send data according to the data sending logic.

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