Method for manufacturing semiconductor device, semiconductor device and memory system

Abstract

The embodiment of the invention provides a preparation method of a semiconductor device, the semiconductor device and a memory system. The method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a stacking structure, a contact connecting part penetrating through the stacking structure and a grid line gap structure, and the grid line gap structure is provided with a protruding part protruding out of the stacking structure in the stacking direction of the stacking structure; the semiconductor structure further comprises a semiconductor layer covering the stacking structure, the contact connection part and the protruding part of the grid line gap structure. Removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion portion; at least one part of the protruding part is removed; and forming a dielectric layer covering the semiconductor layer, the contact connection part and the grid line gap structure.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, and a memory system. Background Art

[0002] In the semiconductor manufacturing process, the planarization process is one of the indispensable process steps. The flatness of the wafer surface will affect the yield of the product. In the related art, the method of wafer surface planarization must go through at least multiple steps such as etching and chemical mechanical polishing (CMP). The process flow is relatively cumbersome and the cost is high. Therefore, it is necessary to explore a method for manufacturing semiconductor devices that can achieve wafer surface planarization and have a simple structure, as well as semiconductor devices and memory systems. Summary of the invention

[0004] The various aspects disclosed in this application and the embodiments included in the various aspects are used to solve or partially solve the above-mentioned or other deficiencies in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor structure, wherein the semiconductor structure comprises a stacking structure, a contact connection portion penetrating the stacking structure, and a gate line gap structure, wherein the gate line gap structure has a protruding portion protruding from the stacking structure along a stacking direction of the stacking structure, and the semiconductor structure further comprises a semiconductor layer covering the stacking structure, the contact connection portion, and the protruding portion of the gate line gap structure; removing at least a portion of the semiconductor layer to expose the contact connection portion and the protruding portion; removing at least a portion of the protruding portion; and forming a dielectric layer covering the semiconductor layer, the contact connection portion, and the gate line gap structure.

[0006] In one embodiment, removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion includes: forming a patterned mask layer on a surface of the semiconductor layer away from the stacked structure, the mask layer including a first opening and a second opening, wherein the first opening exposes a portion of the semiconductor layer covering the contact connection portion, and the second opening exposes a portion of the semiconductor layer covering the gate line gap structure; and etching the semiconductor layer through the first opening and the second opening to expose the contact connection portion and the protrusion.

[0007] In one embodiment, on a plane perpendicular to the stacking direction, a projection of the first opening covers a projection of the contact connection portion.

[0008] In one embodiment, the protrusion has a first end away from the stacking structure and a second end close to the stacking structure; and on a plane perpendicular to the stacking direction, the projection of the second end covers the projection of the second opening, and the projection of the second opening covers the projection of the first end.

[0009] In one embodiment, after at least a portion of the protrusion is removed, a size of the protrusion along the stacking direction is less than or equal to 150 nm.

[0010] In a second aspect, an embodiment of the present application provides a semiconductor device, comprising: a stacked structure having a core region and a contact connection region; a contact connection portion located in the contact connection region and passing through the contact connection region; a gate line gap structure located in the core region and passing through the core region; a semiconductor layer covering a first side surface of the stacked structure and being disconnected at the position of the contact connection portion and the gate line gap structure; and a dielectric layer covering the semiconductor layer, the contact connection portion and the gate line gap structure.

[0011] In one embodiment, the gate line gap structure further includes a portion extending into the dielectric layer, and a size of the portion of the gate line gap structure extending into the dielectric layer along the stacking direction is less than or equal to 150 nm.

[0012] In one embodiment, the material of the semiconductor layer includes a polysilicon layer, and the material of the dielectric layer includes silicon dioxide.

[0013] In one embodiment, the semiconductor device further includes: a peripheral circuit structure located on a second side surface of the stacked structure opposite to the first side surface and electrically connected to the core region and the contact connection region.

[0014] In a third aspect, an embodiment of the present application provides a memory system, comprising: a three-dimensional memory, comprising at least one semiconductor device as described in the above embodiment; and a controller coupled to the three-dimensional memory, for controlling the three-dimensional memory to store data.

[0015] According to the method for manufacturing a semiconductor device of the embodiment of the present application, a second opening that can expose the raised portion of the gate line gap structure covering the semiconductor layer is added to the mask layer, and the raised portion is exposed through the second opening and the height of the raised portion is reduced, thereby improving the morphology of the surface of the dielectric layer, thereby saving the chemical mechanical polishing process, and also reducing the thickness requirement for the dielectric layer, simplifying the preparation method of the semiconductor device, and saving manufacturing costs.

[0016] In addition, according to the semiconductor device and memory system of the embodiments of the present application, by controlling the size of the portion of the gate line gap structure extending into the dielectric layer along the stacking direction to be within a preset threshold range, the problem of excessive undulations on the surface of the dielectric layer covering the semiconductor layer, the contact connection portion and the gate line gap structure is improved, the chemical mechanical polishing process is saved, the thickness requirement for the dielectric layer is reduced, the preparation method of the semiconductor device is simplified, and the manufacturing cost is saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0018] Figure 1 is a schematic flow chart of manufacturing a semiconductor device according to an embodiment of the related art;

[0019] FIG. 2A to FIG. 2E is a schematic diagram of an intermediate structure of a semiconductor device during a manufacturing process according to an embodiment of the related art;

[0020] Figure 3 is a method for preparing a semiconductor device in another embodiment of the present disclosure;

[0021] FIG. 4A to FIG. 4D is a schematic diagram of an intermediate structure of a semiconductor device during a manufacturing process according to another embodiment of the present disclosure;

[0022] Figure 5 is a system block diagram of a memory system according to an exemplary embodiment of the present application; and

[0023] Fig. 6A and Figure 6B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way. Throughout the specification, the same figure numerals refer to the same elements.

[0025] In the drawings, the thickness, size and shape of components have been slightly adjusted for ease of explanation. The drawings are only examples and are not drawn strictly to scale.

[0026] In general, a term can be understood, at least in part, from its use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "the" can also be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context.

[0027] Relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, relative terms are intended to include different orientations of the device. In an exemplary embodiment, when the device in one of the figures is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, depending on the specific orientation of the figure, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, when the device in one of the figures is turned over, the element described as being "below" or "below" the other element will then be oriented "above" the other element. Therefore, the exemplary term "below" or "below" can include both upper and lower orientations.

[0028] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire superstructure or substructure, or may have a range that is smaller than the substructure or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer may be between the top surface and the bottom surface of the continuous structure or between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above it and / or below it. A layer may include multiple layers.

[0029] When “connected” or “coupled” is used in the present application, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0030] It should also be understood that expressions such as "include", "comprising", "having", "including" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or their combinations. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0031] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0033] In the manufacturing process of three-dimensional memory (for example, 3D NAND memory), the gate line gap structure has a portion extending into the substrate. After the substrate is removed, the gate line gap structure has a protruding portion protruding from the surface of the stacked structure, thereby causing the subsequently formed dielectric layer to have a large undulating morphology. In order to bring out the electrical properties of the three-dimensional memory, it is necessary to flatten the surface of the dielectric layer (i.e., flatten the wafer surface) for subsequent preparation of metal wiring. The surface flattening method in the related art requires at least etching, chemical mechanical polishing (CMP) and other steps, and the process flow is relatively cumbersome and the cost is high.

[0034] Figure 1 FIG. 1 shows a schematic flow chart of manufacturing a semiconductor device according to the related technology of the present application. Figure 1 As shown, the method 1000 for manufacturing a semiconductor device provided by the related technology of the present application may include:

[0035] S110, providing a semiconductor structure, wherein the semiconductor structure includes a stacking structure, a contact connection portion penetrating the stacking structure, and a gate line gap structure, wherein the gate line gap structure has a protruding portion protruding from the stacking structure along a stacking direction of the stacking structure, and the semiconductor structure also includes a semiconductor layer covering the stacking structure, the contact connection portion, and the protruding portion of the gate line gap structure.

[0036] S120, removing at least a portion of the semiconductor layer to expose the contact connection portion.

[0037] S130, forming a dielectric layer covering the semiconductor layer and the contact connection portion.

[0038] S140, performing a planarization process on the dielectric layer.

[0039] The following will be combined FIG. 2A to FIG. 2EThe specific process steps S110-S140 of the method for manufacturing the semiconductor device are described in detail.

[0040] Step S110

[0041] Figure 2A The figure shows a specific structural example of a semiconductor structure provided in step S110 according to one embodiment of the present application.

[0042] like Figure 2A As shown, the semiconductor structure provided in step S210 may include a stacked structure 10, a contact connection portion 40 penetrating the stacked structure 10, and a gate line gap structure 30, wherein the gate line gap structure 30 has a protrusion 301 protruding from the stacked structure 10 along the stacking direction of the stacked structure 10, and the semiconductor structure also includes a semiconductor layer 20 covering the stacked structure 10, the contact connection portion 40, and the protrusion 301 of the gate line gap structure 30. The semiconductor structure may be suitable for manufacturing semiconductor devices such as three-dimensional memories. Exemplarily, the semiconductor structure may also include a plurality of channel structures 101. In the three-dimensional memory, the region where the channel structures 101 are located is generally referred to as the core region of the three-dimensional memory, and the region where the contact connection portion 40 is located is generally referred to as the contact connection region of the three-dimensional memory.

[0043] In some embodiments of the present application, along the stacking direction of the stacked structure 10 , a dimension H of the protrusion 301 of the gate line gap structure 30 protruding from the semiconductor layer 20 may be in a range of 200 nm to 500 nm.

[0044] In some embodiments of the present application, the material of the gate line gap structure 30 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0045] In some embodiments of the present application, the contact connection portion 40 penetrates the stacked structure 10 and serves as an electrical connection. For example, the contact connection portion 40 may be prepared by first forming a conductive channel, and then filling the conductive channel with a conductive material to form a conductive channel column. For example, the material of the conductive channel column may be a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). In some embodiments, the contact connection portion 40 may only include a solid conductive channel column; in other embodiments, such as Figure 2A As shown, the contact connection portion 40 may further include a filling portion 401 , that is, the filling portion 401 is made inside the conductive channel column, and the material of the filling portion 401 may be an insulating material.

[0046] In some embodiments of the present application, the semiconductor layer 20 may include multiple layers of different materials. Figure 2A Only two layers are shown exemplarily. The material of the semiconductor layer 20 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0047] In some embodiments of the present application, the semiconductor structure provided in step S110 can be used to manufacture semiconductor devices such as three-dimensional memory. The semiconductor structure can also include a peripheral circuit structure 50, and the peripheral circuit structure 50 is electrically connected to the core area and contact connection area of ​​the three-dimensional memory through multiple interconnection contacts 501. Therefore, in the process of preparing a semiconductor device such as a three-dimensional memory, many steps such as preparing the core area and the peripheral circuit structure 50 of the three-dimensional memory are also included. However, in order to highlight the key points of the invention, the present application does not describe the steps for forming the above-mentioned semiconductor structure. Those skilled in the art can determine the preparation methods related to the preparation of the semiconductor device disclosed in the present application and other structures of the three-dimensional memory based on their knowledge. In the embodiments and process flow of the present application, only the intermediate of forming a three-dimensional memory having a core area and a contact connection area is shown.

[0048] Step S120

[0049] At least a portion of the semiconductor layer 20 is removed to expose the contact connection portion 40 .

[0050] According to one embodiment of the present application, Figure 2B As shown, a patterned mask layer 60 is formed on the surface of the semiconductor layer 20 away from the stacked structure 10, and the mask layer 60 has a first opening 601 that exposes the semiconductor layer 20 and covers the contact connection portion 40. Exemplarily, the mask layer 60 is a photoresist layer, and the first opening 601 can be formed by a photolithography process. Figure 2C As shown, the portion of the semiconductor layer 20 covering the contact connection portion 40 is etched through the first opening 601 to form a shallow isolation trench 201 exposing the contact connection portion 40. In an exemplary embodiment, the portion of the semiconductor layer 20 covering the contact connection portion 40 may be removed by a dry etching process or a wet etching process, but is not limited thereto.

[0051] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the projection of the first opening 601 covers the projection of the contact connection portion 40. This arrangement is conducive to ensuring that the shallow isolation groove 201 formed by etching the semiconductor layer 20 can completely expose the contact connection portion 40, and ensure that a certain distance is maintained between the contact connection portion 40 and the semiconductor layer 20, thereby achieving good and reliable electrical isolation.

[0052] Step S130

[0053] A dielectric layer 70 is formed to cover the semiconductor layer 20 and the contact connection portion 40 . Figure 2D FIG. 1 is a diagram showing a specific structural example of a semiconductor structure provided in step S130 according to an embodiment of the present application.

[0054] In an exemplary embodiment, the dielectric layer 70 may be deposited on the surface of the semiconductor layer 20 and the contact connection portion 40 away from the stack structure 10 by, for example, CVD, PVD, ALD, or any combination thereof.

[0055] Exemplarily, the material of the dielectric layer 70 may be any one of silicon nitride and silicon oxide, but is not limited thereto. The dielectric layer 70 may also be other suitable materials.

[0056] because FIG. 2A to FIG. 2C The semiconductor layer 20 only shows two layers as an example. When the material of the dielectric layer 70 is the same as the material of a layer of the semiconductor layer 20 that is far away from the stacked structure 10, for example Figure 2D and subsequent Figure 2E In the figure, only one semiconductor layer 20 is shown, but actually the semiconductor layer 20 is two layers, wherein the layer of the semiconductor layer 20 far away from the stacked structure 10 has the same color as the dielectric layer 70 and therefore cannot be shown.

[0057] Since the gate line gap structure 30 of the semiconductor structure provided in step S110 has a protruding portion 301 protruding out of the stacked structure 10 along the stacking direction of the stacked structure 10 , the dielectric layer covering the semiconductor layer 20 and the contact connection portion 40 formed in step S130 also has a protruding morphology.

[0058] In the manufacturing process of semiconductor devices such as three-dimensional memory, in order to bring out the electrical properties of the channel structure 101 or the peripheral circuit structure 50 , it is necessary to planarize the surface of the dielectric layer 70 for subsequent preparation of metal wiring.

[0059] Step S140

[0060] In the exemplary embodiment of step S140 , the dielectric layer 70 may be polished and planarized by, for example, a chemical mechanical polishing (CMP) process.

[0061] Figure 2E FIG. 1 is a specific structural example of a semiconductor structure provided in step S140 according to an embodiment of the present application. The dielectric layer 70 should have a certain thickness requirement so that the remaining dielectric layer 70 after the planarization process can cover the protrusion 301 of the gate line gap structure 30. Therefore, along the stacking direction of the stacked structure 10, the thickness of the dielectric layer 70 should be at least greater than the dimension H (refer to FIG. 1 ) of the protrusion 301 of the gate line gap structure 30 protruding from the semiconductor layer 20. Figure 2A ).

[0062] The above method 1000 needs to be processed by chemical mechanical polishing to achieve the surface flattening of the dielectric layer 70, and has a high requirement on the thickness of the dielectric layer 70. The process flow is relatively complicated and the cost is high. Therefore, in order to reduce costs and save processes, some embodiments of the present application provide different from the above method. Figures 1 to 2E A method for preparing a semiconductor device is shown. Figure 3 FIG. 2 schematically shows a flow chart of a method 2000 for preparing a semiconductor device in another embodiment. Figure 3 As shown, method 2000 includes:

[0063] S210: providing a semiconductor structure, wherein the semiconductor structure includes a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line gap structure, wherein the gate line gap structure has a protrusion protruding from the stacked structure along a stacking direction of the stacked structure, and the semiconductor structure further includes a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion of the gate line gap structure;

[0064] S220: removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion;

[0065] S230: removing at least a portion of the protrusion; and

[0066] S240: forming a dielectric layer covering the semiconductor layer, the contact connection portion and the gate line gap structure.

[0067] It should be understood that the steps shown in method 2000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. In addition, some of the steps may be performed simultaneously or in different steps. Figure 3 Executed in the order shown.

[0068] FIG. 4A to FIG. 4D 2 is a cross-sectional schematic diagram of a method 2000 for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 4A to FIG. 4D The above steps S210 to S240 are further described.

[0069] Step S210

[0070] Figure 4A FIG. 2 is a specific structural example of a semiconductor structure provided in step S210 according to an embodiment of the present application. For example, Figure 4A Can be used with Figure 2A Exactly the same.

[0071] It should be noted that the following is only Figure 4A and Figure 2A Taking the same situation as an example, the semiconductor structure provided in step S110 can be fully applicable to step S210, but it should be understood that the present application is not limited to Figure 4A or Figure 2A The situation shown.

[0072] Step S220

[0073] At least a portion of the semiconductor layer 20 is removed to expose the contact connection portion 40 and the protrusion 301 .

[0074] According to one embodiment of the present application, Figure 4B As shown, a patterned mask layer 60 is formed on the surface of the semiconductor layer 20 away from the stacked structure 10, and the mask layer 60 has a first opening 601 and a second opening 602. The first opening 601 exposes a portion of the semiconductor layer 20 covering the contact connection portion 40, and the second opening 602 exposes a portion of the semiconductor layer 20 covering the gate line gap structure 30.

[0075] In an exemplary embodiment, the mask layer 60 is a photoresist layer, and a photolithography process can be used to form the first opening 601 and the second opening 602. The first opening 601 and the second opening 602 can be formed by the same process and method, that is, the first opening 601 and the second opening 602 can be formed simultaneously using the same mask.

[0076] Then, if Figure 4C As shown, the semiconductor layer 20 is etched through the first opening 601 and the second opening 602 to expose the contact connection portion 40 and the protrusion 301. In an exemplary embodiment, the semiconductor layer 20 may be etched through the first opening 601 and the second opening 602 using a dry etching process or a wet etching process, but is not limited thereto.

[0077] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the projection of the first opening 601 covers the projection of the contact connection portion 40. This arrangement is conducive to ensuring that the shallow isolation groove 201 formed by etching the semiconductor layer 20 can completely expose the contact connection portion 40, and ensure that a certain distance is maintained between the contact connection portion 40 and the semiconductor layer 20, thereby achieving good and reliable electrical isolation.

[0078] In an exemplary embodiment, the protrusion 301 has a first end away from the stacking structure 10 and a second end close to the stacking structure 10; on a plane perpendicular to the stacking direction, the projection of the second end covers the projection of the second opening 602, and the projection of the second opening 602 covers the projection of the first end. Exemplarily, the protrusion 301 may be similar to a raised hill, with a small first end (i.e., top end) away from the stacking structure 10 and a large second end (i.e., bottom end) close to the stacking structure 10.

[0079] For example, etching the semiconductor layer 20 through the first opening 601 and the second opening 602 may be performed simultaneously, so that the first end of the protrusion 301 away from the stacked structure 10 is also exposed while the contact connection portion 40 is exposed.

[0080] Step S230

[0081] After the contact connection portion 40 and the protrusion 301 are exposed in step S220 , step S230 is continued to remove at least a portion of the protrusion 301 . Figure 4C A specific structural example of a semiconductor structure provided in step S230 according to an embodiment of the present application is also shown.

[0082] For example, a wet etching process may be used to remove at least a portion of the protrusion 301. Since the contact connection portion 40 and the protrusion 301 are made of different materials and have different etching selectivities, when a wet etching process is used to remove at least a portion of the protrusion 301, the contact connection portion 40 will not be further etched.

[0083] Exemplarily, the material of the contact connection portion 40 is a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al), and the material of the protrusion 301 may, for example, include silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0084] In an exemplary embodiment, the raised portion 301 may be similar to a raised hill, which is small at the first end (i.e., the top end) away from the stacking structure 10 and large at the second end (i.e., the bottom end) close to the stacking structure 10. The projection of the bottom end covers the projection of the second opening 602, and the projection of the second opening 602 covers the projection of the top end. In other words, the size of the second opening 602 is between the top size and the bottom size of the raised portion 301. Such a setting can ensure that at least a portion of the top of the raised portion 301 is etched away through the second opening 602.

[0085] In an exemplary embodiment, after at least a portion of the protrusion 301 is removed, the remaining protrusion 301 protrudes from the semiconductor layer 20 along the stacking direction by a dimension h (refer to Figure 4C The enlarged part) is less than or equal to 150nm.

[0086] Step S240

[0087] A dielectric layer 70 is formed to cover the semiconductor layer 20 , the contact connection portion 40 and the gate line gap structure 30 . Figure 4D FIG. 1 is a diagram showing a specific structural example of a semiconductor structure provided in step S240 according to an embodiment of the present application.

[0088] In an exemplary embodiment, the dielectric layer 70 may be deposited on the surface of the semiconductor layer 20 , the contact connection portion 40 , and the gate line gap structure 30 away from the stack structure 10 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or any combination thereof.

[0089] Exemplarily, the material of the dielectric layer 70 may be any one of silicon nitride and silicon oxide, but is not limited thereto. The dielectric layer 70 may also be other suitable materials.

[0090] Since the protrusion 301 of the gate line gap structure 30 has been basically removed after step S230, the semiconductor structure has no obvious protrusion, and therefore the dielectric layer 70 formed in step S240 covering the semiconductor layer 20, the contact connection portion 40 and the gate line gap structure 30 also has no obvious protrusion morphology. Furthermore, in the manufacturing process of semiconductor devices such as three-dimensional memory, when the electrical properties of the channel structure 101 or the peripheral circuit structure 50 of the three-dimensional memory are extracted, the process of flattening the dielectric layer 70 by using, for example, a chemical mechanical polishing process can be omitted.

[0091] It is worth noting that, even in some cases, after step S230 , the raised portion 301 of the gate line gap structure 30 still does not meet the planarization requirement, it is sufficient to perform planarization correction on the dielectric layer 70 through a small amount of chemical mechanical polishing process.

[0092] In addition, since the protrusion 301 of the gate line gap structure 30 has been basically removed after step S230, the semiconductor structure has no obvious protrusion, and therefore, the thickness requirement of the dielectric layer 70 covering the semiconductor layer 20, the contact connection portion 40 and the gate line gap structure 30 is significantly reduced. Along the stacking direction of the stacked structure 10, the thickness of the dielectric layer 70 only needs to be greater than the dimension h (refer to the dimension h of the remaining protrusion 301 protruding from the semiconductor layer 20 along the stacking direction) of the semiconductor layer 20. Figure 4C The enlarged part of the image can be used.

[0093] The above disclosed content of the present application provides a method 2000 for preparing a semiconductor device. According to at least one embodiment of the present application, by adding a second opening 602 on the mask layer 60 to expose the raised portion 301 of the covering gate line gap structure 30 of the semiconductor layer 20, the raised portion 301 is exposed through the second opening 602 and the height of the raised portion 301 is reduced, thereby improving the morphology problem of the surface of the dielectric layer 70, thereby saving the chemical mechanical polishing process, and also reducing the thickness requirement of the dielectric layer 70, simplifying the method for preparing the semiconductor device, and saving the manufacturing cost.

[0094] Another aspect of the present application provides a semiconductor device. Figure 4D 4 is a cross-sectional view showing a semiconductor device 400 according to an embodiment of the present disclosure. Figure 4D The semiconductor device 400 is described in detail. The semiconductor device 400 can be manufactured by any of the above-mentioned manufacturing methods.

[0095] The semiconductor device 400 may include a stack structure 10 having a core region 110 and a contact connection region 120 .

[0096] The semiconductor device 400 further includes a contact connection portion 40 located in the contact connection region 120 and penetrating the contact connection region 120 , and a gate line gap structure 30 located in the core region 110 and penetrating the core region 110 .

[0097] The semiconductor device 400 further includes a semiconductor layer 20 , which covers the first side surface of the stacked structure 10 and is disconnected at the locations of the contact connection portion 40 and the gate line gap structure 30 . Figure 4D The semiconductor 20 is only shown as a one-layer structure by way of example. However, in some embodiments, the semiconductor layer 20 may include multiple layers of different materials. The material of the semiconductor layer 20 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0098] The semiconductor device 400 further includes a dielectric layer 70, which covers the semiconductor layer 20, the contact connection portion 40 and the gate line gap structure 30. Exemplarily, the material of the dielectric layer 70 may be any one of silicon nitride and silicon oxide, but is not limited thereto, and the dielectric layer 70 may also be other suitable materials.

[0099] The gate line gap structure 30 further includes a portion (ie, the protrusion 301) extending into the dielectric layer 70. For example, the portion of the gate line gap structure 30 extending into the dielectric layer 70 has a dimension h' (refer to Figure 4DThe enlarged part) is less than or equal to 150nm.

[0100] like Figure 4D As shown, the semiconductor device 400 may further include a peripheral circuit structure 50 , which is located on a second side of the stacked structure 10 opposite to the first side and is electrically connected to the core region 110 and the contact connection region 120 through a plurality of interconnect contacts 501 .

[0101] In some embodiments of the present application, the contact connection portion 40 penetrates the stacked structure 10 and serves as an electrical connection. For example, the contact connection portion 40 may be prepared by first forming a conductive channel, and then filling the conductive channel with a conductive material to form a conductive channel column. For example, the material of the conductive channel column may be a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). In some embodiments, the contact connection portion 40 may only include a solid conductive channel column; in other embodiments, such as Figure 4D As shown, the contact connection portion 40 may further include a filling portion 401 , that is, the filling portion 401 is made inside the conductive channel column, and the material of the filling portion 401 may be an insulating material.

[0102] Since the contents and structures involved in the preparation methods 1000 and 2000 described above can be fully or partially applied to the semiconductor device described here, the related or similar contents will not be repeated.

[0103] Although an exemplary method of manufacturing and structure of a semiconductor device is described herein, it is understood that one or more features may be omitted, replaced, or added to the structure of the semiconductor device. For example, the peripheral circuit structure 50 may be configured as desired.

[0104] According to a semiconductor structure provided by an embodiment of the present application, by controlling the size of the portion of the gate line gap structure 30 extending into the dielectric layer 70 along the stacking direction to be within a preset threshold range, the problem of excessive undulation of the surface of the dielectric layer 70 covering the semiconductor layer 20, the contact connection portion 40 and the gate line gap structure 30 is improved, the chemical mechanical polishing process is saved, and the thickness requirement for the dielectric layer 70 is reduced, thereby simplifying the preparation method of the semiconductor device and saving manufacturing costs.

[0105] Some embodiments of the present application also provide a memory system. Figure 5 is a block diagram of a system 10 having a memory system 12 according to an exemplary embodiment of the present application.

[0106] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the memory system 12 located therein). Figure 5 As shown, the system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0107] The three-dimensional memory 14 may include a semiconductor device described in any embodiment of the present application, for example, Figure 4DThe semiconductor device 400 is shown. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0108] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 6AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 5 The host 18 in the memory card connector 24 is coupled. Figure 6B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 5 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0109] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions in the present application.

Claims

1. A method for preparing a semiconductor device, wherein: The method comprises: A semiconductor structure is provided, wherein the semiconductor structure comprises a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line gap structure, wherein the gate line gap structure has a protrusion protruding from the stacked structure along a stacking direction of the stacked structure, and the semiconductor structure further comprises a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion of the gate line gap structure; removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion; removing at least a portion of the raised portion; and A dielectric layer is formed to cover the semiconductor layer, the contact connection portion and the gate line gap structure.

2. The method according to claim 1, wherein: Removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion portion comprises: forming a patterned mask layer on a surface of the semiconductor layer away from the stacked structure, the mask layer comprising a first opening and a second opening, wherein the first opening exposes a portion of the semiconductor layer covering the contact connection portion, and the second opening exposes a portion of the semiconductor layer covering the gate line gap structure; and The semiconductor layer is etched through the first opening and the second opening to expose the contact connection portion and the protrusion.

3. The method according to claim 2, wherein: On a plane perpendicular to the stacking direction, a projection of the first opening covers a projection of the contact connection portion.

4. The method according to claim 2, wherein: The protrusion has a first end away from the stacking structure and a second end close to the stacking structure; as well as On a plane perpendicular to the stacking direction, a projection of the second end covers a projection of the second opening, and a projection of the second opening covers a projection of the first end.

5. The method according to any one of claims 1 to 4, wherein: After at least a portion of the protrusion is removed, a size of the protrusion along the stacking direction is less than or equal to 150 nm.

6. A semiconductor device comprising: A stacked structure having a core region and a contact connection region; A contact connection portion, located in the contact connection area and passing through the contact connection area; A gate line gap structure, located in the core area and passing through the core area; a semiconductor layer covering the first side surface of the stacked structure and being disconnected at the positions of the contact connection portion and the gate line gap structure; as well as A dielectric layer covers the semiconductor layer, the contact connection portion and the gate line gap structure.

7. The semiconductor device according to claim 6, wherein: The gate line gap structure also includes a portion extending into the dielectric layer, The size of the portion of the gate line gap structure extending into the dielectric layer along the stacking direction is less than or equal to 150 nm.

8. The semiconductor device according to claim 6, wherein: The material of the semiconductor layer includes a polysilicon layer, and the material of the dielectric layer includes silicon dioxide.

9. The semiconductor device according to claim 6, wherein: The semiconductor device further comprises: The peripheral circuit structure is located on a second side surface of the stacked structure opposite to the first side surface and is electrically connected to the core area and the contact connection area.

10. A memory system, characterized in that: include: A three-dimensional memory comprising at least one semiconductor device according to any one of claims 6 to 9; as well as The controller is coupled to the three-dimensional memory and is used to control the three-dimensional memory to store data.

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