Mask plate for etching square array pattern and method for etching square array pattern by using mask plate

Abstract

The invention discloses a mask plate for etching a square array pattern and a method for etching the square array pattern by using the mask plate, and the mask plate and the method for etching the square array pattern by dry etching avoid the use of photoresist or a polar solvent and the like, improve the containment of an MEMS (Micro-Electro-Mechanical System) process, reduce the production cost and improve the production efficiency. More novel films with excellent performance can be applied to microelectronic devices; the array pattern manufactured by using the layout etching method can be compatible in any MEMS manufacturing factory, alignment marks of the substrate and the mask can be compatible in a first layer circuit wiring process, and the manufacturing cost is saved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a mask plate for etching square array patterns and a method for etching square array patterns using the mask plate. Background Art

[0002] Etching is an important process in the manufacture of semiconductor devices and integrated circuits, and is an important means of patterning in integrated circuit devices. Usually, the etching process is carried out after the photolithography technology, and the device structure pattern generated by the photolithography is prepared on the underlying substrate through etching. Simply put, the photolithography technology is first used to react the photoresist under light source or laser exposure, and the pattern to be removed is revealed in the developer; then the etching process is used to remove the part of the pattern that is not blocked by the photoresist, and then the photoresist is removed. Etching includes wet etching and dry etching. Wet etching uses various corrosive solutions to remove the pattern protected by the photoresist by immersion; while dry etching is completed with the help of special etching technology using equipment, including reactive ion beam etching (RIE) technology, inductively coupled plasma etching (ICP) technology, and ion beam etching (IBE) technology.

[0003] The above etching scheme is a common strategy in the manufacture of semiconductor devices and integrated circuits. However, with the continuous emergence of high-performance new materials, MEMS manufacturing processes are constantly challenging, because the physical and chemical properties of new materials are often not able to be manufactured with existing MEMS (for example, some materials are easily corroded by photoresists or polar solvents, etc.), so process incompatibility has become a barrier restricting the use of new materials in microelectronic chips. For example, in recent years, halide perovskite materials with suitable band gaps, high carrier mobility, high absorption coefficients, low exciton binding energy, and long carrier lifetimes have attracted global attention. Their quantum dots, nanowires and other structures have become a new generation of optoelectronic functional materials, and have excellent performance in light-emitting diodes, light sensors, memristors, etc., but they are easily corroded by polar solutions (water, ethanol, acetone, photoresists, etc.); for example, MnBi2Te4 materials, which are antiferromagnetic topological insulators, have strange states such as quantum anomalous Hall insulators, axion insulators, and Weyl semimetals. Not only are they attractive in basic research, they also have great potential in practical applications, but this functional material has the characteristic of being easily corroded by polar solvents. With the development of science and technology, the number and types of new materials of this type are becoming more and more diverse. In order to avoid contact with solvents of the same polarity, photolithography and wet etching solutions need to be excluded first, so only dry etching solutions can be used. However, a mask plate is needed to perform graphic processing on the material by blocking.

[0004] Usually, a hollow mask plate has a shielded and protected portion that needs to be patterned, and an exposed portion that is to be removed; a characteristic is that the pattern of the non-hollowed portion of the mask plate must be continuous, that is, the pattern of the shielded and protected portion is continuous; conversely, if the pattern of the hollowed portion is continuous, and the pattern of the shielded and protected portion is incoherent, the mask plate with such a pattern design itself does not exist. Based on the above background, the present invention proposes a design method for etching a square array mask plate pattern and a method for etching a square array mask plate pattern using the same. Summary of the invention

[0005] The object of the present invention is to provide a mask plate for etching square array patterns, and at the same time, providing a method for etching square array patterns using the mask plate is the second invention object of the present invention.

[0006] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical solutions:

[0007] A mask plate for etching a square array pattern, wherein the number of etching square array points of the etching square array pattern is N*N, the size of the dot array is a*a square, and the resolution is b;

[0008] The mask plate includes a first layer layout and a second layer layout;

[0009] The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, including:

[0010] 1) Functional film and circuit area, and blank area, the blank area is the layout area for drawing other leads and pads of the circuit, the functional film and circuit area (purple area) is a square centered at the layout center (0, 0), with a side length of N*b;

[0011] 2) The functional film and the four corners outside the circuit area are placed with the alignment marks of the etching array, and the center position of the alignment mark is c away from the center position (0, 0) of the layout, where c>Nb / 2 1 / 2 The angle between the center of the layout and the adjacent lines connecting the centers of the four alignment marks is 90°, and the hierarchical structure of the etching alignment marks can be from a cross of hundreds of microns to a cross of several microns;

[0012] 3) Set on the first level Figure 4The alignment mark at the corner is used for alignment between the mask and the substrate. The alignment mark is a cross-shaped structure with a multi-precision level design. The size of the cross can range from thousands of microns to microns. The next level is placed at the blank positions at the four corners of the previous level. The alignment mark level is formulated according to the accuracy of the etching pattern. If the accuracy of the layout pattern is hundreds of microns, the alignment mark cross can be drawn from thousands of microns to ten microns. The first level of the layout cross is thousands of microns (millimeters), and the position between the mask and the substrate can be judged by the naked eye for the first time; the second level is hundreds of microns, which can be judged by an optical microscope; the third level is ten microns; the fourth level is several microns; and so on. According to the increasing level of accuracy, each level of cross is located at the blank positions at the four corners of the previous level and the cross.

[0013] The second layer of pattern is used to make a mask plate for etching, including:

[0014] 4) including hollow areas and mask areas, which correspond to the functional film and circuit areas and blank areas of the first layer layout respectively; the hollow areas are the etched area mask area layout: the etched mask area layout is a grating stripe structure, wherein each stripe has a length of N*b and a width of a, with a total of N stripes, and the center of the N stripes is the layout center (0, 0);

[0015] 5) The etching array etching alignment marks are placed at the four corners of the etching mask area, which are consistent with the etching alignment marks of the first layer layout, and are used for position calibration between the etching area of ​​the mask plate and the substrate;

[0016] 6) Four-corner alignment marks: consistent with the four-corner alignment marks of the first layer layout, used for direct position alignment between the mask plate and the substrate.

[0017] A method for etching a square array pattern using a mask for etching a square array pattern comprises the following steps:

[0018] S1: Using the first layer layout:

[0019] S11: manufacturing a circuit in the lower layer of the functional thin film array region on the substrate, and also patterning each alignment mark;

[0020] S12: After the lower circuit and alignment mark of the array point are patterned, a functional film is deposited on the upper layer of the circuit. The deposition method of the functional film can be made by a thermal evaporation method, a coating method, etc., which is specifically set according to the specific functional film production situation, and will not be described in detail here;

[0021] S2: Make the second layer of the pattern mask and perform etching

[0022] S21: The mask plate material may be a metal material such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. The removed area of ​​the mask plate is the hollowed area, and the retained area is the mask area.

[0023] S22: Alignment of the mask plate and the substrate: The first alignment can be judged by naked eyes. According to the thousand-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the relative position of the mask plate and the substrate is moved, and the mask plate and the substrate are brought into contact for the first time. Then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform. According to the hundred-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the alignment between the mask plate and the substrate is roughly adjusted. The substrate transfer platform is used again to fine-tune the alignment between the mask plate and the substrate according to the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate.

[0024] S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level;

[0025] S24: After the alignment is completed, the mask and the substrate are fixed by using resin glue or a pressure spring;

[0026] S25: placing the fixed mask plate and substrate together in an etcher to perform the first etching;

[0027] S3: After the first etching is completed, the mask is removed, rotated 90 degrees, and the mask and substrate are aligned again, and step S2 is repeated. The etching of the square array dot square array pattern is completed.

[0028] As a further preferred embodiment of the present invention, in S11, the production of circuits and alignment marks does not involve corrosion by photoresist or polar solvents, and the general MEMS process is used to use the first layer of the layout as a photolithography layout to complete the graphic process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching; or, the first layer of the layout can be made into a mask plate, which is attached to the surface of the substrate, and the thin film production of the circuit and alignment mark is completed using a physical vapor deposition process.

[0029] As a further preferred embodiment of the present invention, the physical vapor deposition process includes any one of an electron beam evaporation coating process, a thermal evaporation coating process, and a magnetron sputtering coating process.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The present invention proposes for the first time a mask plate and method for dry etching a rectangular array dot matrix array dot pattern;

[0032] 2. The present invention avoids the use of photoresist or polar solvents, improves the MEMS process tolerance, and enables more new films with superior performance to be applied in microelectronic devices;

[0033] 3. The array pattern produced by the layout etching method of the present invention can be compatible with any MEMS manufacturing factory, and the alignment marks of the substrate and the mask can be compatible with the first-layer circuit wiring process, saving manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 is the square array point matrix to be completed;

[0036] Figure 2 It is the first level layout design plan and instructions;

[0037] Figure 3 It is the second-level layout design plan and instructions;

[0038] Figure 4 It is a schematic diagram of the process of etching square array graphics of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention is described in detail below, but the following embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by those skilled in the art without making creative work belong to the scope of protection of the present invention.

[0040] Example 1

[0041] A mask plate for etching a square array pattern, the etching square array pattern is as follows Figure 1 The number of dots in the etched square array shown is N*N, the dot size is a*a square, and the resolution is b.

[0042] The mask plate includes Figure 2 The first layer layout shown and Figure 3 The second layer layout shown;

[0043] The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, including:

[0044] 1) Functional film and circuit area (purple area), and blank area, the blank area is the layout area for drawing other leads and pads of the circuit, the functional film and circuit area (purple area) is a square centered on the layout center (0,0), with a side length of N*b (N is the number of dot matrix horizontal / columns, b is the dot matrix resolution), the circuit layout design scheme of the lower layer of the film and the circuit leads outside the film layer are formulated according to the dot matrix and device structure of the functional film, and the layout does not provide a specific design scheme; only the purple area is used to draw the functional film and the circuit area of ​​the lower layer of the film;

[0045] 2) The functional film and the four corners outside the circuit area (purple area) are placed with the alignment marks of the etching array. The distance between the center of the alignment mark and the center of the layout (the center of the purple area) (0, 0) is c, where c>Nb / 2 1 / 2 The angle between the center of the layout and the adjacent lines connecting the centers of the four alignment marks is 90°, and the hierarchical structure of the etching alignment marks can be from a cross of hundreds of microns to a cross of several microns;

[0046] 3) Set on the first level Figure 4 Angle alignment mark ( Figure 2 Right), used for alignment between the mask and the substrate. The alignment mark is a cross-shaped structure with a multi-precision level design. The size of the cross can range from thousands of microns to microns. The next level is placed in the blank positions at the four corners of the previous level. The alignment mark level is formulated according to the accuracy of the etching pattern. If the accuracy of the layout pattern is hundreds of microns, the alignment mark cross can be drawn from thousands of microns to ten microns. The first level of the cross in the layout is thousands of microns (millimeter level), and the position between the mask and the substrate can be judged by the naked eye for the first time; the second level is hundreds of microns, which can be judged by an optical microscope; the third level is ten microns; the fourth level is several microns; and so on. According to the increasing level of accuracy, each level of cross is located in the blank positions at the four corners of the previous level and the cross;

[0047] Instructions for use: First, place the mask on the surface of the substrate, and the position can be determined by naked eyes according to the first-level thousand-micron cross-shaped structure; secondly, use the substrate transfer table to coarsely adjust the position between the mask and the substrate according to the second-level hundred-micron cross-shaped structure; then, use the substrate transfer table to fine-tune the position of the mask and the substrate according to the third-level ten-micron and fourth-level several-micron cross-shaped structures.

[0048] The second layer of the pattern (mask) is used to make the mask for etching, such as Figure 3 As shown, including:

[0049] 4) includes a hollow area (red area) and a mask area (white area), which correspond to the functional film and circuit area and the blank area of ​​the first layer layout respectively; the hollow area is the mask area layout of the etching area (such as Figure 3Left): The etching mask area layout is a grid-like stripe structure, where each stripe length is N*b (N is the number of dot array horizontal / column numbers, b is the resolution of the square array dot), width is a (the side length of the square array dot), there are N stripes in total, and the center of the N stripes is the center of the layout (0, 0);

[0050] 5) The etching array etching alignment marks are placed at the four corners of the etching mask area, which are consistent with the etching alignment marks of the first layer layout, and are used for position calibration between the etching area of ​​the mask plate and the substrate;

[0051] 6) Four corner alignment marks (such as Figure 3 As shown on the right): It is consistent with the four corner alignment marks of the first layer layout and is used for direct position alignment between the mask plate and the substrate.

[0052] Example 2

[0053] The method of etching a square array pattern using a mask for etching a square array pattern in this embodiment includes the following steps:

[0054] S1: Using the first layer layout:

[0055] S11: The circuit of the lower layer of the functional thin film array area is made on the substrate, and each alignment mark is also patterned. The production of the circuit and the alignment mark does not involve corrosion by photoresist or polar solvents. Therefore, the general MEMS process can be used to use the first layer of the layout as the photolithography layout to complete the patterning process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching (wet / dry etching); or, the first layer of the layout can be made into a mask plate, attached to the surface of the substrate, and the thin film production of the circuit and the alignment mark is completed by using a physical vapor deposition process (electron beam evaporation coating process, thermal evaporation coating process, magnetron sputtering coating process);

[0056] S12: After the lower circuit and alignment mark of the array point are patterned, a functional film is deposited on the upper layer of the circuit. The deposition method of the functional film can be made by a thermal evaporation method, a coating method, etc., which is specifically set according to the specific functional film production situation, and will not be described in detail here;

[0057] S2: Make the second layer of the pattern mask and perform etching

[0058] S21: The mask material can be a metal material such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. The red area of ​​the layout is the removed area (hollow area) of the mask, and the white area is the retained area (mask area);

[0059] S22: Alignment of the mask plate and the substrate: The first alignment can be judged by naked eyes. According to the thousand-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the relative position of the mask plate and the substrate is moved, and the mask plate and the substrate are brought into contact for the first time. Then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform. According to the hundred-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the alignment between the mask plate and the substrate is roughly adjusted. The substrate transfer platform is used again to fine-tune the alignment between the mask plate and the substrate according to the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate.

[0060] S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level;

[0061] S24: After the alignment is completed, the mask and the substrate are fixed by using resin glue or a pressure spring;

[0062] S25: Place the fixed mask plate and substrate in the etcher for the first etching. The specific equipment, etching parameters and other details used in the etching process are related to the physical and chemical properties of the etched film. The process needs to be adjusted according to the specific situation. This description does not provide specific instructions.

[0063] S3: After the first etching is completed, the mask is removed, rotated 90 degrees, and the mask and substrate are aligned again, and step S2 is repeated. The etching of the square array dot square array pattern is completed.

[0064] The schematic diagram of the process of etching the square array pattern of the present invention is as follows Figure 4 shown.

[0065] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A mask plate for etching a square array pattern, characterized in that: The number of etched square array points of the etched square array pattern is N*N, the size of the point array is a*a square, and the resolution is b; The mask plate includes two layers of layout, a first layer of layout and a second layer of layout; The first layer of the layout is used to make various alignment marks and lower layer circuits of functional films, including: 1) Functional film and circuit area, and blank area, the blank area is the layout area for drawing other leads and pads of the circuit, the functional film and circuit area (purple area) is a square centered at the layout center (0, 0), with a side length of N*b; 2) The functional film and the four corners outside the circuit area are placed with the alignment marks of the etching array, and the center position of the alignment mark is c away from the center position (0, 0) of the layout, where c>Nb / 2 1 / 2 The angle between the center of the layout and the adjacent lines connecting the centers of the four alignment marks is 90°, and the hierarchical structure of the etching alignment marks can be from a cross of hundreds of microns to a cross of several microns; 3) The alignment marks set at the four corners of the first layer are used for alignment between the mask and the substrate. The alignment marks are cross-shaped structures with multi-precision level design. The size of the cross can range from thousands of microns to microns. The next level is placed at the blank positions at the four corners of the previous level. The second layer of pattern is used to make a mask plate for etching, including: 4) including hollow areas and mask areas, which correspond to the functional film and circuit areas and blank areas of the first layer layout respectively; the hollow areas are the etched area mask area layout: the etched mask area layout is a grating stripe structure, wherein each stripe has a length of N*b and a width of a, with a total of N stripes, and the center of the N stripes is the layout center (0, 0); 5) The etching array etching alignment marks are placed at the four corners of the etching mask area, which are consistent with the etching alignment marks of the first layer layout, and are used for position calibration between the etching area of ​​the mask plate and the substrate; 6) Four-corner alignment marks: consistent with the four-corner alignment marks of the first layer layout, used for direct position alignment between the mask plate and the substrate.

2. A method for etching a square array pattern using a mask for etching a square array pattern, characterized in that: The following steps are involved: S1: Using the first layer layout: S11: manufacturing a circuit in the lower layer of the functional thin film array region on the substrate, and also patterning each alignment mark; S12: After the lower circuit and alignment mark of the array point are patterned, a functional film is deposited on the upper layer of the circuit. The deposition method of the functional film can be made by a thermal evaporation method, a coating method, etc., which is specifically set according to the specific functional film production situation, and will not be described in detail here; S2: Make the second layer of the pattern mask and perform etching S21: The mask plate material may be a metal material such as stainless steel, or a silicon-based wafer or a ceramic thin film material such as silicon nitride and silicon dioxide. The removed area of ​​the mask plate is the hollowed area, and the retained area is the mask area. S22: Alignment of the mask plate and the substrate: The first alignment can be judged by naked eyes. According to the thousand-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the relative position of the mask plate and the substrate is moved, and the mask plate and the substrate are brought into contact for the first time. Then, the position of the mask plate and the substrate is continued to be adjusted using the substrate transfer platform. According to the hundred-micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate, the alignment between the mask plate and the substrate is roughly adjusted. The substrate transfer platform is used again to fine-tune the alignment between the mask plate and the substrate according to the ten-micron-level and micron-level cross-shaped alignment marks at the four corners of the mask plate and the substrate. S23: Etching position alignment confirmation: After the positions of the mask plate and the substrate are adjusted, the substrate transfer platform is used to observe whether the alignment marks at the four corners of the functional film and the circuit area are aligned at each level; S24: After the alignment is completed, the mask and the substrate are fixed by using resin glue or a pressure spring; S25: placing the fixed mask plate and substrate together in an etcher to perform the first etching; S3: After the first etching is completed, the mask is removed, rotated 90 degrees, and the mask and substrate are aligned again, and step S2 is repeated. The etching of the square array dot square array pattern is completed.

3. The method for etching a square array pattern using a mask according to claim 2, characterized in that: In S11, the production of circuits and alignment marks does not involve corrosion by photoresist or polar solvents. The general MEMS process is used to take the first layer of the layout as the photolithography layout to complete the graphic process: photolithography - development - deposition of conductive metal layer - stripping or deposition of conductive metal layer - photolithography - development - etching; or, the first layer of the layout can be made into a mask plate, which is attached to the surface of the substrate, and the thin film production of the circuit and alignment mark is completed using a physical vapor deposition process.

4. The method for etching a square array pattern using a mask according to claim 3, characterized in that: The physical vapor deposition process includes any one of an electron beam evaporation coating process, a thermal evaporation coating process, and a magnetron sputtering coating process.

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